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CN105262480A - System for recovering clock signal from high-speed serial signals - Google Patents

System for recovering clock signal from high-speed serial signals Download PDF

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Publication number
CN105262480A
CN105262480A CN201510690899.9A CN201510690899A CN105262480A CN 105262480 A CN105262480 A CN 105262480A CN 201510690899 A CN201510690899 A CN 201510690899A CN 105262480 A CN105262480 A CN 105262480A
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CN
China
Prior art keywords
filter
clock signal
speed serial
serial signals
controlled oscillator
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Pending
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CN201510690899.9A
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Chinese (zh)
Inventor
赵猛
张红英
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JIANGSU LVYANG ELECTRONIC INSTRUMENT GROUP CO Ltd
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JIANGSU LVYANG ELECTRONIC INSTRUMENT GROUP CO Ltd
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Priority to CN201510690899.9A priority Critical patent/CN105262480A/en
Publication of CN105262480A publication Critical patent/CN105262480A/en
Pending legal-status Critical Current

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Abstract

The invention belongs to the field of signal processing, in particular to a system for recovering a clock signal from high-speed serial signals. The system comprises a phase detector, a filter and a voltage controlled oscillator. The phase detector is connected with the filter. The filter is connected with the voltage controlled oscillator. The voltage controlled oscillator is connected with the phase detector. The phase detector is a Hilbert transform phase detector. According to the invention, the system can accurately recover a clock signal from high-speed serial signals by using phase-locked loop technology, provides guarantee for subsequent data processing, can meet the requirement of growing data rate, and can also meet higher requirements of the data transmission rate and processing.

Description

A kind of system of recovered clock signal from high-speed serial signals
Technical field
The invention belongs to signal transacting field, be specifically related to a kind of system of recovered clock signal from high-speed serial signals.
Background technology
In recent years, along with the develop rapidly of microprocessor and IC technology, the data volume of required process increases with showing as explosion type.Along with the demand of people constantly promotes, to transmission rate and the process proposition requirements at the higher level of data.The phase-locked loop applied in systems in practice is necessarily band-limited, and loop filter shows as low-pass characteristic.This means that signal medium and low frequency phase error can be filtered, and HFS still retains.For system designer, identify and analyze the key that this part shake is design system, elevator system performance.As a kind of measuring instrument, the levels of precision of oscilloscope time domain measurement is closely related with triggering, but cannot obtain required external signal in some cases as triggering, even if can obtain external signal, the shake of this signal itself also can be introduced into measurement.Like this in order to the temporal characteristics of measuring-signal, reasonable method recovers a clock exactly.Usually this clock adopts PHASE-LOCKED LOOP PLL TECHNIQUE to recover from source signal, and the optimum configurations of phase-locked loop as far as possible close to the optimum configurations of receiving terminal phase-locked loop, will be shaken and structure eye as measurement with this clock figurereference clock be reasonable because the clock of this clock and receiving terminal is basically identical.Digital fluorescence oscilloscope is as structure eye figurewith measurement eye figurethe powerful of parameter and shake needs to realize a phase-locked loop therein.And software phase-lock loop is due to its various advantages, become eye figurethe clock recovery techniques of structure and jitter analysis aspect main flow.
Summary of the invention
The object of the present invention is to provide a kind of system of recovered clock signal from high-speed serial signals, this system employing PHASE-LOCKED LOOP PLL TECHNIQUE can from high-speed serial signals by recovering clock signals out.
To achieve these goals, the present invention adopts following technical scheme: a kind of system of recovered clock signal from high-speed serial signals, comprise phase discriminator, filter and voltage controlled oscillator, described phase discriminator is connected with filter, described filter is connected with voltage controlled oscillator, and described voltage controlled oscillator is connected with phase discriminator; Described phase discriminator is Hilbert transform phase discriminator.
Further, described filter adopts first-order loop filter.
Further, described first-order loop filter is active proportional-integral filter.
Further, described voltage controlled oscillator adopts waveform synthesizer DCO.
Further, described phase discriminator, filter and voltage controlled oscillator are software module, realize in the microprocessor.
Further, described microprocessor adopts S3C2440A chip.
The system of recovered clock signal from high-speed serial signals of the present invention, this system adopts PHASE-LOCKED LOOP PLL TECHNIQUE can be recovered by inaccurate clock signal from high-speed serial signals, for follow-up data processing provides safeguard, the requirement of growing data rate can be met, also can meet people and requirements at the higher level are proposed to the transmission rate of data and process.
Accompanying drawing explanation
fig. 1for modular structure of the present invention is illustrated figure;
fig. 2for Hilbert transform phase discriminator structure figure;
fig. 3for software PLL algorithm flow figure;
fig. 4for software phase-lock loop clock recovery figure.
Embodiment
Below in conjunction with embodiment, method of the present invention is described in detail.
as Fig. 1shown in, a kind of system of recovered clock signal from high-speed serial signals, comprises phase discriminator, filter and voltage controlled oscillator, and described phase discriminator is connected with filter, and described filter is connected with voltage controlled oscillator, and described voltage controlled oscillator is connected with phase discriminator; Described phase discriminator is Hilbert transform phase discriminator.
Described filter adopts first-order loop filter.
Described first-order loop filter is active proportional-integral filter.
Described voltage controlled oscillator adopts waveform synthesizer DCO.
Described phase discriminator, filter and voltage controlled oscillator are software module, realize in the microprocessor.
Described microprocessor adopts S3C2440A chip.
1, Hilbert transform phase discriminator
Software the simplest attainable phase discriminator is multiplication phase discriminator, but owing to being single channel, its output accuracy is comparatively large by the amplitude influences of input signal, and arcsin function exists phase fuzzy problem, so adopt the Hilbert transform phase discriminator of two-way herein simultaneously.So-called Hilbert transform phase discriminator as Fig. 2shown in, its critical component is Hilbert transformer, and it is the phase shift 90 degree of input sinusoidal signal.To see below, and utilize triangle geometry to calculate, the output phase error signal θ of Hilbert transform phase discriminator can be obtained e.This kind of phase discriminator uses DCO to produce two input signals: signal I=cosW in the same way 0t, orthogonal signalling Q=sinW 0t, as accompanying drawing 2shown in, u 1for input signal, for the signal after phase shift 900.Utilize triangulo operation:
cos θ e = Iu 1 + Q u ^ 1 , sin θ e = I u ^ 1 - Q u 1
Calculate phase error theta esine and cosine value, be divided by and obtain tan θ e, then calculate arc tangent tan θ by digital algorithm e -1, thus obtain phase error theta e.
2, loop filter
Loop filter adopts the active proportional-integral filter of single order, realizes more convenient.The transfer function of active proportional-integral filter is for obtaining the roughly the same digital filter of function, needing F (s) to be transformed into z territory and obtaining F (z).Order be updated to the z territory expression formula that just can obtain transfer function in F (s):
F ( z ) = b 0 + b 1 z - 1 1 + az - 1
Wherein a=-1, b 0 = T 2 τ 1 ( 1 + 2 τ 2 T ) , b 1 = T 2 τ 1 ( 1 - 2 τ 2 T ) ,
Can see in expression formula and comprise parameter τ 1and τ 2, T can value be 1.Transform in time domain, the output of filter is:
u f(n)=-au f(n-1)+b 0u d(n)+b 1u d(n-1)
This recurrence formula is easy to realize in software.
3, waveform synthesis DCO
Can use software simulating easily, such DCO, by the data in reference to storage, produces sinusoidal or cosine wave.Solve SIN function with look-up table, and directly need not calculate Taylor series and Chebyshev polynomials, computational speed can increase substantially.The output signal of loop filter can produce corresponding wave form output by control DCO, and DCO goes to search corresponding numerical value for exporting according to the phase place of current input in fact.DCO can produce the data that sine or cosine wave also can adjust storage and produce other waveform, is the most simply square wave.
4, software phase-lock loop implementation algorithm
Continuous time is the derivation of above-mentioned Hilbert transform phase discriminator draw in situation, with needing its discretization during software simulating, if T is the sampling interval.Suppose that input signal is
u 1(nT)=Asin(ω 0nT+θ e(nT)),I=cosω 0(nT)
Then
u ^ 1 ( n T ) = A c o s ( ω 0 n T + θ e ( n T ) ) , Q = sinω 0 ( n T )
Can push away through calculating,
cosθ e ( n T ) = Iu 1 ( n T ) + Q u ^ 1 ( n T )
sinθ e ( n T ) = I u ^ 1 ( n T ) - Qu 1 ( n T )
Finally exported
u d ( n T ) = θ e ( n T ) = arctan ( sinθ e ( n T ) cosθ e ( n T ) )
The output of DCO is controlled by the output fu of loop filter, and within a time interval, DCO exports phase delta θ 2=[ω 0+ K 0(nT)] T, wherein ω 0t is normal phase increment K 0u f(nT) T is the phase place change caused by phase difference.In the phase place in next moment be
θ 2((n+1)T)=θ 2(nT)+[ω 0+K 0u f(nT)]T
Software obtains output waveform value u according to this phase place 2((n+1) T).
Software PLL algorithm flow figureas accompanying drawing 3shown in.
accompanying drawing 4it is the clock that software phase-lock loop recovers from serial data.

Claims (6)

1. the system of a recovered clock signal from high-speed serial signals, it is characterized in that: comprise phase discriminator, filter and voltage controlled oscillator, described phase discriminator is connected with filter, and described filter is connected with voltage controlled oscillator, and described voltage controlled oscillator is connected with phase discriminator; Described phase discriminator is Hilbert transform phase discriminator.
2. the system of recovered clock signal from high-speed serial signals according to claim 1, is characterized in that: described filter adopts first-order loop filter.
3. the system of recovered clock signal from high-speed serial signals according to claim 2, is characterized in that: described first-order loop filter is active proportional-integral filter.
4. the system of recovered clock signal from high-speed serial signals according to claim 1, is characterized in that: described voltage controlled oscillator adopts waveform synthesizer DCO.
5. the system of recovered clock signal from high-speed serial signals according to claim 1, is characterized in that: described phase discriminator, filter and voltage controlled oscillator are software module, realize in the microprocessor.
6. the system of recovered clock signal from high-speed serial signals according to claim 5, is characterized in that: described microprocessor adopts S3C2440A chip.
CN201510690899.9A 2015-10-22 2015-10-22 System for recovering clock signal from high-speed serial signals Pending CN105262480A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510690899.9A CN105262480A (en) 2015-10-22 2015-10-22 System for recovering clock signal from high-speed serial signals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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CN105262480A true CN105262480A (en) 2016-01-20

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Citations (8)

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Publication number Priority date Publication date Assignee Title
US5953386A (en) * 1996-06-20 1999-09-14 Lsi Logic Corporation High speed clock recovery circuit using complimentary dividers
CN1382995A (en) * 2002-04-24 2002-12-04 清华大学 Digital measuring method of frequency and phase
CN1561023A (en) * 2004-03-04 2005-01-05 北京清华华环电子股份有限公司 Digital clock recovery method and its circuit
CN1968019A (en) * 2005-11-16 2007-05-23 弥亚微电子(上海)有限公司 All-digital phase-lock loop used for precision testing of city electricity
CN101183869A (en) * 2006-11-17 2008-05-21 卓联半导体有限公司 Boucle a verrouillage de phase numerique
CN101582692A (en) * 2009-06-12 2009-11-18 东南大学 Method for improving performances of digital phase-locked loops
CN101986568A (en) * 2010-10-22 2011-03-16 江苏锦丰电子有限公司 Steady state phase-locking error-free phase locking system and phase locking method
CN102346443A (en) * 2011-08-17 2012-02-08 北斗天汇(北京)科技有限公司 1PPS (pulse per second) latch and control method

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5953386A (en) * 1996-06-20 1999-09-14 Lsi Logic Corporation High speed clock recovery circuit using complimentary dividers
CN1382995A (en) * 2002-04-24 2002-12-04 清华大学 Digital measuring method of frequency and phase
CN1561023A (en) * 2004-03-04 2005-01-05 北京清华华环电子股份有限公司 Digital clock recovery method and its circuit
CN1968019A (en) * 2005-11-16 2007-05-23 弥亚微电子(上海)有限公司 All-digital phase-lock loop used for precision testing of city electricity
CN101183869A (en) * 2006-11-17 2008-05-21 卓联半导体有限公司 Boucle a verrouillage de phase numerique
CN101582692A (en) * 2009-06-12 2009-11-18 东南大学 Method for improving performances of digital phase-locked loops
CN101986568A (en) * 2010-10-22 2011-03-16 江苏锦丰电子有限公司 Steady state phase-locking error-free phase locking system and phase locking method
CN102346443A (en) * 2011-08-17 2012-02-08 北斗天汇(北京)科技有限公司 1PPS (pulse per second) latch and control method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
叶淮: ""数字化载波同步环路算法的设计与实现"", 《中国优秀硕士学位论文全文数据库信息科技辑》 *

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