CN105262477B - A kind of S4R logic control circuit and logic control realization method thereof - Google Patents

Abstract

The present invention relates to an S ⁴ R logic control circuit and a logic control implementation method thereof. The input ends of the logic control circuit are respectively connected with the full-tuning bus control signal FG1 and the charging control signal FG2. After logic operation, G1=FG1&FG2 is realized. G2=FG2+(^FG1), the shunt drive signal G1 output from the output terminal of the logic control circuit is connected to the S ⁴ R shunt drive circuit, and the output charge drive signal G2 is connected to the charge drive circuit to realize logic control. The realization principle of the logic control of the present invention is simple and understandable in topology, easy in engineering implementation, and has important engineering application value for satellite solar array adjustment technology.

Description

A kind of S4R logic control circuit and logic control realization method thereof

technical field

The invention belongs to the technical field of solar array regulation and control, and in particular relates to an S ⁴ R (Series Sequential Switching Shunt Regulator, series sequential switching shunt regulator) logic control circuit and a method for realizing logic control thereof.

Background technique

On a general satellite, the solar array adjustment adopts the S ⁴ R control adjustment circuit. For example, CN201310108239 discloses an S ⁴ R type power control device, which includes: a shunt control circuit, a triangular wave generation circuit, a logic control circuit, a charging control circuit, a charging switch tube, a shunt switch tube, and the like. It implements a logic control method through a comparator, a triode, etc. The method performs logic level conversion by turning ^on and off the triode, and realizes the control logic of S4R. However, this logic control method needs more devices, and its advantages are not obvious in realizing multi-channel S ⁴ R circuits.

Contents of the invention

The object of the present invention is to provide an S ⁴ R logic control circuit with simple circuit topology and easy engineering implementation and its logic control implementation method.

In order to achieve the above object, a technical solution of the present invention is to provide a kind of S ⁴ R logic control circuit, which comprises:

four NOR gates each having two input terminals and one output terminal;

Wherein, the full modulation bus control signal FG1 is connected to the two input terminals of the first NOR gate;

The signal P1 of the output terminal of the first NOR gate is respectively connected to the first input terminal of the second NOR gate and the first input terminal of the third NOR gate;

The charging control signal FG2 is connected to the second input terminal of the third NOR gate;

The signal P2 of the output terminal of the third NOR gate is respectively connected to the second input terminal of the second NOR gate, and the two input terminals of the fourth NOR gate;

The output terminal of the second NOR gate outputs the shunt driving signal G1;

The output terminal of the fourth NOR gate outputs the charging driving signal G2;

Among them, G1=^(P1+P2)=(^P1)&(^P2)=(FG1)&(^FG1+FG2)=(FG1)&(FG2);

G2=^P2=P1+FG2=FG2+^FG1.

Another technical solution of the present invention is to provide a kind of S ⁴ R logic control circuit, it comprises:

three NAND gates each having two input terminals and one output terminal;

Wherein, the full modulation bus control signal FG1 is respectively connected to the first input end of the first NAND gate and the second input end of the third NAND gate;

The charging control signal FG2 is connected to the second input terminal of the first NAND gate;

The signal Q1 of the output terminal of the first NAND gate is respectively connected to the two input terminals of the second NAND gate and the first input terminal of the third NAND gate;

The output end of the second NAND gate outputs the shunt driving signal G1;

The output terminal of the third NAND gate outputs the charging driving signal G2;

Among them, G1=^(Q1)=(FG1)&(FG2),

G2=^(Q1&FG1)=^((^FG1+^FG2)&FG1)=FG2+^FG1.

Still another technical solution of the present invention is to provide a method for implementing S ⁴ R logic control. Through any of the above S ⁴ R logic control circuits, respectively receive the full-tuning bus control signal FG1 and the charging control signal FG2 to perform logic operations to obtain shunt drive signal G1 and charge drive signal G2;

Among them, G1=FG1&FG2, G2=FG2+(^FG1);

The shunt driving signal G1 is sent to the S ⁴ R shunt driving circuit, and the charging driving signal G2 is sent to the charging driving circuit.

Preferably, the full-tuning bus control signal FG1 is "0" indicating that the full-tuning bus requires power, and "1" indicates that the full-tuning bus does not require power;

The charging control signal FG2 being "0" indicates that the battery pack requires power, and being "1" indicates that the battery pack does not need power;

The shunt drive signal G1 being "1" indicates that the power of the solar array is shunted to the ground, and being "0" indicates that the power of the solar array is not shunted to the ground;

The charging drive signal G2 being "0" indicates that the solar array is charging the battery pack, and being "1" indicates that the solar array is not charging the battery pack.

Compared with the prior art, the S ⁴ R logic control circuit and logic control implementation method of the present invention have the advantages that: the present invention can realize the logic control method through a 4-way 2-input gate circuit, and adopt the chip as a NAND gate or NOR gate, only one device is needed, saving cost. At the same time, the circuit topology is simple and easy to understand, and the engineering is easy to realize, which has important engineering application value for the satellite solar array adjustment technology.

Description of drawings

The S ⁴ R logic control circuit and logic control implementation method provided by the present invention are given by the following embodiments and accompanying drawings.

Fig. 1 is the schematic diagram of the logic control circuit that the present invention adopts 4 roads 2 input NOR gates to realize in the first example;

Fig. 2 is the schematic diagram of the second example of the logical control circuit realized by the present invention using 4-way 2-input NAND gates;

Fig. 3 is a logic truth table realized by the present invention.

detailed description

The logic control circuit and implementation method of the present invention will be further described in detail below with reference to FIGS. 1 to 3 . It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

In the S ⁴ R logic control circuit and implementation method provided by the present invention, the two input terminals of the logic control circuit are respectively connected with the full-tuning bus control signal FG1 and the charging control signal FG2. The truth table realizes G1=FG1&FG2, G2=FG2+(^FG1). Wherein, the shunt driving signal G1 at the output end is connected to the S ⁴ R shunt driving circuit, and the charging driving signal G2 is connected to the charging driving circuit.

The FG1 being "0" indicates that the fully-regulated bus requires power, and "1" indicates that the fully-regulated bus requires no power; the FG2 being "0" indicates that the battery pack requires power, and "1" indicates that the battery pack does not require power; The G1 being "1" indicates that the power of the solar array is shunted to the power ground, and "0" indicates that the power of the solar array is not shunted to the ground; the G2 being "0" indicates that the solar array charges the battery pack, and "1" indicates that The solar array is not charging the battery pack.

After the FG1 and FG2 enter the logic circuit operation, the output signals G1 and G2 realize the control logic of S ⁴ R.

Embodiment one

As shown in Figure 1, it is a logic control circuit realized by using 4-way 2-input NOR gates. The two input terminals of the first NOR gate are respectively connected to FG1, and the signal P1 at the output terminal is respectively connected to the first NOR gate of the second NOR gate. Input terminal, and the first input terminal of the third NOR gate; the second input terminal of the third NOR gate is connected to FG2, and the signal P2 of its output terminal is respectively connected to the second input terminal of the second NOR gate, and the fourth or The two input ends of the NOT gate; the output signal G1 of the second NOR gate, and the output signal G2 of the fourth NOR gate.

Wherein, after the FG1 and FG2 enter the logic circuit: P1=^FG1, P2=^(P1+FG2),

Therefore, G1=^(P1+P2)=(^P1)&(^P2)=(FG1)&(^FG1+FG2)=(FG1)&(FG2),

G2=^P2=P1+FG2=FG2+^FG1.

Signals G1 and G2 are respectively provided to the S ⁴ R shunt drive circuit and charge drive circuit to realize the S ⁴ R logic control method.

Embodiment two

As shown in Figure 2, it is a logic control circuit realized by using 4-way 2-input NAND gates. The two input terminals of the first NAND gate are respectively connected to FG1 and FG2, and the signal Q1 at the output terminal is respectively connected to the two terminals of the second NAND gate. The second input terminal of the third NAND gate is connected to FG1; the second NAND gate outputs G1, and the third NAND gate outputs G2.

Wherein, after the FG1 and FG2 enter the logic circuit: Q1=^(FG1&FG2),

Therefore, G1=^(Q1)=(FG1)&(FG2),

G2=^(Q1&FG1)=^((^FG1+^FG2)&FG1)=FG2+^FG1.

Signals G1 and G2 are respectively provided to the S ⁴ R shunt drive circuit and charge drive circuit to realize the S ⁴ R logic control method.

Claims (4)

1. A kind of 1. S⁴R logic control circuits, it is characterised in that include：

   Four nor gates, it each has two inputs and an output end；

   Wherein, bus control signal FG1 is adjusted to be connected to two inputs of the first nor gate entirely；

   The signal P1 of the output end of first nor gate is respectively connecting to the first input end and the 3rd nor gate of the second nor gate First input end；

   Charging control signal FG2 is connected to the second input of the 3rd nor gate；

   The signal P2 of the output end of 3rd nor gate is respectively connecting to the second input of the second nor gate, and the two of four nor gate Individual input；

   The output end output steering drive signal G1 of second nor gate；

   The output end output charging drive signal G2 of four nor gate；

   Wherein, G1=^ (P1+P2)=(^P1) ＆ (^P2)=(FG1) ＆ (^FG1+FG2)=(FG1) ＆ (FG2)；

   G2 =^P2=P1+FG2=FG2+^FG1。
2. A kind of 2. S⁴R logic control circuits, it is characterised in that include：

   Three NAND gates, it each has two inputs and an output end；

   Wherein, adjust full bus control signal FG1 be respectively connecting to the first NAND gate first input end and the 3rd NAND gate the Two inputs；

   Charging control signal FG2 is connected to the second input of the first NAND gate；

   The signal Q1 of the output end of first NAND gate, it is respectively connecting to two inputs and the 3rd NAND gate of the second NAND gate First input end；

   The output end output steering drive signal G1 of second NAND gate；

   The output end output charging drive signal G2 of 3rd NAND gate；

   Wherein, G1=^ (Q1)=(FG1) ＆ (FG2),

   G2=^(Q1&FG1)=^((^FG1+^FG2)&FG1)=FG2+^FG1。
3. A kind of 3. S⁴R logic control implementation methods, it is characterised in that

   Pass through the S of claim 1 or 2⁴R logic control circuits, full tune bus control signal FG1, charging control signal are received respectively FG2 carries out logical operation, obtains shunting drive signal G1 and charging drive signal G2；

   Wherein, G1=FG1＆FG2, G2=FG2+（^FG1）；

   Shunting drive signal G1 is delivered to S⁴R shunts drive circuit, and charging drive signal G2 is delivered into charging driving electricity Road.
4. 4. S as claimed in claim 3⁴R logic control implementation methods, it is characterised in that

   The full tune bus control signal FG1 is that " 0 " shows to adjust bus to need power entirely, shows to adjust bus need not entirely for " 1 " Power；

   The charging control signal FG2 is that " 0 " shows that batteries need power, shows that batteries do not need power for " 1 "；

   The shunting drive signal G1 is that " 1 " shows that sun battle array power falls to Power Groud shunting, shows sun battle array power not for " 0 " Shunt over the ground；

   The charging drive signal G2 is that " 0 " shows that sun battle array to battery charging, shows sun battle array not to battery for " 1 " Group charging.