CN105261557A - Manufacturing method for semiconductor device, and semiconductor device - Google Patents
Manufacturing method for semiconductor device, and semiconductor device Download PDFInfo
- Publication number
- CN105261557A CN105261557A CN201410299942.4A CN201410299942A CN105261557A CN 105261557 A CN105261557 A CN 105261557A CN 201410299942 A CN201410299942 A CN 201410299942A CN 105261557 A CN105261557 A CN 105261557A
- Authority
- CN
- China
- Prior art keywords
- substrate
- manufacture method
- semiconductor device
- doped region
- halation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a manufacturing method for a semiconductor device, and the semiconductor device. The manufacturing method for the semiconductor device comprises the steps of providing a substrate; forming a gate structure on the substrate; forming grooves in the positions, on two sides of the gate structure, of the substrate; and epitaxially growing in the grooves and doping at the same time to form a halo doped region. According to the manufacturing method, by forming the grooves in the positions, on two sides of the gate structure, of the substrate, and by forming the halo doped region in the groove by the epitaxial growth mode, the dispersion of the doped ions to conductive channels in the halo doped region is reduced consequently, the reduction of the carrier mobility caused by recombination of the doped ions and the carriers is reduced, so that the performance of the semiconductor device is improved; and meanwhile, the halo doped region can avoid the shortcomings of vacancy or interstitial atoms and the like generated in the substrate in a halo implantation mode, so that a transient enhanced diffusion effect caused by the shortcomings is reduced consequently, and the performance of the semiconductor device is further improved.
Description
Technical field
The application relates to semiconductor integrated circuit manufacture technology field, in particular to a kind of manufacture method and semiconductor device of semiconductor device.
Background technology
Along with the size of semiconductor device constantly reduces, particularly enter into 40 nanometers and with lower node, the conducting channel of semiconductor device is shorter and shorter, thus cause the short-channel effect of semiconductor device (SCE) more and more serious.SCE can affect the Electric Field Distribution of semiconductor device, threshold voltage controls and the characteristic such as electric leakage, and then limits the reducing further of characteristic size of semiconductor device.
In the manufacturing process of existing semiconductor device; usually can carry out halo (Halo) to source/drain region in semiconductor device and inject formation halation doped region; to improve the local doping concentrations near source/drain region; and then stop source/drain depletion region to be expanded to channel region; thus reduce the junction depth of extension area and shorten channel length, suppress SCE effect.
But, the process part Doped ions injected at halo (Halo) can by inject or the mode such as diffusion enters into conducting channel, these Doped ions can become the complex centre of charge carrier in conducting channel, thus reduce the mobility of charge carrier, and then reduce the performance of semiconductor device.Simultaneously, the mode that this halo (Halo) injects also can produce damage to the lattice of backing material, and produce the defect such as room or interstitial atom in the substrate, these defects can catch the charge carrier to substrate surface migration, thus cause instantaneous enhanced diffustion effect (TED), cause producing leakage current in semiconductor device, and then reduce the performance of semiconductor device.
Summary of the invention
The application aims to provide a kind of manufacture method and semiconductor device of semiconductor device, to improve the performance of semiconductor device.
To achieve these goals, this application provides a kind of manufacture method of semiconductor device, this manufacture method comprises: provide substrate, and substrate is formed with grid structure; The position being positioned at grid structure both sides in the substrate forms groove; Epitaxial growth is adulterated simultaneously and is formed halation doped region in a groove.
Further, the step forming halation doped region comprises: epitaxial growth basis material in a groove, and adulterates to form halation doped region to basis material in epitaxially grown process simultaneously.
Further, basis material is the material identical with substrate, or the dissimilar materials identical with the crystal orientation of substrate.
Further, substrate is monocrystalline silicon, and basis material is monocrystalline silicon, SiGe or carborundum.
Further, substrate is p type single crystal silicon, and the Doped ions adulterated to basis material is boron ion; Substrate is n type single crystal silicon, and the Doped ions adulterated to basis material is arsenic ion.
Further, the doping content of Doped ions is 1E+13 ~ 1E+19atoms/cm
3.
Further, in the step forming halation doped region, form the halation doped region that thickness is 1/4 ~ 3/4 of the width of grid.
Further, this manufacture method comprises further: in the substrate of the both sides of grid structure, form source-drain electrode, and part source-drain electrode is formed in halation doped region.
Further, before the step forming source-drain electrode, remove mask layer, and ion implantation is carried out, to form light doping section away from the substrate of the side of grid to the first side wall layer.
Present invention also provides a kind of semiconductor device, this semiconductor device is made by the manufacture method that the application is above-mentioned.
The technical scheme that application the application provides, groove is formed respectively by the position of the both sides being positioned at grid in the substrate, and extension forms halation doped region in a groove, thus the Doped ions decreased in halation doped region is to the diffusion in conducting channel, and decrease the decline of the carrier mobility caused due to Doped ions and charge carrier generation compound, and then improve the performance of semiconductor device.Meanwhile, the defects such as the room that the mode that this halation doped region can avoid halo to inject produces in the substrate or interstitial atom, thus decrease the instantaneous enhanced diffustion effect (TED) caused by defect, and then improve the performance of semiconductor device.
Accompanying drawing explanation
The Figure of description forming a application's part is used to provide further understanding of the present application, and the schematic description and description of the application, for explaining the application, does not form the improper restriction to the application.In the accompanying drawings:
Fig. 1 shows the schematic flow sheet of the manufacture method of the semiconductor device provided according to the application's execution mode;
Fig. 2 shows in the manufacture method according to the semiconductor device provided at the application's execution mode, provides the cross-sectional view of the matrix after substrate;
Fig. 3 shows the cross-sectional view of the matrix form grid structure on the substrate shown in Fig. 2 after;
Fig. 4 show to be positioned in the substrate shown in Fig. 3 grid form groove respectively for the both sides arranging halation doped region after the cross-sectional view of matrix;
Fig. 4-1 shows and form the first side wall layer on the sidewall that the grid shown in Fig. 3 corresponds to the both sides for arranging halation doped region, and the cross-sectional view of matrix form mask layer on the upper surface of grid after;
Fig. 5 shows the cross-sectional view of the matrix to form halation doped region in the groove shown in Fig. 4 after;
Fig. 6 shows the cross-sectional view of the matrix form source-drain electrode in the both sides substrate of the grid shown in Fig. 5 after; And
Fig. 6-1 shows and removes the mask layer shown in Fig. 5, and carries out away from the substrate of the side of grid the cross-sectional view that ion implantation forms the matrix behind light doping section to the first side wall layer in Fig. 6.
Embodiment
It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.Below with reference to the accompanying drawings and describe the application in detail in conjunction with the embodiments.
It should be noted that used term is only to describe embodiment here, and be not intended to the illustrative embodiments of restricted root according to the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative is also intended to comprise plural form, in addition, it is to be further understood that, when use belongs to " comprising " and/or " comprising " in this manual, it indicates existing characteristics, step, operation, device, assembly and/or their combination.
For convenience of description, here can usage space relative terms, as " ... on ", " in ... top ", " at ... upper surface ", " above " etc., be used for the spatial relation described as a device shown in the figure or feature and other devices or feature.Should be understood that, space relative terms is intended to comprise the different azimuth in use or operation except the described in the drawings orientation of device.Such as, " in other devices or structure below " or " under other devices or structure " will be positioned as after if the device in accompanying drawing is squeezed, being then described as the device of " above other devices or structure " or " on other devices or structure ".Thus, exemplary term " in ... top " can comprise " in ... top " and " in ... below " two kinds of orientation.This device also can other different modes location (90-degree rotation or be in other orientation), and relatively describe space used here and make respective explanations.
Technical term " halation doped region " to refer to that in semiconductor device source/drain region is carried out halo (Halo) and injected the local doped region formed in this application, to improve the local doping concentrations near source/drain region, and then stop source/drain depletion region to be expanded to channel region, thus reduce the junction depth of extension area and shorten channel length, suppress SCE effect.
As what introduce in background technology, the halation doped region that the method adopting halo (Halo) to inject is formed can reduce the mobility of charge carrier, and then reduces the performance of semiconductor device.Present inventor studies for the problems referred to above, thus provides a kind of manufacture method of semiconductor device.As shown in Figure 1, this manufacture method comprises: provide substrate, and substrate is formed with grid structure; The position being positioned at grid structure both sides in the substrate forms groove; Epitaxial growth is adulterated simultaneously and is formed halation doped region in a groove.
Above-mentioned manufacture method forms groove respectively by the position of the both sides being positioned at grid in the substrate, and extension forms halation doped region in a groove, thus the Doped ions decreased in halation doped region is to the diffusion in conducting channel, and decrease the decline of the carrier mobility caused due to Doped ions and charge carrier generation compound, and then improve the performance of semiconductor device.Meanwhile, the defects such as the room that the mode that this halation doped region can avoid halo to inject produces in the substrate or interstitial atom, thus decrease the instantaneous enhanced diffustion effect (TED) caused by defect, and then improve the performance of semiconductor device.
Illustrative embodiments according to the application will be described in more detail below.But these illustrative embodiments can be implemented by multiple different form, and should not be interpreted as being only limited to execution mode set forth herein.Should be understood that, there is provided these execution modes be in order to make the application open thorough and complete, and the design of these illustrative embodiments is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expand the thickness in layer and region, and use the device that identical Reference numeral represents identical, thus will omit description of them.
Fig. 2 to Fig. 6 shows in the manufacture method of the semiconductor device that the application provides, the cross-sectional view of the matrix obtained after each step.Below in conjunction with Fig. 3 to Fig. 6, further illustrate the manufacture method of the semiconductor device that the application provides.
First, substrate 10 is as shown in Figure 2 provided.Above-mentioned substrate 10 can be monocrystalline silicon (Si) or brilliant germanium (Ge), also can be silicon-on-insulator (SOI), germanium on insulator (GOI).Exemplarily, in present embodiment using monocrystalline silicon as substrate 10.
Above-mentioned substrate 10 forms grid structure, and then forms basal body structure as shown in Figure 3.Grid structure comprises grid 20 and the dielectric layer between grid 30 and substrate 10 20.Grid can be the common grid material in this area, such as polysilicon, Cu or Al etc.Dielectric layer 20 can be the common dielectric material in this area, such as SiO
2or SiN.The method forming above-mentioned grid 30 and dielectric layer 20 can be the common manufacture method in this area.In the optional execution mode of one, the step forming above-mentioned grid 30 and dielectric layer 20 comprises: first form medium preparation layers and grid preparation layers over the substrate 10, then etch described grid preparation layers and dielectric layer 20, forms grid 30 and dielectric layer 20.
After forming the step of above-mentioned grid structure over the substrate 10, the both sides being positioned at grid structure in substrate 10 form groove 60 respectively, and its basal body structure as shown in Figure 4.In a preferred embodiment, the step forming above-mentioned groove 60 comprises: grid structure correspond to for formed halation doped region 70 both sides sidewall on form the first side wall layer 41, and form mask layer 50 on the upper surface of grid structure, and then form the basal body structure as shown in Fig. 4-1; And along the etched substrate 10 of the first side wall layer 41 away from grid 30 side, form groove 60, and then form basal body structure as shown in Figure 4.
Above-mentioned the first side wall layer 41 is offset by gap wall, for defining the position of groove 60.Above-mentioned the first side wall layer 41 can be the common dielectric material in this area, such as SiO
2or SiN.The technique forming above-mentioned the first side wall layer 41 can be chemical vapour deposition (CVD) or sputtering etc., and above-mentioned technique is state of the art, does not repeat them here.It should be noted that in the process forming above-mentioned the first side wall layer 41, on the upper surface of grid 30, form mask layer 50, and the material of this mask layer 50 is identical with the material of the first side wall layer 41 simultaneously.
The shape of above-mentioned groove 60 can be the common groove shapes in this area, such as U-shaped, brilliant (or being called Σ type).The shape of above-mentioned groove 60 is relevant to etching the technique adopted.Above-mentioned etching can be dry etching or wet etching, or adopts dry etching and wet etching to combine.In the optional execution mode of one, adopt dry etch process to etch above-mentioned substrate 10, form U-shaped groove 60, wherein the process conditions of dry etching are: etching gas is CF
4and CHF
3, sputtering power is 400 ~ 1000 watts, and etching temperature is 25 ~ 60 DEG C, and etch period is 30 ~ 360 seconds.Meanwhile, can also carry out wet etching to above-mentioned U-shaped groove 60, form the groove 60 of brilliant, now above-mentioned groove 60 can extend to the below of grid 30.Wherein, wet etching can have crystal orientation and optionally etches for well known in the art.In a preferred embodiment, using tetramethyl ammonium hydroxide solution as etching liquid, wherein the volume content of Tetramethylammonium hydroxide is 1% ~ 5%, and be preferably 2.38%, the temperature of wet etching is 30 ~ 70 DEG C, and the time is 30 ~ 120s.The etching liquid of above-mentioned wet etching can also be other reagent, such as ammoniacal liquor, and those skilled in the art can according to the process conditions of the kind of actual process demand selective etching liquid and etching.
After the both sides completing grid structure in substrate 10 form the step of groove 60 respectively, in groove 60, epitaxial growth is adulterated simultaneously and is formed halation doped region 70, and then forms basal body structure as shown in Figure 5.Preferably, the step forming halation doped region comprises: epitaxial growth basis material in a groove, and adulterate to form halation doped region to basis material in epitaxially grown process simultaneously, namely, in the process of the above-mentioned substrate material of epitaxial growth, pass into the presoma of doped chemical to carry out in-situ doped to substrate material simultaneously.Wherein, basis material is the material identical with substrate, or the dissimilar materials identical with the crystal orientation of substrate.
Doped ions in above-mentioned halation doped region 70 has identical type with the Doped ions of substrate 10.When above-mentioned substrate 10 is P type, the Doped ions in halation doped region 70 is P type ion; When above-mentioned substrate 10 is N-type, the Doped ions in halation doped region 70 is N-type ion.Aforementioned p-type ion is relevant to the material of substrate 10 with the kind of N-type ion.When substrate 10 is single crystalline Si, P type ion is group iii elements, and N-type ion is group-v element.In the optional execution mode of one, P type ion is boron ion, and N-type ion is phosphonium ion.The concentration of above-mentioned Doped ions can set according to actual process demand, and in a preferred embodiment, the doping content of Doped ions is 1E+13 ~ 1E+19atoms/cm3.
Above-mentioned epitaxial growth technology can be chemical vapour deposition (CVD) or ald etc.When halation doped region 70 is P type single crystalline Si, in a kind of optional execution mode, the technique forming above-mentioned halation doped region 70 is: with SiH
4or SiH
2cl
2for presoma, and pass into BF
2as Doped ions presoma, BF
2flow be 20 ~ 200sccm, the temperature of deposition is 800 ~ 1100 DEG C, and deposition rate is 0.0001 ~ 0.2 μm/min.
The manufacture method of above-mentioned semiconductor device also comprises: after the above-mentioned halation doped region 70 of formation, in the both sides substrate 10 of grid 30, form source-drain electrode 90, preferred part source-drain electrode 90 is formed in halation doped region 70, and its basal body structure as shown in Figure 6.In a kind of Alternate embodiments, the step forming source-drain electrode 90 comprises: on the first side wall, form the second side wall layer; And away from the substrate 10 of the side of grid 30, ion implantation is carried out to the second side wall layer, form source-drain electrode 90.
Above-mentioned second side wall layer is source and drain clearance wall, for defining the position of source-drain electrode 90.Above-mentioned second side wall layer can be the common dielectric material in this area, such as SiO
2or SiN.The technique forming above-mentioned second side wall layer 42 can be chemical vapour deposition (CVD) or sputtering etc., and above-mentioned technique is state of the art, does not repeat them here.The process conditions of above-mentioned ion implantation can set according to actual process demand.
Before the step forming above-mentioned source-drain electrode 90, can also remove described mask layer 50, and carry out ion implantation to the first side wall layer 41 away from the substrate 10 of the side of grid 30, to form light doping section 80, its basal body structure as in Figure 6-1.The process conditions of above-mentioned ion implantation can set according to actual process demand.
From above description, can find out, the application's the above embodiments achieve following technique effect: arrange groove respectively by the both sides being positioned at grid in the substrate, and extension arranges halation doped region in a groove, thus the Doped ions decreased in halation doped region is to the diffusion in conducting channel, and decrease the decline of the carrier mobility caused due to Doped ions and charge carrier generation compound, and then improve the performance of semiconductor device.Meanwhile, the defects such as the room that the mode that this halation doped region can avoid halo to inject produces in the substrate or interstitial atom, thus decrease the instantaneous enhanced diffustion effect (TED) caused by defect, and then improve the performance of semiconductor device.
The foregoing is only the preferred embodiment of the application, be not limited to the application, for a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the application.
Claims (10)
1. a manufacture method for semiconductor device, is characterized in that, described manufacture method comprises:
Substrate is provided, described substrate is formed with grid structure;
The position being positioned at described grid structure both sides in described substrate forms groove;
In described groove, epitaxial growth is adulterated simultaneously and is formed halation doped region.
2. manufacture method according to claim 1, it is characterized in that, the step forming described halation doped region comprises: epitaxial growth basis material in described groove, and adulterates to form described halation doped region to described basis material in epitaxially grown process simultaneously.
3. manufacture method according to claim 2, is characterized in that, described basis material is the material identical with described substrate, or the dissimilar materials identical with the crystal orientation of described substrate.
4. manufacture method according to claim 3, described substrate is monocrystalline silicon, and described basis material is monocrystalline silicon, SiGe or carborundum.
5. manufacture method according to claim 2, is characterized in that,
Described substrate is p type single crystal silicon, and the Doped ions adulterated to described basis material is boron ion;
Described substrate is n type single crystal silicon, and the Doped ions adulterated to described basis material is arsenic ion.
6. manufacture method according to claim 5, is characterized in that, the doping content of described Doped ions is 1E+13 ~ 1E+19atoms/cm
3.
7. manufacture method according to claim 2, is characterized in that, in the step forming described halation doped region, forms the described halation doped region that thickness is 1/4 ~ 3/4 of the width of described grid.
8. manufacture method according to claim 1, is characterized in that, described manufacture method comprises further: in the substrate of the both sides of described grid structure, form source-drain electrode, and the described source-drain electrode of part is formed in described halation doped region.
9. manufacture method according to claim 1, is characterized in that, before the step forming described source-drain electrode, removes described mask layer, and carries out ion implantation, to form light doping section to described the first side wall layer away from the substrate of the side of described grid.
10. a semiconductor device, is characterized in that, the manufacture method of described semiconductor device according to any one of claim 1 to 9 is made.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410299942.4A CN105261557A (en) | 2014-06-26 | 2014-06-26 | Manufacturing method for semiconductor device, and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410299942.4A CN105261557A (en) | 2014-06-26 | 2014-06-26 | Manufacturing method for semiconductor device, and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105261557A true CN105261557A (en) | 2016-01-20 |
Family
ID=55101188
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410299942.4A Pending CN105261557A (en) | 2014-06-26 | 2014-06-26 | Manufacturing method for semiconductor device, and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105261557A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113471234A (en) * | 2021-06-30 | 2021-10-01 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN113871451A (en) * | 2021-09-24 | 2021-12-31 | 华虹半导体(无锡)有限公司 | DMOS device and method of forming the same |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050085055A1 (en) * | 2003-10-17 | 2005-04-21 | Chartered Semiconductor Manufacturing Ltd. | End of range (EOR) secondary defect engineering using substitutional carbon doping |
| CN1773722A (en) * | 2004-10-12 | 2006-05-17 | 国际商业机器公司 | Field Effect Transistor and Method for Making the Same |
| US20080023752A1 (en) * | 2006-07-28 | 2008-01-31 | International Business Machines Corporation | BORON DOPED SiGe HALO FOR NFET TO CONTROL SHORT CHANNEL EFFECT |
| US20080230805A1 (en) * | 2007-03-20 | 2008-09-25 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing semiconductor device |
| US7829939B1 (en) * | 2009-04-20 | 2010-11-09 | International Business Machines Corporation | MOSFET including epitaxial halo region |
| CN103187276A (en) * | 2011-12-27 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | N-type MOS field-effect transistor and formation method thereof, semiconductor device and formation method of semiconductor device |
| CN103426768A (en) * | 2012-05-25 | 2013-12-04 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN103545213A (en) * | 2012-07-16 | 2014-01-29 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
-
2014
- 2014-06-26 CN CN201410299942.4A patent/CN105261557A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050085055A1 (en) * | 2003-10-17 | 2005-04-21 | Chartered Semiconductor Manufacturing Ltd. | End of range (EOR) secondary defect engineering using substitutional carbon doping |
| CN1773722A (en) * | 2004-10-12 | 2006-05-17 | 国际商业机器公司 | Field Effect Transistor and Method for Making the Same |
| US20080023752A1 (en) * | 2006-07-28 | 2008-01-31 | International Business Machines Corporation | BORON DOPED SiGe HALO FOR NFET TO CONTROL SHORT CHANNEL EFFECT |
| US20080230805A1 (en) * | 2007-03-20 | 2008-09-25 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing semiconductor device |
| US7829939B1 (en) * | 2009-04-20 | 2010-11-09 | International Business Machines Corporation | MOSFET including epitaxial halo region |
| CN103187276A (en) * | 2011-12-27 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | N-type MOS field-effect transistor and formation method thereof, semiconductor device and formation method of semiconductor device |
| CN103426768A (en) * | 2012-05-25 | 2013-12-04 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN103545213A (en) * | 2012-07-16 | 2014-01-29 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113471234A (en) * | 2021-06-30 | 2021-10-01 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN113471234B (en) * | 2021-06-30 | 2023-08-18 | 武汉新芯集成电路制造有限公司 | Semiconductor device and manufacturing method thereof |
| CN113871451A (en) * | 2021-09-24 | 2021-12-31 | 华虹半导体(无锡)有限公司 | DMOS device and method of forming the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8853008B1 (en) | Counter-doped low-power FinFET | |
| CN104752211B (en) | Fin formula field effect transistor and forming method thereof | |
| CN103579324B (en) | A kind of three source tunneling field-effect transistors and preparation method thereof | |
| EP3087603A1 (en) | High mobility transistors | |
| CN106558614A (en) | Semiconductor structure and forming method thereof | |
| CN104425591B (en) | Transistor and forming method thereof | |
| CN103715090A (en) | Transistor and forming method thereof | |
| CN104009078B (en) | Nodeless mesh body pipe and manufacture method thereof | |
| CN103035610B (en) | Electric connection structure and the manufacture method of trap and substrate is connected in RFLDMOS | |
| TWI739152B (en) | Epitaxial semiconductor material grown with enhanced local isotropy | |
| CN103000499B (en) | A kind of germanium silicon boron outer layer growth method | |
| CN105261557A (en) | Manufacturing method for semiconductor device, and semiconductor device | |
| CN106601677A (en) | Semiconductor device and manufacturing method thereof, and electronic device | |
| WO2019114201A1 (en) | Silicon carbide power semiconductor device having low on-resistance | |
| KR101682420B1 (en) | Self-aligned heterojunction tunnel field-effect transistor using selective germanium condensation and sidewall processes | |
| CN109698237A (en) | A kind of trench gate silicon carbide MOSFET device and its manufacturing method | |
| CN105575804B (en) | Fin field effect transistor and manufacturing method thereof | |
| CN106558493A (en) | The forming method of fin field effect pipe | |
| CN104253090B (en) | The forming method of CMOS transistor | |
| CN103123899B (en) | FinFET manufacture method | |
| CN105097437A (en) | Method for forming strain silicon layer, manufacturing method for PMOS device and semiconductor device | |
| CN105244277A (en) | Junction-free field effect transistor and formation method thereof | |
| CN105244375B (en) | PNIN/NPIP type SSOI TFET and preparation method with mutation tunnel junctions | |
| CN105575810B (en) | The forming method of transistor | |
| WO2014121752A1 (en) | Manufacturing method of multi-gate fin field-effect transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160120 |
|
| RJ01 | Rejection of invention patent application after publication |