CN105259719B - The discharge circuit and display device of a kind of display panel - Google Patents
The discharge circuit and display device of a kind of display panel Download PDFInfo
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- CN105259719B CN105259719B CN201510607726.6A CN201510607726A CN105259719B CN 105259719 B CN105259719 B CN 105259719B CN 201510607726 A CN201510607726 A CN 201510607726A CN 105259719 B CN105259719 B CN 105259719B
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- 239000004973 liquid crystal related substance Substances 0.000 description 7
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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Abstract
The invention discloses the discharge circuit and display device of a kind of display panel, the discharge circuit includes：At least one the first transistor, and the control terminal of the first transistor and input terminal short circuit, the input terminal of each the first transistor is correspondingly connected with any one at least one clock signal input terminal of high potential input terminal, display test switch signal input end and gate drivers；One second transistor, the control terminal of the second transistor are connected with the output terminal of the first transistor, and the input terminal of the second transistor is connected with common electric voltage input terminal, and the output terminal of the second transistor is connected with display data signal under test input terminal；One capacitance, the first end of the capacitance are connected with the output terminal of the first transistor, and the second end of the capacitance is connected with the common electric voltage input terminal, the film flicker phenomenon after realizing power-off ghost shadow picture caused by preventing residual charge and restarting.
Description
Technical field
The present embodiments relate to display technology field more particularly to a kind of discharge circuits of display panel and display to fill
It puts.
Background technology
In recent years, liquid crystal display because its operating voltage is low, low-power consumption, Low emissivity, small space occupancy and frivolous U.S.
See etc. advantages and constantly popularize, be known as the market mainstream display device.At present, requirement of the people for liquid crystal display constantly carries
The display image quality requirement of height, particularly whole display is higher and higher.Wherein ghost problem is to influence the crime of image display quality
One of key factor.
After liquid crystal display power-off and various tests, the pixel capacitance in liquid crystal display has little time to discharge or put
It is electric not exclusively, the phenomenon that being susceptible to power-off ghost shadow picture.If these charges can not be complete before liquid crystal display is activated next time
It is complete to exclude, after liquid crystal display being again turned on, there is of short duration flicker, under the image display quality for causing liquid crystal display
Drop.
The content of the invention
The present invention provides a kind of discharge circuit and display device of display panel, to realize the residual discharged in interview panel
Charge solves the problems, such as the film flicker caused by residual charge.
In a first aspect, an embodiment of the present invention provides a kind of discharge circuit of display panel, including：
At least one the first transistor, and the control terminal of the first transistor and input terminal short circuit, each described first
The input terminal of transistor is at least one with high potential input terminal, display test switch signal input end and gate drivers
Any one in clock signal input terminal is correspondingly connected with；
One second transistor, the control terminal of the second transistor is connected with the output terminal of the first transistor, described
The input terminal of second transistor is connected with common electric voltage input terminal, output terminal and the display test data letter of the second transistor
The connection of number input terminal；
One capacitance, the first end of the capacitance are connected with the output terminal of the first transistor, the second end of the capacitance
It is connected with the common electric voltage input terminal.
Second aspect, the embodiment of the present invention additionally provide a kind of display device, including the discharge circuit described in first aspect.
Display panel discharge circuit provided by the invention includes at least one the first transistor, a second transistor and an electricity
Hold, wherein by the control terminal of the first transistor and input terminal short circuit, the input terminal of each the first transistor and height electricity
Appointing at least one clock signal input terminal of position input terminal, display test switch signal input end and gate drivers
Meaning one is correspondingly connected with；The control terminal for stating second transistor is connected with the output terminal of the first transistor, second crystal
The input terminal of pipe is connected with common electric voltage input terminal, output terminal and the display data signal under test input terminal of the second transistor
Connection；The first end of the capacitance is connected with the output terminal of the first transistor, the second end of the capacitance with it is described public
Voltage input end connects.In display panel normal work, display test or module test process, the first transistor conducting is institute
Capacitance charging is stated, after the completion of display panel power-off, display test or module test, capacitance driving second transistor conducting makes to show
Show that remaining charge releases in panel, therefore display panel discharge circuit provided by the invention can discharge display panel and break
Remaining charge after the completion of electricity, display test or module test, institute is so as to prevent power-off ghost shadow picture caused by residual charge
And the film flicker phenomenon after restarting.
Description of the drawings
Fig. 1 is a kind of discharge circuit structure diagram of display panel provided in an embodiment of the present invention；
Fig. 2 is the discharge circuit structure diagram of another display panel provided in an embodiment of the present invention；
Fig. 3 is the discharge circuit structure diagram of another display panel provided in an embodiment of the present invention；
Fig. 4 is the discharge circuit structure diagram of another display panel provided in an embodiment of the present invention；
Fig. 5 is the discharge circuit structure diagram of another display panel provided in an embodiment of the present invention；
Fig. 6 is the discharge circuit structure diagram of another display panel provided in an embodiment of the present invention；
Fig. 7 is the discharge circuit structure diagram of another display panel provided in an embodiment of the present invention；
Fig. 8 is the discharge circuit structure diagram of another display panel provided in an embodiment of the present invention；
Fig. 9 is the discharge circuit structure diagram of another display panel provided in an embodiment of the present invention；
Figure 10 is the discharge circuit structure diagram of another display panel provided in an embodiment of the present invention；
Figure 11 is the discharge circuit structure diagram of another display panel provided in an embodiment of the present invention；
Figure 12 is the discharge circuit structure diagram of another display panel provided in an embodiment of the present invention；
Figure 13 is the discharge circuit structure diagram of another display panel provided in an embodiment of the present invention；
Figure 14 is the discharge circuit structure diagram of another display panel provided in an embodiment of the present invention；
Figure 15 is the Contrast on effect schematic diagram using the discharge circuit shown in Figure 14 and the prior art；
Figure 16 is the discharge circuit structure diagram of another display panel provided in an embodiment of the present invention；
Figure 17 is the discharge circuit structure diagram of another display panel provided in an embodiment of the present invention；
Figure 18 is the discharge circuit structure diagram of another display panel provided in an embodiment of the present invention；
Figure 19 is the discharge circuit structure diagram of another display panel provided in an embodiment of the present invention；
Figure 20 is the discharge circuit structure diagram of another display panel provided in an embodiment of the present invention；
Figure 21 is the discharge circuit structure diagram of another display panel provided in an embodiment of the present invention；
Figure 22 is the discharge circuit structure diagram of another display panel provided in an embodiment of the present invention；
Figure 23 is the discharge circuit structure diagram of another display panel provided in an embodiment of the present invention；
Figure 24 is the Contrast on effect schematic diagram using the discharge circuit shown in Figure 23 and the prior art.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limitation of the invention.It also should be noted that in order to just
Part related to the present invention rather than entire infrastructure are illustrated only in description, attached drawing.
The present invention provides a kind of discharge circuit of display panel, including：
At least one the first transistor, and the control terminal of the first transistor and input terminal short circuit, each described first
The input terminal of transistor is at least one with high potential input terminal, display test switch signal input end and gate drivers
Any one in clock signal input terminal is correspondingly connected with；
One second transistor, the control terminal of the second transistor is connected with the output terminal of the first transistor, described
The input terminal of second transistor is connected with common electric voltage input terminal, output terminal and the display test data letter of the second transistor
The connection of number input terminal；
One capacitance, the first end of the capacitance are connected with the output terminal of the first transistor, the second end of the capacitance
It is connected with the common electric voltage input terminal.
The discharge circuit operation principle of display panel provided by the invention is as follows：
In display panel normal work, display test or module test process, the first transistor conducting is the capacitance
It charges；After the completion of display panel power-off, display test or module test, capacitance driving second transistor conducting makes display panel
In remaining charge release, therefore display panel discharge circuit provided by the invention can discharge display panel power-off, aobvious
Show remaining charge after the completion of test or module test, institute is so as to prevent power-off ghost shadow picture caused by residual charge and again
Film flicker phenomenon after opening.
The above are the core concept of the application, below in conjunction with the attached drawing in the embodiment of the present invention, to the embodiment of the present invention
In technical solution be clearly and completely described, it is clear that described embodiment be only part of the embodiment of the present invention,
Instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making creative labor
Under the premise of dynamic, all other embodiments obtained belong to the scope of protection of the invention.
Many details are elaborated in the following description to facilitate a thorough understanding of the present invention, still the present invention can be with
Implemented using other different from other embodiment described here, those skilled in the art can be without prejudice in the present invention
Similar popularization is done in the case of culvert, therefore the present invention is from the limitation of following public specific embodiment.
Fig. 1 is a kind of discharge circuit structure diagram of display panel provided in an embodiment of the present invention, as shown in Figure 1, institute
Stating the discharge circuit of display panel includes：
The first transistor T1, and the control terminal of the first transistor T1 and input terminal short circuit, the first transistor T1
Input terminal be correspondingly connected with high potential input terminal VGH；
Second transistor T2, the control terminal of the second transistor T2 are connected with the output terminal of the first transistor T1,
The input terminal of the second transistor T2 is connected with common electric voltage input terminal Vcom, and the output terminal of the second transistor T2 is with showing
Show the VT-DATA connections of data signal under test input terminal.
One capacitance C1, the first end of the capacitance C1 are connected with the output terminal of the first transistor T1, the capacitance C1
Second end be connected with the common electric voltage input terminal Vcom.
It should be noted that in addition to said structure, display panel further include other support its component worked normally and
Structure, for example, state display panel include a plurality of data lines and multi-strip scanning line, a plurality of data lines and multi-strip scanning line insulation
Overlapping to limit multiple pixel units, each pixel unit includes a pixel switch Tpixel, the control of the pixel switch Tpixel
End processed is connected with corresponding scan line, and the input terminal of the pixel switch Tpixel is connected with respective data lines, and the pixel is opened
The output terminal for closing Tpixel is connected with pixel electrode；Each scan line of the display panel is connected to input with driving chip interface
Scanning signal.Further include pixel capacitance Cpixel, display test scanning signal input terminal VG, data signal input Dn, scanning
Signal input part Gn.It is each pixel unit input wherein to show that test scanning signal input terminal VG is used in test process is shown
Scanning signal；Display data signal under test input terminal VT-DATA is used in test process is shown be each pixel unit input number
It is believed that number；Scanning signal input terminal Gn is used in display panel course of normal operation or when module is tested, and is each pixel
Unit provides scanning signal；Data signal input Dn is used to test in display panel course of normal operation or in module
When, provide data-signal for each pixel unit.
As shown in Figure 1, when display panel is normally shown or carry out module test when, it is necessary to which high potential is defeated
Enter to hold VGH to provide high potential, due to the first transistor T1 input terminals and control terminal short circuit, the T1 of the first transistor at this time is led
It is logical, it charges for the capacitance C1.When display panel powers off, capacitance C1 driving second transistors T2 is opened, at this point, pixel switch
Tpixel leaks electricity naturally, and the charge that each pixel unit in display panel is remained in pixel capacitance Cpixel can be by second
Transistor T2 discharges.Therefore, the discharge circuit of display panel provided in an embodiment of the present invention can solve display panel power-off with
And remaining charge causes afterimage and film flicker problem after module test.
Fig. 2 is the discharge circuit structure diagram of another display panel provided in an embodiment of the present invention, as shown in Fig. 2,
The discharge circuit of the display panel includes：
The first transistor T1, and the control terminal of the first transistor T1 and input terminal short circuit, the first transistor T1
Input terminal with display test switch signal input end SWITCH be correspondingly connected with；
Second transistor T2, the control terminal of the second transistor T2 are connected with the output terminal of the first transistor T1,
The input terminal of the second transistor T2 is connected with common electric voltage input terminal Vcom, and the output terminal of the second transistor T2 is with showing
Show the VT-DATA connections of data signal under test input terminal；
One capacitance C1, the first end of the capacitance C1 are connected with the output terminal of the first transistor T1, the capacitance C1
Second end be connected with the common electric voltage input terminal Vcom；
The control terminal of third transistor T3, the third transistor T3 and input terminal short circuit, and with the of the capacitance C1
One end connects, and the output terminal of the third transistor T3 switchs the control terminal of Mgn with display test scanning signal respectively and shows
Show the control terminal connection of data signal under test switch Mdn, the input terminal of the display test scanning signal switch Mgn is surveyed with display
Examination scanning signal input terminal VG is connected, and the output terminal of the display test scanning signal switch Mgn is connected with corresponding scan line,
The input terminal of the display data signal under test switch Mdn is connected with display data signal under test input terminal VT-DATA, described aobvious
Show that the output terminal of data signal under test switch Mdn is connected with respective data lines.
As described in Figure 2, when carrying out display test, the first transistor T1 conductings are charged for capacitance C1.When display is tested
Cheng Hou, capacitance C1 driving third transistor T3 conductings, display test scanning signal switch Mgn and display test scanning signal switch
Mgn is opened, and capacitance C1 also drives second transistor T2 to open in addition, at this point, pixel switch Tpixel leaks electricity naturally, display panel
In each pixel unit remain in charge in pixel capacitance Cpixel can be by second transistor T2, display test scanning letter
Number switch Mgn and display test scanning signal switch Mgn release.Therefore, the electric discharge of display panel provided in an embodiment of the present invention
Remaining charge causes afterimage and film flicker after circuit can solve the problems, such as display test.
Fig. 3 is the discharge circuit structure diagram of another display panel provided in an embodiment of the present invention, as shown in figure 3,
The discharge circuit includes：
The first transistor T1, and the control terminal of the first transistor T1 and input terminal short circuit, the first transistor T1
Input terminal be correspondingly connected with high potential input terminal VGH；
Second transistor T2, the control terminal of the second transistor T2 are connected with the output terminal of the first transistor T1,
The input terminal of the second transistor T2 is connected with common electric voltage input terminal Vcom, and the output terminal of the second transistor T2 is with showing
Show the VT-DATA connections of data signal under test input terminal.
One capacitance C1, the first end of the capacitance C1 are connected with the output terminal of the first transistor T1, the capacitance C1
Second end be connected with the common electric voltage input terminal Vcom.
The control terminal of third transistor T3, the third transistor T3 and input terminal short circuit, and with the of the capacitance C1
One end connects, and the output terminal of the third transistor T3 switchs the control terminal of Mgn with display test scanning signal respectively and shows
Show the control terminal connection of data signal under test switch Mdn, the input terminal of the display test scanning signal switch Mgn is surveyed with display
Examination scanning signal input terminal VG is connected, and the output terminal of the display test scanning signal switch Mgn is connected with corresponding scan line,
The input terminal of the display data signal under test switch Mdn is connected with display data signal under test input terminal VT-DATA, described aobvious
Show that the output terminal of data signal under test switch Mdn is connected with respective data lines.
It should be noted that the display panel further includes display test switch signal input end SWITCH, display test
Switch signal input end SWITCH switchs the control terminal of Mgn and display test data with the display test scanning signal respectively
The control terminal connection of signaling switch Mdn.
The discharge circuit of display panel provided in an embodiment of the present invention works normally display and module in display panel
During test, high level input terminal VGH input high levels, the first transistor T1 conductings are charged for capacitance C1, when display panel powers off
Or after module is tested, capacitance C1 driving third transistor T3 conductings.Display test scanning signal switch Mgn and display are surveyed
It tries data-signal switch Mdn to open, second transistor T2 is opened, and pixel switch Tpixel leaks electricity naturally, is remained after display test
Charge and power-off after or module test after remaining charge can be discharged by second transistor T2, so as to avoid
Residual charge causes the problem of afterimage and film flicker.
Fig. 4 is the discharge circuit structure diagram of another display panel provided in an embodiment of the present invention, as shown in figure 3,
The discharge circuit includes：
2 the first transistor T1, and the control terminal of the first transistor T1 and input terminal short circuit, a first transistor
The input terminal of T1 with display test switch signal input end SWITCH be correspondingly connected with, the input terminal of another the first transistor T1 with
High potential input terminal VGH is correspondingly connected with；
Second transistor T2, the control terminal of the second transistor T2 are connected with the output terminal of the first transistor T1,
The input terminal of the second transistor T2 is connected with common electric voltage input terminal Vcom, and the output terminal of the second transistor T2 is with showing
Show the VT-DATA connections of data signal under test input terminal；
One capacitance C1, the first end of the capacitance C1 are connected with the output terminal of the first transistor T1, the capacitance C1
Second end be connected with the common electric voltage input terminal Vcom；
The control terminal of third transistor T3, the third transistor T3 and input terminal short circuit, and with the of the capacitance C1
One end connects, and the output terminal of the third transistor T3 switchs the control terminal of Mgn with display test scanning signal respectively and shows
Show the control terminal connection of data signal under test switch Mdn, the input terminal of the display test scanning signal switch Mgn is surveyed with display
Examination scanning signal input terminal VG is connected, and the output terminal of the display test scanning signal switch Mgn is connected with corresponding scan line,
The input terminal of the display data signal under test switch Mdn is connected with display data signal under test input terminal VT-DATA, described aobvious
Show that the output terminal of data signal under test switch Mdn is connected with respective data lines.
The discharge circuit of display panel provided in an embodiment of the present invention is showing that display test switching signal is defeated when testing
Enter to hold SWITCH input high levels, turned on the first transistor T1 of display test switch signal input end SWITCH connections, be
Capacitance C1 charges, after display test is completed, capacitance C1 driving third transistor conductings, and display test scanning signal switch
Mgn and display data signal under test switch Mdn are opened, and second transistor T2 is opened, and pixel switch Tpixel leaks electricity naturally, is shown
The charge remained in after test in pixel capacitance Cpixel can be discharged by second transistor T2.When display panel works normally
It shows or when carrying out module test, high level input terminal VGH input high levels are connected with the high level input terminal VGH
The first transistor T1 conducting, for the capacitance C1 be powered, when display panel power-off or module test after, capacitance C1 driving
Second transistor T2 is opened, and pixel switch Tpixel leaks electricity naturally, is remained after display panel power-off or after module is tested
Charge in pixel capacitance Cpixel can be discharged by second transistor T2, so as to which residual charge be avoided to cause afterimage
And the problem of film flicker.
Fig. 5 is the structure diagram of the discharge circuit of another display panel provided in an embodiment of the present invention, such as Fig. 5 institutes
Show, the discharge circuit includes：
The first transistor T1, and the control terminal of the first transistor T1 and input terminal short circuit, the first transistor T1
Input terminal be correspondingly connected with high potential input terminal VGH；
Second transistor T2, the control terminal of the second transistor T2 are connected with the output terminal of the first transistor T1,
The input terminal of the second transistor T2 is connected with common electric voltage input terminal Vcom, and the output terminal of the second transistor T2 is with showing
Show the VT-DATA connections of data signal under test input terminal.
One capacitance C1, the first end of the capacitance C1 are connected with the output terminal of the first transistor T1, the capacitance C1
Second end be connected with the common electric voltage input terminal Vcom.
4th transistor T4, the control terminal and input terminal short circuit of the 4th transistor T4, and with the of the capacitance C1
One end connects, and the output terminal of the 4th transistor T4 is connected with display test scanning signal input terminal VG.
Discharge circuit provided in an embodiment of the present invention when display panel is worked normally and shown or is carrying out module test
When, high level input terminal VGH input high levels, the first transistor T1 conducting, for capacitance C1 charge, when display panel power-off or
After module is tested, capacitance C1 drives the 4th transistor T4 conductings, so that pixel switch Tpixel is opened, capacitance C1 in addition
Also second transistor T2 is driven to open, remained in after display panel power-off or after module is tested in pixel capacitance Cpixel
Charge can be discharged by second transistor T2, so as to which residual charge be avoided to cause asking for afterimage and film flicker
Topic.Since the present embodiment is provided with the 4th transistor T4, driving pixel switch Tpixel is opened, and accelerates pixel capacitance Cpixel
In charge rate of release.
It should be noted that Fig. 5 illustratively high level input terminal VGH connect a first transistor T1, at other
In embodiment, switch signal input end SWITCH one the first transistor T1 (referring to Fig. 6) of series connection can also be tested in display,
By setting the 4th transistor T4, accelerate the release of residual charge after display test；Or switching signal is tested in display simultaneously
Input terminal SWITCH and high level input terminal VGH connects a first transistor T1 (referring to Fig. 7) respectively, pass through set it is the 4th brilliant
Body pipe T4 accelerates display test and display panel power-off, the release of module test residual charge.
Fig. 8 is the structure diagram of the discharge circuit of another display panel provided in an embodiment of the present invention, such as Fig. 8 institutes
Show, the discharge circuit includes：
The first transistor T1, and the control terminal of the first transistor T1 and input terminal short circuit, the first transistor T1
Input terminal be correspondingly connected with high potential input terminal VGH；
Second transistor T2, the control terminal of the second transistor T2 are connected with the output terminal of the first transistor T1,
The input terminal of the second transistor T2 is connected with common electric voltage input terminal Vcom, and the output terminal of the second transistor T2 is with showing
Show the VT-DATA connections of data signal under test input terminal；
One capacitance C1, the first end of the capacitance C1 are connected with the output terminal of the first transistor T1, the capacitance C1
Second end be connected with the common electric voltage input terminal Vcom；
5th transistor T5, the control terminal of the 5th transistor T5 are connected with the first end of the capacitance C1, and described
The input terminal of five transistor T5 is connected with display test scanning signal input terminal VG, the output terminal of the 5th transistor T5 and institute
State the Vcom connections of common electric voltage input terminal.
Discharge circuit provided in an embodiment of the present invention when display panel works normally and shows picture or is carrying out mould
During group test, high level input terminal VGH input high levels, the first transistor T1 conductings are charged for capacitance C1, when display panel breaks
After electricity or module are tested, capacitance C1 driving second transistor T2 and the 5th transistor T5 are opened, at this time the discharge circuit
The charge in pixel capacitance Cpixel can not only be discharged, can also be discharged to remain in and sweep by the opening of the 5th transistor T5
Retouch the charge on line.
It should be noted that Fig. 8 is illustratively high level input terminal VGH one the first transistor T1 of series connection, at other
In embodiment, if the display panel further includes display test switch signal input end SWITCH, then can only show
Switch signal input end SWITCH one the first transistor T1 of series connection is tested, and the 5th transistor T5 (referring to Fig. 9) is set；May be used also
To connect respectively a first transistor T1 in high level input terminal VGH and display test switch signal input end SWITCH, and
5th transistor T5 (referring to Figure 10) is set.
Figure 11 is the structure diagram of the discharge circuit of another display panel provided in an embodiment of the present invention, such as Figure 11 institutes
Show, the discharge circuit includes：
The first transistor T1, and the control terminal of the first transistor T1 and input terminal short circuit, the first transistor T1
Input terminal be correspondingly connected with high potential input terminal VGH；
Second transistor T2, the control terminal of the second transistor T2 are connected with the output terminal of the first transistor T1,
The input terminal of the second transistor T2 is connected with common electric voltage input terminal Vcom, and the output terminal of the second transistor T2 is with showing
Show the VT-DATA connections of data signal under test input terminal；
One capacitance C1, the first end of the capacitance C1 are connected with the output terminal of the first transistor T1, the capacitance C1
Second end be connected with the common electric voltage input terminal Vcom；
6th transistor T6, the control terminal and input terminal short circuit of the 6th transistor T6, and with the of the capacitance C1
One end connects, and the output terminal of the 6th transistor T6 is connected with the second end of the capacitance C1.
Discharge circuit provided in an embodiment of the present invention when display panel is worked normally and shown or is carrying out module test
When, high level input terminal VGH input high levels, the first transistor T1 conducting, for capacitance C1 charge, when display panel power-off or
After module is tested, capacitance C1 drivings second transistor T2 is opened, and remains in charge in pixel capacitance Cpixel at this time just
It can be released by second transistor t2.After the final residual charge when in pixel capacitance Cpixel is discharged completely, by institute
The control terminal of the 6th transistor T6 and input terminal short circuit are stated, and is connected with the first end of the capacitance C1, the 6th transistor
The output terminal of T6 is connected with the second end of the capacitance C1, therefore releases the charge in capacitance C1 eventually by the 6th transistor T6
It puts.
It should be noted that Figure 11 is illustrative, in high level input terminal VGH one the first transistor T1 of series connection, and finally
The charge in capacitance C1 is discharged by the 6th transistor T6, in other embodiments, switch letter can also be tested in display
Number input terminal SWITCH connects a first transistor T1, and sets the 6th transistor T6 (referring to Figure 12)；It can also be in high electricity
Flat input terminal VGH and display test switch signal input end SWITCH connect a first transistor T1 respectively, and set the 6th
Transistor T6 (referring to Figure 13).
It should be noted that as long as the discharge circuit that the various embodiments described above provide includes the first transistor T1, the second crystal
Pipe T2 and capacitance C1, and be attached according to the connection relation described in the various embodiments described above, you can it realizes and residual charge is released
It puts, third transistor T3, the 4th transistor T4, the 5th transistor T5 and the 6th transistor can also be included at least on this basis
It is at least one in T6, and be configured according to the connection relation described in the various embodiments described above, accordingly complete respective function.Figure
14 be the structure diagram of the discharge circuit of another display panel provided in an embodiment of the present invention, as shown in figure 14, described to put
Circuit includes：
2 the first transistor T1, and the control terminal of the first transistor T1 and input terminal short circuit, a first transistor
The input terminal of T1 with display test switch signal input end SWITCH be correspondingly connected with, the input terminal of another the first transistor T1 with
High potential input terminal VGH is correspondingly connected with；
Second transistor T2, the control terminal of the second transistor T2 are connected with the output terminal of the first transistor T1,
The input terminal of the second transistor T2 is connected with common electric voltage input terminal Vcom, and the output terminal of the second transistor T2 is with showing
Show the VT-DATA connections of data signal under test input terminal；
One capacitance C1, the first end of the capacitance C1 are connected with the output terminal of the first transistor T1, the capacitance C1
Second end be connected with the common electric voltage input terminal Vcom；
The control terminal of third transistor T3, the third transistor T3 and input terminal short circuit, and with the of the capacitance C1
One end connects, and the output terminal of the third transistor T3 switchs the control terminal of Mgn with display test scanning signal respectively and shows
Show the control terminal connection of data signal under test switch Mdn, the input terminal of the display test scanning signal switch Mgn is surveyed with display
Examination scanning signal input terminal VG is connected, and the output terminal of the display test scanning signal switch Mgn is connected with corresponding scan line,
The input terminal of the display data signal under test switch Mdn is connected with display data signal under test input terminal VT-DATA, described aobvious
Show that the output terminal of data signal under test switch Mdn is connected with respective data lines；
4th transistor T4, the control terminal and input terminal short circuit of the 4th transistor T4, and with the of the capacitance C1
One end connects, and the output terminal of the 4th transistor T4 is connected with display test scanning signal input terminal VG；
5th transistor T5, the control terminal of the 5th transistor T5 are connected with the first end of the capacitance C1, and described
The input terminal of five transistor T5 is connected with display test scanning signal input terminal VG, the output terminal of the 5th transistor T5 and institute
State the Vcom connections of common electric voltage input terminal；
6th transistor T6, the control terminal and input terminal short circuit of the 6th transistor T6, and with the of the capacitance C1
One end connects, and the output terminal of the 6th transistor T6 is connected with the second end of the capacitance C1.
The discharge circuit that Figure 14 is provided, in display test, module test or display panel normal work display, first
Transistor T1 is turned on, and is charged for capacitance C1, after display test terminates, module test terminates or display panel powers off, capacitance
C1 driving second transistors T2, third transistor T3, the 4th transistor T4, the 5th transistor T5 and the 6th transistor T6 are opened.
The control terminal of 4th transistor T4 and input terminal short circuit, the 4th transistor T4 conductings, therefore pixel switch can be driven
Tpixel is opened, and accelerates the release of residual charge.5th transistor T5 is opened, and the input terminal of the 5th transistor T5 is surveyed with display
The VG connections of scanning signal input terminal are tried, the output terminal of the 5th transistor T5 is connected with the common electric voltage input terminal Vcom,
Therefore the charge remained in scan line can also release.6th transistor T6 is opened, and the control terminal of the 6th transistor
With input terminal short circuit, the 6th transistor T6 conductings are equivalent to, the first end of capacitance C1 described in the input terminal of the 6th transistor T6 connects
It connects, the output terminal of the 6th transistor T6 is connected with the second end of the capacitance C1, therefore can be in most at last capacitance C1
Charge releases.
Further, the discharge circuit of the display panel shown in Fig. 1-Figure 14 is applied in display panel, the display surface
Each scan line of plate is connected to input scanning signal with driving chip interface.
Figure 15 is the Contrast on effect schematic diagram using the discharge circuit shown in Figure 14 and the prior art, and above Figure 15 when is existing
There is no the simulated effect figure of discharge circuit in technology, lower section is the simulated effect figure using discharge circuit of the present invention, is shown
Example property, Figure 15 is using the discharge circuit shown in Figure 14.According to Figure 15, when there is no discharge circuit, pixel capacitance and
There is residual charge, therefore, the voltage difference between pixel electrode and public electrode is bigger, scan line and pixel electricity in scan line
The voltage difference of pole or public electrode is also bigger.After the discharge circuit described in the embodiment of the present invention, pixel capacitance and sweep
The charge retouched on line is released, therefore the voltage difference of pixel electrode and public electrode is substantially zeroed, and scan line and pixel electricity
The voltage difference of pole or public electrode is also substantially reduced.
It is described in detail below when display panel includes gate drivers, the concrete structure of the discharge circuit of display panel.
Figure 16 is the structure diagram of the discharge circuit of another display panel provided in an embodiment of the present invention, such as Figure 16 institutes
Show, the discharge circuit includes：
At least one the first transistor T1, and the control terminal of the first transistor T1 and input terminal short circuit, it is each described
Any one in the input terminal of the first transistor T1 and at least one clock signal input terminal of gate drivers is correspondingly connected with；
Second transistor T2, the control terminal of the second transistor T2 are connected with the output terminal of the first transistor T1,
The input terminal of the second transistor T2 is connected with common electric voltage input terminal Vcom, and the output terminal of the second transistor T2 is with showing
Show the VT-DATA connections of data signal under test input terminal；
Capacitance C1, the first end of the capacitance C1 are connected with the output terminal of the first transistor T1, the capacitance C1's
Second end is connected with the common electric voltage input terminal Vcom.
Figure 16 illustratively sets two clock signal input terminal i.e. CLK1 and CLK2 of the gate drivers, goes here and there respectively
Join a first transistor T1, in other embodiments, may be arranged as the clock signal input terminal series connection the of different number
One transistor T1.
It should be noted that the display panel in the embodiment of the present invention, which further includes other, supports its component worked normally
And structure, such as state display panel include a plurality of data lines and multi-strip scanning line, a plurality of data lines and multi-strip scanning line are exhausted
Edge, which overlaps, limits multiple pixel units, and each pixel unit includes a pixel switch Tpixel, the pixel switch Tpixel's
Control terminal is connected with corresponding scan line, and the input terminal of the pixel switch Tpixel is connected with respective data lines, the pixel
The output terminal of switch Tpixel is connected with pixel electrode；The display panel is provided with gate drivers, the gate drivers
It is connected to input scanning signal with corresponding scan line.Gate drivers include raster data model reset switch Tre, and raster data model resets
Signal input part Reset, low-level input VGL etc..
The embodiment of the present invention provides scanning signal by gate drivers for the pixel unit of display panel, in display panel
During normal work display or when module is tested, by clock signal clk 1 and CLK2, the first transistor T1 is turned on, for electricity
Hold C1 to charge, after display panel power-off or after module test, capacitance C1 driving second transistors T2 is opened, pixel switch
Tpixel leaks electricity naturally, so as to be discharged the charge remained in pixel capacitance Cpixel by second transistor T2.
Figure 17 is the structure diagram of the discharge circuit of another display panel provided in an embodiment of the present invention, such as Figure 17 institutes
Show, the display panel includes display test switch signal input end SWITCH, and the discharge circuit includes：
2 the first transistor T1, and the control terminal of the first transistor T1 and input terminal short circuit, a first transistor
The clock signal input terminal CLK1 connections of the input terminal and gate drivers of T1；The input terminal of another the first transistor T1 is with showing
Show test switch signal input end SWITCH connections；
Second transistor T2, the control terminal of the second transistor T2 are connected with the output terminal of the first transistor T1,
The input terminal of the second transistor T2 is connected with common electric voltage input terminal Vcom, and the output terminal of the second transistor T2 is with showing
Show the VT-DATA connections of data signal under test input terminal；
Capacitance C1, the first end of the capacitance C1 are connected with the output terminal of the first transistor T1, the capacitance C1's
Second end is connected with the common electric voltage input terminal Vcom.
7th transistor T7, the control terminal and input terminal short circuit of the 7th transistor T7, and with the of the capacitance C1
One end connects, and the output terminal of the 7th transistor T7 is connected with the control terminal of the display data signal under test switch Mdn, institute
The input terminal for stating display data signal under test switch Mdn is connected with display data signal under test input terminal VT-DATA, the display
The output terminal of data signal under test switch Mdn is connected with respective data lines.
Discharge circuit provided in an embodiment of the present invention, can both discharge display panel power-off and module tests remaining electricity
Lotus can also discharge display and test remaining charge.
Figure 18 is the structure diagram of the discharge circuit of another display panel provided in an embodiment of the present invention, such as Figure 18 institutes
Show, the discharge circuit includes：
2 the first transistor T1, and the control terminal of the first transistor T1 and input terminal short circuit, a first transistor
The clock signal input terminal CLK1 connections of the input terminal and gate drivers of T1；The input terminal and grid of another the first transistor T1
The clock signal input terminal CLK2 connections of driver；
Second transistor T2, the control terminal of the second transistor T2 are connected with the output terminal of the first transistor T1,
The input terminal of the second transistor T2 is connected with common electric voltage input terminal Vcom, and the output terminal of the second transistor T2 is with showing
Show the VT-DATA connections of data signal under test input terminal；
Capacitance C1, the first end of the capacitance C1 are connected with the output terminal of the first transistor T1, the capacitance C1's
Second end is connected with the common electric voltage input terminal Vcom；
8th transistor T8, the control terminal and input terminal short circuit of the 8th transistor T8, and with the of the capacitance C1
One end connects, and the output terminal of the 8th transistor T8 is connected with the control terminal of raster data model reset switch Tre, and the grid drives
The input terminal of dynamic reset switch Tre is connected with low level signal input terminal VGL, the output of the raster data model reset switch Tre
End is connected with corresponding scan line, control terminal and the raster data model reset signal input terminal of the raster data model reset switch Tre
Reset connections；
9th transistor T9, the control terminal and input terminal short circuit of the 9th transistor T9, and with the of the capacitance C1
One end connects, and the output terminal of the 9th transistor T9 is connected with low-level input VGL.
Discharge circuit provided in an embodiment of the present invention when display panel is worked normally and shown or when module is tested, leads to
Oversampling clock signal CLK1 and CLK2 turns on the first transistor T1, charges for capacitance C1, is surveyed in display panel power-off or module
After examination, capacitance C1 drives the 8th transistor T8 and the 9th transistor T9 conductings, and then leads raster data model reset switch Tre
Logical, then pixel switch Tpixel is opened, and capacitance C1 also drives second transistor T2 to open in addition, therefore residual charge can lead to
Cross pixel switch Tpixel and second transistor T2 releases.Since the 8th transistor T8 of setting and the 9th transistor T9 can make
Pixel switch Tpixel is opened, therefore the release of the residual charge accelerated.
Figure 19 is the structure diagram of the discharge circuit of another display panel provided in an embodiment of the present invention, such as Figure 19 institutes
Show, all clock signal input terminals and display test switch signal input end SWITCH of gate drivers are according to series connection one
The first transistor T1, and the 7th transistor T7, the 8th transistor T8 and the 9th transistor are additionally provided in the discharge circuit
T9 can not only accelerate the rate of release of display panel power-off and module test residual charge, may also speed up display test
The rate of release of remaining charge.
Figure 20 is the structure diagram of the discharge circuit of another display panel provided in an embodiment of the present invention, such as Figure 20 institutes
Show, the discharge circuit includes：
2 the first transistor T1, and the control terminal of the first transistor T1 and input terminal short circuit, a first transistor
The clock signal input terminal CLK1 connections of the input terminal and gate drivers of T1；The input terminal and grid of another the first transistor T1
The clock signal input terminal CLK2 connections of driver；
Second transistor T2, the control terminal of the second transistor T2 are connected with the output terminal of the first transistor T1,
The input terminal of the second transistor T2 is connected with common electric voltage input terminal Vcom, and the output terminal of the second transistor T2 is with showing
Show the VT-DATA connections of data signal under test input terminal；
Capacitance C1, the first end of the capacitance C1 are connected with the output terminal of the first transistor T1, the capacitance C1's
Second end is connected with the common electric voltage input terminal Vcom；
8th transistor T8, the control terminal and input terminal short circuit of the 8th transistor T8, and with the of the capacitance C1
One end connects, and the output terminal of the 8th transistor T8 is connected with the control terminal of raster data model reset switch Tre, and the grid drives
The input terminal of dynamic reset switch Tre is connected with low level signal input terminal VGL, the output of the raster data model reset switch Tre
End is connected with corresponding scan line, control terminal and the raster data model reset signal input terminal of the raster data model reset switch Tre
Reset connections；
Tenth transistor T10, the control terminal of the tenth transistor T10 is connected with the first end of the capacitance C1, described
The input terminal of tenth transistor T10 is connected with low-level input VGL, output terminal and the public affairs of the tenth transistor T10
The Vcom connections of common voltage input terminal.
The operation principle of discharge circuit shown in Figure 20 is as follows：It is surveyed when display panel is worked normally and shown or in module
During examination, clock signal input terminal CLK1 and CLK2 the control the first transistor T1 conductings of gate drivers are charged for capacitance C1,
After display panel power-off or after module test, capacitance C1 drives the 8th transistor T8 conductings, and the tenth transistor T10 is beaten
It opens, raster data model reset switch Tre is opened, in addition, capacitance C1 driving second transistors T2 is opened, since the raster data model is answered
The output terminal of bit switch Tre is connected with corresponding scan line, so display panel power-off or module test remain in pixel capacitance
Charge in Cpixel and the charge remained in scan line can be discharged by second transistor T2.
Figure 21 is the structure diagram of the discharge circuit of another display panel provided in an embodiment of the present invention, such as Figure 21 institutes
Show, the discharge circuit includes：
3 the first transistor T1, and the control terminal of the first transistor T1 and input terminal short circuit, a first transistor
The clock signal input terminal CLK1 connections of the input terminal and gate drivers of T1；The input terminal and grid of one the first transistor T1
The clock signal input terminal CLK2 connections of driver；The input terminal of another the first transistor T1 and display test switching signal are defeated
Enter SWITCH is held to connect；
Second transistor T2, the control terminal of the second transistor T2 are connected with the output terminal of the first transistor T1,
The input terminal of the second transistor T2 is connected with common electric voltage input terminal Vcom, and the output terminal of the second transistor T2 is with showing
Show the VT-DATA connections of data signal under test input terminal；
Capacitance C1, the first end of the capacitance C1 are connected with the output terminal of the first transistor T1, the capacitance C1's
Second end is connected with the common electric voltage input terminal Vcom；
7th transistor T7, the control terminal and input terminal short circuit of the 7th transistor T7, and with the of the capacitance C1
One end connects, and the output terminal of the 7th transistor T7 is connected with the control terminal of the display data signal under test switch Mdn, institute
The input terminal for stating display data signal under test switch Mdn is connected with display data signal under test input terminal VT-DATA, the display
The output terminal of data signal under test switch Mdn is connected with respective data lines；
8th transistor T8, the control terminal and input terminal short circuit of the 8th transistor T8, and with the of the capacitance C1
One end connects, and the output terminal of the 8th transistor T8 is connected with the control terminal of raster data model reset switch Tre, and the grid drives
The input terminal of dynamic reset switch Tre is connected with low level signal input terminal VGL, the output of the raster data model reset switch Tre
End is connected with corresponding scan line, control terminal and the raster data model reset signal input terminal of the raster data model reset switch Tre
Reset connections；
Tenth transistor T10, the control terminal of the tenth transistor T10 is connected with the first end of the capacitance C1, described
The input terminal of tenth transistor T10 is connected with low-level input VGL, output terminal and the public affairs of the tenth transistor T10
The Vcom connections of common voltage input terminal.
The embodiment of the present invention can not only discharge display panel power-off and module tests remaining charge, can also discharge
Remaining charge is tested in display, and due to being provided with the 8th transistor T8 and the tenth transistor T10, is surveyed for display
The charge that examination, module test and display panel power-off are remained in scan line can also discharge.Concrete operating principle refers to
The detailed description of Figure 19, therefore not to repeat here for the embodiment of the present invention.
Figure 22 is the structure diagram of the discharge circuit of another display panel provided in an embodiment of the present invention, such as Figure 22 institutes
Show, the discharge circuit includes：
2 the first transistor T1, and the control terminal of the first transistor T1 and input terminal short circuit, a first transistor
The clock signal input terminal CLK1 connections of the input terminal and gate drivers of T1；The input terminal and grid of another the first transistor T1
The clock signal input terminal CLK2 connections of driver；
Second transistor T2, the control terminal of the second transistor T2 are connected with the output terminal of the first transistor T1,
The input terminal of the second transistor T2 is connected with common electric voltage input terminal Vcom, and the output terminal of the second transistor T2 is with showing
Show the VT-DATA connections of data signal under test input terminal；
Capacitance C1, the first end of the capacitance C1 are connected with the output terminal of the first transistor T1, the capacitance C1's
Second end is connected with the common electric voltage input terminal Vcom；
11st transistor T11, the control terminal and input terminal short circuit of the 11st transistor T11, and with the capacitance
The first end connection of C1, the output terminal of the 11st transistor T11 are connected with the second end of the capacitance C1.
After charge of the discharge circuit provided in an embodiment of the present invention after the power-off of release display panel or module test, may be used also
By opening the 11st transistor T11, the charge in capacitance C1 to be discharged.
It should be noted that two clock signal output terminals series connection first of the Figure 22 illustratively on gate drivers is brilliant
Body pipe T1, as long as at least one clock signal output terminal in other embodiments on the gate drivers is connected one
The first transistor T1.If display panel further includes display test switch signal input end SWITCH, then can be only aobvious
Show test switch signal input end SWITCH one the first transistor T1 of series connection, it can also be defeated in display test switching signal simultaneously
Enter to hold at least one clock signal output terminal of SWITCH and gate drivers series connection the first transistor T1.And institute
When stating display panel includes display test switch signal input end SWITCH, also need to set the 7th transistor T7, the described 7th is brilliant
The connection mode of body pipe T7 refers to Figure 17.
It should be noted that the discharge circuit of the above-mentioned display panel including gate drivers, as long as including first crystal
Pipe T1, second transistor T2 and capacitance C1, and be attached according to the connection relation described in the various embodiments described above, you can realization pair
The release of residual charge can also include at least the 7th transistor T7, the 8th transistor T8, the 9th transistor on this basis
It is at least one in T9, the tenth transistor T10 and the 11st transistor T11, and closed according to the connection described in the various embodiments described above
System is configured, and accordingly completes respective function.Figure 23 is the electric discharge electricity of another display panel provided in an embodiment of the present invention
The structure diagram on road, as shown in figure 23, the discharge circuit include：Second transistor T2, the 7th transistor T7, the 8th crystal
Pipe T8, the 9th transistor T9, the tenth transistor T10, the 11st transistor T11, capacitance C1 and at least one the first transistor
T1, wherein, control terminal and the input terminal short circuit of each the first transistor T1, the input terminal and high potential of the first transistor T1
At least one clock signal input terminal of input terminal VGH, display test switch signal input end SWITCH and gate drivers
In any one be correspondingly connected with, Figure 23 illustratively sets 3 the first transistor T1, the input terminal of a first transistor T1
It is connected with the clock signal input terminal CLK1 of gate drivers；The input terminal of one the first transistor T1 and gate drivers when
The CLK2 connections of clock signal input part；The input terminal of another the first transistor T1 and display test switch signal input end SWITCH
Connection；The control terminal of the second transistor T2 is connected with the output terminal of the first transistor T1, the second transistor T2
Input terminal be connected with common electric voltage input terminal Vcom, the output terminal of the second transistor T2 and display data signal under test are defeated
Enter VT-DATA is held to connect；The first end for stating capacitance C1 is connected with the output terminal of the first transistor T1, and the of the capacitance C1
Two ends are connected with the common electric voltage input terminal Vcom.The control terminal and input terminal short circuit of the 7th transistor T7, and with institute
State the first end connection of capacitance C1, the control of the output terminal and display data signal under test switch Mdn of the 7th transistor T7
End connection, the input terminal of the display data signal under test switch Mdn is with showing data signal under test input terminal VT-DATA phases
Even, the output terminal of the display data signal under test switch Mdn is connected with respective data lines.The control of the 8th transistor T8
End and input terminal short circuit, and be connected with the first end of the capacitance C1, the output terminal and raster data model of the 8th transistor T8
The control terminal connection of reset switch Tre, input terminal and the low level signal input terminal VGL of the raster data model reset switch Tre
Connection, the output terminal of the raster data model reset switch Tre are connected with corresponding scan line, the raster data model reset switch Tre
Control terminal be connected with raster data model reset signal input terminal Reset；The control terminal and input terminal of the 9th transistor T9 is short
It connects, and is connected with the first end of the capacitance C1, the output terminal of the 9th transistor T9 is connected with low-level input VGL.
The control terminal of the tenth transistor T10 is connected with the first end of the capacitance C1, the input terminal of the tenth transistor T10 with
Low-level input CGL connections, the output terminal of the tenth transistor T10 are connected with the common electric voltage input terminal Vcom.The
11 transistor T11, the control terminal and input terminal short circuit of the 11st transistor T11, and with the first end of the capacitance C1
Connection, the output terminal of the 11st transistor T11 are connected with the second end of the capacitance C1.The discharge circuit that Figure 21 is provided exists
When display test, module test or display panel normal work display, the first transistor T1 conductings are charged for capacitance C1, when
After display test completion, module test completion or display panel power-off, capacitance C1 driving second transistors T2, the 7th transistor
T7, the 8th transistor T8, the 9th transistor T9, the tenth transistor T10 are opened.Due to the 8th transistor T8 and the 9th transistor T9
It opens, turns on raster data model reset switch Tre, therefore pixel switch Tpixel is opened, and accelerates electricity in pixel capacitance Cpixel
The release of lotus.Since the 8th transistor T8 and the tenth transistor T10 is opened, raster data model reset switch Tre is opened, in addition, electric
Hold C1 driving second transistors T2 to open, since the output terminal of the raster data model reset switch Tre is connected with corresponding scan line,
So the charge remained in scan line can be discharged by second transistor T2.
Figure 24 is the Contrast on effect schematic diagram using the discharge circuit shown in Figure 23 and the prior art, as shown in figure 24, figure
In the prior art without the simulated effect figure of discharge circuit during 24 top, lower section is using the discharge circuit described in Figure 23 of the present invention
Simulated effect figure.According to Figure 15, when there is no discharge circuit, there is residual charge on pixel capacitance and scan line,
Therefore, the voltage difference between pixel electrode and public electrode is bigger, scan line and the voltage difference of pixel electrode or public electrode
Also it is bigger.After the discharge circuit described in the embodiment of the present invention, the charge on pixel capacitance and scan line is released,
Therefore the voltage difference of pixel electrode and public electrode is substantially zeroed, and scan line and the voltage difference of pixel electrode or public electrode
It is substantially reduced.
On the basis of the various embodiments described above, optionally, the first transistor, second transistor, third transistor with
And the 5th transistor of the 4th transistor, the 6th transistor, the 7th transistor, the 8th transistor, the 9th transistor, the tenth transistor
Conduction type with the 11st transistor can be N-type or p-type.
Further, it is preferred that the 5th transistor of the second transistor, third transistor and the 4th transistor,
At least one in six transistors, the 7th transistor, the 8th transistor, the 9th transistor, the tenth transistor and the 11st transistor
The scope of a or several channel width-over-length ratio is (1:200,200:1).The benefit so set is can be surveyed to avoid in display
Cause the generation of leaky when examination, module test and display panel normal work display.
The embodiment of the present invention also provides a kind of display device.The display device includes the electric discharge described in the various embodiments described above
Circuit.It should be noted that display device provided in an embodiment of the present invention, which further includes other, supports the normal work of display device
The component of work.The display device for example can be any one in mobile phone, tablet computer, Electronic Paper, digital photo frame.
Note that it above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various apparent variations,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above example to the present invention
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
It can include other more equivalent embodiments, and the scope of the present invention is determined by scope of the appended claims.
Claims (16)
1. a kind of discharge circuit of display panel, which is characterized in that including：
At least one the first transistor, and the control terminal of the first transistor and input terminal short circuit, each first crystal
At least one clock of the input terminal of pipe and high potential input terminal, display test switch signal input end and gate drivers
Any one in signal input part is correspondingly connected with；
One second transistor, the control terminal of the second transistor are connected with the output terminal of the first transistor, and described second
The input terminal of transistor is connected with common electric voltage input terminal, and the output terminal and display data signal under test of the second transistor are defeated
Enter end connection；
One capacitance, the first end of the capacitance are connected with the output terminal of the first transistor, the second end of the capacitance and institute
State the connection of common electric voltage input terminal.
2. discharge circuit according to claim 1, which is characterized in that the display panel includes a plurality of data lines and a plurality of
Scan line, a plurality of data lines and the overlapping multiple pixel units of restriction of multi-strip scanning line insulation, each pixel unit include one
Pixel switch, the control terminal of the pixel switch are connected with corresponding scan line, the input terminal of the pixel switch and corresponding number
It is connected according to line, the output terminal of the pixel switch is connected with pixel electrode；Each scan line and driving chip of the display panel
Interface is connected to input scanning signal, control terminal and the high potential input terminal and display test switching signal of each the first transistor
Any one correspondence in input terminal is connected；
If the display panel includes display test switch signal input end, the discharge circuit further includes：
Third transistor, control terminal and the input terminal short circuit of the third transistor, and be connected with the first end of the capacitance, institute
The output terminal for stating third transistor is opened respectively with the control terminal of display test scanning signal switch and display data signal under test
The control terminal connection of pass, the input terminal of the display test scanning signal switch are connected with display test scanning signal input terminal,
The output terminal of the display test scanning signal switch is connected with corresponding scan line, the display data signal under test switch
Input terminal is connected with display data signal under test input terminal, the output terminal and corresponding data of the display data signal under test switch
Line is connected.
3. discharge circuit according to claim 2, which is characterized in that the discharge circuit further includes：
4th transistor, the control terminal and input terminal short circuit of the 4th transistor, and be connected with the first end of the capacitance, institute
The output terminal for stating the 4th transistor is connected with display test scanning signal input terminal.
4. discharge circuit according to claim 2, which is characterized in that the discharge circuit further includes：
5th transistor, the control terminal of the 5th transistor are connected with the first end of the capacitance, the 5th transistor
Input terminal is connected with display test scanning signal input terminal, output terminal and the common electric voltage input terminal of the 5th transistor
Connection.
5. discharge circuit according to claim 2, which is characterized in that the discharge circuit further includes：
6th transistor, the control terminal and input terminal short circuit of the 6th transistor, and be connected with the first end of the capacitance, institute
The output terminal for stating the 6th transistor is connected with the second end of the capacitance.
6. discharge circuit according to claim 1, which is characterized in that the display panel includes a plurality of data lines and a plurality of
Scan line, a plurality of data lines and the overlapping multiple pixel units of restriction of multi-strip scanning line insulation, each pixel unit include one
Pixel switch, the control terminal of the pixel switch are connected with corresponding scan line, the input terminal of the pixel switch and corresponding number
It is connected according to line, the output terminal of the pixel switch is connected with pixel electrode；The display panel is provided with gate drivers, described
Gate drivers are connected to input scanning signal with corresponding scan line, and the control terminal of each the first transistor is tested with the display
Any one correspondence at least one clock signal input terminal of switch signal input end and the gate drivers is connected；
When the control terminal of the first transistor is corresponding with the display test switch signal input end to be connected, the discharge circuit is also
Including：
7th transistor, the control terminal and input terminal short circuit of the 7th transistor, and be connected with the first end of the capacitance, institute
The output terminal for stating the 7th transistor is connected with the control terminal of display data signal under test switch, and the display data signal under test is opened
The input terminal of pass with display data signal under test input terminal be connected, it is described display data signal under test switch output terminal with it is corresponding
Data cable is connected.
7. discharge circuit according to claim 6, which is characterized in that the discharge circuit further includes：
8th transistor, the control terminal and input terminal short circuit of the 8th transistor, and be connected with the first end of the capacitance, institute
The output terminal for stating the 8th transistor is connected with the control terminal of raster data model reset switch, the input of the raster data model reset switch
End is connected with low level signal input terminal, and the output terminal of the raster data model reset switch is connected with corresponding scan line, the grid
The control terminal of pole driving reset switch is connected with raster data model reset signal input terminal；
9th transistor, the control terminal and input terminal short circuit of the 9th transistor, and be connected with the first end of the capacitance, institute
The output terminal for stating the 9th transistor is connected with low-level input.
8. discharge circuit according to claim 6, which is characterized in that the discharge circuit further includes：
8th transistor, the control terminal and input terminal short circuit of the 8th transistor, and be connected with the first end of the capacitance, institute
The output terminal for stating the 8th transistor is connected with the control terminal of raster data model reset switch, the input of the raster data model reset switch
End is connected with low level signal input terminal, and the output terminal of the raster data model reset switch is connected with corresponding scan line, the grid
The control terminal of pole driving reset switch is connected with raster data model reset signal input terminal；
Tenth transistor, the control terminal of the tenth transistor are connected with the first end of the capacitance, the tenth transistor
Input terminal is connected with low-level input, and the output terminal of the tenth transistor is connected with the common electric voltage input terminal.
9. discharge circuit according to claim 6, which is characterized in that the discharge circuit further includes：
11st transistor, the control terminal and input terminal short circuit of the 11st transistor, and connect with the first end of the capacitance
It connects, the output terminal of the 11st transistor is connected with the second end of the capacitance.
10. according to the discharge circuit described in claim 3, which is characterized in that the first transistor, second transistor,
The conduction type of three transistors and the 4th transistor be N-type or p-type, the second transistor, third transistor and the 4th
The scope of any one or several channel width-over-length ratios in transistor is (1:200,200:1).
11. according to the discharge circuit described in claim 4, which is characterized in that the first transistor, second transistor,
The conduction type of three transistors and the 5th transistor be N-type or p-type, the second transistor, third transistor and the 5th
The scope of any one or several channel width-over-length ratios in transistor is (1:200,200:1).
12. according to the discharge circuit described in claim 5, which is characterized in that the first transistor, second transistor,
The conduction type of three transistors and the 6th transistor be N-type or p-type, the second transistor, third transistor and the 6th
The scope of any one or several channel width-over-length ratios in transistor is (1:200,200:1).
13. according to any discharge circuit in claim 7, which is characterized in that the first transistor, the second crystal
The conduction type of pipe, the 7th transistor, the 8th transistor and the 9th transistor is N-type or p-type, the second transistor, the
The scope of any one or several channel width-over-length ratios in seven transistors, the 8th transistor and the 9th transistor is (1:200,
200:1)。
14. according to any discharge circuit in claim 8, which is characterized in that the first transistor, the second crystal
The conduction type of pipe, the 7th transistor, the 8th transistor and the tenth transistor is N-type or p-type, the second transistor, the
The scope of any one or several channel width-over-length ratios in seven transistors, the 8th transistor and the tenth transistor is (1:200,
200:1)。
15. according to any discharge circuit in claim 9, which is characterized in that the first transistor, the second crystal
Pipe, the conduction type of the 7th transistor and the 11st transistor are N-type or p-type, the second transistor, the 7th transistor with
And the 11st in transistor any one or it is several, the scope of channel width-over-length ratio is (1:200,200:1).
16. a kind of display device, which is characterized in that including any discharge circuits of claim 1-15.
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| CN106097995A (en) * | 2016-06-13 | 2016-11-09 | 深圳市华星光电技术有限公司 | The driving method of a kind of display floater and the driving means of display floater |
| KR102594791B1 (en) * | 2016-12-28 | 2023-10-30 | 엘지디스플레이 주식회사 | Liquid Crystal Display Device |
| CN107886922A (en) * | 2017-12-08 | 2018-04-06 | 南京中电熊猫平板显示科技有限公司 | Liquid crystal display device and the method for improving liquid crystal display device power down splashette |
| CN108492792B (en) * | 2018-03-30 | 2021-09-17 | 京东方科技集团股份有限公司 | Liquid crystal display, shutdown discharge circuit of liquid crystal display and driving method thereof |
| CN110400531B (en) * | 2019-07-29 | 2022-08-23 | 昆山龙腾光电股份有限公司 | Neutralization circuit and display panel |
| TWI799244B (en) * | 2022-04-26 | 2023-04-11 | 友達光電股份有限公司 | Pixel circuit and power supply method for power-off sequence thereof |
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