CN105244322B

CN105244322B - The forming method of semiconductor structure

Info

Publication number: CN105244322B
Application number: CN201410272775.4A
Authority: CN
Inventors: 邓浩
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2014-06-18
Filing date: 2014-06-18
Publication date: 2018-12-21
Anticipated expiration: 2034-06-18
Also published as: CN105244322A

Abstract

A kind of forming method of semiconductor structure, comprising: substrate is provided, is formed with groove in the substrate；The precursor material layer for filling the full groove is formed using mobility chemical vapor deposition process；The precursor material is made annealing treatment, converts first medium layer for precursor material layer, nitrogen-atoms is contained in the first medium layer material, and the nitrogen-atoms has the first atomic quantity；Nitrogen-atoms in the first medium layer material is replaced using oxygen atom, converts second dielectric layer for first medium layer, nitrogen-atoms has the second atomic quantity in the second medium layer material, and the second atomic quantity is less than the first atomic quantity.The present invention reduces the quantity of Si-N key and Si-N-H key in second dielectric layer by the method for oxygen atom displacement nitrogen-atoms, to improve the compactness and hardness of the second dielectric layer of formation, optimizes the electric property of semiconductor structure.

Description

The forming method of semiconductor structure

Technical field

The present invention relates to field of semiconductor fabrication technology, in particular to a kind of forming method of semiconductor structure.

Background technique

With the development of manufacture of semiconductor technology, the faster flash of access speed has been developed in terms of storage device Device (flash memory).Flash memory is acted with can repeatedly carry out deposit, reading and erasing of information etc., and be stored in The characteristic that information will not disappear after a loss of power, therefore, flash memory has become PC and electronic equipment is adopted extensively A kind of nonvolatile memory.Wherein, flash memory mainly divides NAND gate flash according to the difference of array structure Device and nor gate flash memory, since NAND gate flash memory is higher than the integrated level of nor gate flash memory, so with NOT gate flash memory has wider array of application range.

Typical NAND gate flash memory as floating grid (floating gate) and is controlled using the polysilicon that adulterates Grid (control gate)；Wherein, control grid is formed on floating grid, and is separated by by dielectric layer between grid；Floating gate Pole is formed on substrate, is separated by by one layer of tunneling medium layer (tunnel oxide).When to flash memory progress information When write operation, by being biased in control grid with source/drain regions, make in electron injection floating grid；Reading quick flashing When memorizer information, apply an operating voltage in control grid, the electriferous state of floating grid will affect channel below at this time (channel) ON/OFF, and the ON/OFF of this channel is to judge the foundation of the value of information 0 or 1；When flash memory is believed in erasing When breath, by substrate, source region, drain region or the relative potentials raising for controlling grid, and make electronics by floating grid using tunneling effect Enter substrate, in source region or drain region across tunneling medium layer, or passes through dielectric layer between grid and enter in control grid.

With the continuous reduction of semiconductor structure size, the electric property of the semiconductor structure containing flash memory and can Need to be further increased by property.

Summary of the invention

Problems solved by the invention is to provide a kind of forming method of semiconductor structure, improves and uses mobility chemical gaseous phase The consistency and hardness for the dielectric layer that depositing operation is formed, improve the performance of dielectric layer material.

To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, comprising: substrate is provided, in institute It states and is formed with groove in substrate；The precursor material layer for filling the full groove is formed using mobility chemical vapor deposition process； The precursor material is made annealing treatment, first medium layer is converted by precursor material layer, in the first medium layer material Containing nitrogen-atoms, and the nitrogen-atoms has the first atomic quantity；It is replaced in the first medium layer material using oxygen atom First medium layer is converted second dielectric layer by nitrogen-atoms, and nitrogen-atoms has the second atomicity in the second medium layer material Amount, and the second atomic quantity is less than the first atomic quantity.

Optionally, silicon atom and nitrogen-atoms are included at least in the precursor material layer material.

Optionally, the precursor material that the mobility chemical vapor deposition process uses includes three silicon substrate nitrogen, silane, two Silane, methyl-monosilane, dimethylsilane, trimethyl silane, tetramethylsilane, ethyl orthosilicate, triethoxysilane, prestox One of cyclotetrasiloxane, tetramethyl disiloxane, tetramethyl-ring tetrasiloxane, trimethylsilyl amine, dimethyl silanyl amine Or it is several.

Optionally, the mobility chemical vapor deposition process carries out under nitrogenous atmosphere.

Optionally, the method for the nitrogen-atoms of the first medium layer material is replaced using oxygen atom are as follows: go using oxygen containing Ionized water carries out immersion treatment to the first medium layer.

Optionally, the oxygen element in the oxygen containing deionized water is ozone ion.

Optionally, the mass percent of ozone ion is 5% to 25% in the oxygen containing deionized water.

Optionally, the when a length of 30min to 60min of the immersion treatment, temperature when immersion treatment is 50 degree to 80 degree.

Optionally, it further comprises the steps of: and plasma bombardment is carried out to the second medium layer surface.

Optionally, the technological parameter of the plasma bombardment are as follows: the plasma is by He, Ne, Xe, Kr or Ar gas Plasmarized formation, He, Ne, Xe, Kr or Ar gas flow be 50sccm to 500sccm, low frequency RF power be 100 watts extremely 1500 watts, HFRF power is 100 watts to 1500 watts.

Optionally, the annealing carries out under oxygen-containing atmosphere.

Optionally, the anneal duration of the annealing includes continuous first duration, the second duration and third duration, In, the annealing temperature in the first duration is the first temperature, and the annealing temperature in the second duration is by the first temperature increment to the second temperature It spends, the annealing temperature in third duration is second temperature.

Optionally, first temperature is 200 degree to 450 degree, and the second temperature is 550 degree to 650 degree.

Optionally, it further comprises the steps of: and the second annealing is carried out to the second dielectric layer；It is etched back to removal segment thickness Second dielectric layer.

Optionally, the technological parameter of second annealing are as follows: annealing temperature is 800 degree to 950 degree, and anneal duration is 20min to 40min.

Optionally, the substrate includes substrate, positioned at the tunneling medium layer of substrate surface and positioned at tunneling medium layer table The floating gate conductive layer in face.

Optionally, it is etched back to the second dielectric layer of removal segment thickness, is made at the top of remaining second dielectric layer lower than floating gate Conductive layer top surface.

Optionally, it further comprises the steps of: in the floating gate conductive layer top surface and sidewall surfaces, remaining second dielectric layer Surface forms dielectric layer between grid；Dielectric layer surface forms control grid conductive layer between the grid.

Optionally, the processing step for forming the groove includes: to form patterned cover in the floating gate conductive layer surface Film layer；Using the patterned mask layer as exposure mask, the lining of the floating gate conductive layer, tunneling medium layer and segment thickness is etched Bottom forms groove.

Optionally, after forming first medium layer, removal is higher than patterned exposure mask layer surface the is further comprised the steps of: One dielectric layer；Remove the patterned mask layer.

Compared with prior art, technical solution of the present invention has the advantage that

In the embodiment of the present invention, the precursor material layer for filling full groove is formed using mobility chemical vapor deposition process, The precursor material layer is made annealing treatment, first medium layer is converted by precursor material layer, contains in first medium layer material There is nitrogen-atoms, and nitrogen-atoms has the first atomic quantity；Using the nitrogen-atoms in atomic substitutions first medium layer material, by first Dielectric layer is converted into second dielectric layer, and nitrogen-atoms has the second atomic quantity, and the second atom in the second medium layer material Quantity is less than the first atomic quantity.Si-N key and Si-N-H bond number amount are more in first medium layer, and set using oxygen atom After changing the nitrogen-atoms in first medium layer, Si-N key and Si-N-H bond number amount significantly reduce in the second dielectric layer of formation, And the quantity of Si-O key and O-Si-O key obviously increases in second dielectric layer, the compactness and hardness of second dielectric layer are mentioned Height improves the performance of the second dielectric layer of formation, and then optimizes the electric property of semiconductor structure.

Further, the oxygen element in the oxygen containing deionized water is ozone ion, the oxygen content of ozone ion it is high and Activity is high in aqueous solution, is easy to spread into first medium layer, improves the efficiency of oxygen atom displacement nitrogen-atoms.

Further, the embodiment of the invention also includes steps: plasma bombardment is carried out to second medium layer surface, in high energy Under the plasma bombardment of amount, second dielectric layer surface property is improved, and further increases the densification of second medium layer surface Property.

Further, in the embodiment of the present invention after forming first medium layer, removal is higher than the of patterned mask layer One dielectric layer, so that the thickness of first medium layer is thinning, therefore during immersion treatment, oxygen atom diffuses into first medium Diffusion path in layer shortens, and oxygen atom diffuses into the reduction of the difficulty in first medium layer, to improve oxygen atom displacement nitrogen The efficiency of atom；The duration for reducing immersion treatment simultaneously minimizes adverse effect caused by immersion treatment, improves second medium The performance of layer.

Further, substrate includes substrate, positioned at the tunneling medium layer of substrate surface and positioned at tunnel in the embodiment of the present invention Wear the floating gate conductive layer of dielectric layer surface；It is etched back to the second dielectric layer of removal segment thickness, makes remaining second dielectric layer top Portion is lower than floating gate conductive layer top surface, exposes floating gate Conductive layer portions sidewall surfaces, increases floating gate conductive layer and control gate Overlapping area between conductive layer increases the coupling efficiency of semiconductor structure, optimizes the electric property and reliability of semiconductor structure.

Further, since the embodiment of the present invention is using the second dielectric layer material formed after oxygen atom displacement nitrogen-atoms Can be higher, second dielectric layer compactness and hardness are high, and it is etched back to technique and reaches unanimity to each region etch rate of second dielectric layer, Therefore work as and be etched back to after the completion of technique, remaining second dielectric layer surface flatness is higher, so that in the second dielectric layer table The thickness uniformity of dielectric layer is high between the grid that face is formed, and improves the electric property and reliability of semiconductor structure.

Detailed description of the invention

Fig. 1 is the flow diagram of an embodiment method for forming semiconductor structure；

Fig. 2 to Figure 12 be another embodiment of the present invention provides semiconductor structure formed process the schematic diagram of the section structure.

Specific embodiment

It can be seen from background technology that the electric property and reliability for the semiconductor structure that the prior art is formed are to be improved.

Studied for the forming method of semiconductor structure, referring to FIG. 1, the forming method of semiconductor structure include with Lower step: step S1, providing substrate, successively forms tunneling medium layer, positioned at Tunnel dielectric layer surface in the substrate surface Floating gate conductive layer；Step S2, the substrate of the floating gate conductive layer, tunneling medium layer and segment thickness is etched, groove is formed；Step Rapid S3, the dielectric layer for filling the full groove is formed, and the dielectric layer surface is higher than floating gate conductive layer surface；Step S4, it returns The dielectric layer of etching removal segment thickness, exposes floating gate conductive layer sidewall surfaces；Step S5, in the remaining dielectric layer table Face, floating gate conductive layer sidewall surfaces and top surface form dielectric layer between grid；Step S6, the dielectric layer surface shape between the grid At control grid conductive layer.

With the continuous reduction of semiconductor structure size, the electric property of the semiconductor structure formed using the above method is become Difference, reliability are lower.It has been investigated that after the dielectric layer for being etched back to removal segment thickness, remaining dielectric layer surface Can it is poor, remaining dielectric layer surface is uneven, cause dielectric layer surface formation grid between dielectric layer it is in uneven thickness, this It is an one of the major reasons for leading to the electric property difference of semiconductor structure.It is found through analysis, causes to be etched back to rear dielectric layer The reason of surface irregularity, is as follows:

With the continuous reduction of semiconductor structure size, the width of groove constantly reduces, in the trench filled media layer Difficulty is increasing, in order to improve filling gap (gap-filling) ability of dielectric layer, avoids filled media material in the trench Cavity is formed when material wherein, the precursor material for generalling use mobility forms the precursor material layer for filling full groove.As one A embodiment forms the technique for filling the precursor material layer of full groove using mobility chemical vapor deposition (FCVD, Flowable CVD) technology, and then the dielectric layer for filling full groove is formed, specifically, forming the processing step packet for filling the dielectric layer of full groove It includes: forming the precursor material layer for filling full groove using FCVD technology, contain silicon atom and nitrogen-atoms in precursor material layer material； Curing process is carried out to the precursor material layer, precursor material layer is changed into dielectric layer.

Above-mentioned curing process is usually the annealing carried out under oxygen-containing atmosphere, sends out the material of oxygen and precursor material layer Raw reaction, forms one or both of Si-O or O-Si-O, nitrogen-atoms is taken out of from forerunner's material layer, makes precursor material layer It is changed into the dielectric layer of isolation structure.If the temperature of annealing is excessively high, it will cause the precursor material layers of flute surfaces short Dielectric layer is completely transformed into time, the compactness of the dielectric layer of flute surfaces is relatively strong and oxygen is caused to be difficult to enter channel bottom Precursor material layer in, the transforming degree of the precursor material layer of channel bottom is limited, and therefore, annealing is generally moved back using lower Fiery temperature (less than 700 degrees Celsius).

However, the annealing temperature of annealing is lower and other adverse effects can be brought, specifically, due to annealing temperature Limitation lower, that the material of oxygen and precursor material layer chemically reacts, after the completion of curing process, in precursor material layer Nitrogen atom content it is still higher, the content of Si-N key and Si-N-H key is higher in precursor material layer, the Si-N key and Si-N- The compactness for the dielectric layer that the presence of H key results in is poor, and the quality of dielectric layer is softer.When to the compactness difference and quality When softer dielectric layer is etched back processing, it is etched back to technique and the etch rate in each region of dielectric layer surface is difficult to tend to one It causes, therefore after the completion of being etched back to, the rough state of remaining dielectric layer surface presentation, between the grid for causing dielectric layer surface The thickness uniformity of dielectric layer is poor, and then causes the reliability of semiconductor structure and electric property poor.

For this purpose, the present invention provides a kind of forming method of semiconductor structure, substrate is provided, is formed with ditch in the substrate Slot；The precursor material layer for filling the full groove is formed using mobility chemical vapor deposition process；To the precursor material into Row annealing, converts first medium layer for precursor material layer, contains nitrogen-atoms in the first medium layer material, and described Nitrogen-atoms has the first atomic quantity；Nitrogen-atoms in the first medium layer material is replaced using oxygen atom, by first medium Layer is converted into second dielectric layer, and nitrogen-atoms has the second atomic quantity, and the second atomic quantity in the second medium layer material Less than the first atomic quantity.The present invention reduces Si-N in second dielectric layer by using the method for oxygen atom displacement nitrogen-atoms With the quantity of Si-N-H key, the quantity of Si-O and O-Si-O key in second dielectric layer is increased, to improve second dielectric layer Consistency and hardness, optimize the electric property and reliability of semiconductor structure.

To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention Specific embodiment be described in detail.

Referring to FIG. 2, providing substrate, the substrate includes substrate 200, the tunneling medium layer 201 positioned at 200 surface of substrate And the floating gate conductive layer 202 positioned at 201 surface of tunneling medium layer.

The material of the substrate 200 is the silicon on silicon, germanium, SiGe, GaAs, silicon carbide or insulator.The present embodiment In, the material of the substrate 200 is silicon.

The tunneling medium layer 201 is used for isolation liner bottom 200 and floating gate conductive layer 202.

The material of the tunneling medium layer 201 be silica, silicon nitride or silicon oxynitride, formation process be thermal oxidation method or Chemical vapour deposition technique.

In the present embodiment, the material of the tunneling medium layer 201 is silica, with a thickness of 50 angstroms to 150 angstroms, using hot oxygen Change method is formed.

After forming tunneling medium layer 201, further comprises the steps of: and well region ion doping is carried out to substrate 200.Specifically, When the semiconductor structure of formation is PMOS device, N-type ion is carried out to substrate 200 and adulterates to form N-type well region；The semiconductor of formation When structure is NMOS device, P-type ion is carried out to substrate 200 and adulterates to form P type trap zone.

The material of the floating gate conductive layer 202 is polysilicon, is formed by chemical vapor deposition process and diffusion technique.

In the present embodiment, the floating gate conductive layer 202 is formed by depositing polysilicon and phosphorus doping, the floating gate conductive layer 202 with a thickness of 200 angstroms to 2000 angstroms.

The present embodiment done so that the semiconductor structure that is formed is flash memory as an example it is exemplary illustrated, in other embodiments In, the semiconductor structure of formation may be transistor.

It is described patterned to cover referring to FIG. 3, form patterned mask layer 203 on 202 surface of floating gate conductive layer Film layer 203 has the opening 204 for exposing 202 surface of floating gate conductive layer.

The material of the patterned mask layer 203 is silicon oxide or silicon nitride, and the patterned mask layer 203 is single Layer structure or multilayer lamination structure, the present embodiment do exemplary theory so that the patterned mask layer 203 is single layer structure as an example It is bright.

The position of the opening 204 and size correspond to position and the size for the isolation structure being subsequently formed.

As one embodiment, the forming step of the patterned mask layer 203 includes: in the floating gate conductive layer 202 surfaces form original mask layer；Patterned photoresist layer is formed in the original mask layer surface；With described patterned Photoresist layer is exposure mask, etches the original mask layer, forms patterned mask layer 203, the patterned mask layer 203 With opening 204；Remove the patterned photoresist layer.

In the present embodiment, the material of the patterned mask layer 203 is silicon nitride, the patterned mask layer 203 With a thickness of 2000 angstroms to 10000 angstroms.

Referring to FIG. 4, being exposure mask with the patterned mask layer 203, described in opening 204 (please referring to Fig. 3) etching The substrate 200 of floating gate conductive layer 202, tunneling medium layer 201 and segment thickness forms groove 205.

In the present embodiment, using dry etch process, it is sequentially etched floating gate conductive layer 202, tunneling medium layer 201 and portion Divide the substrate 200 of thickness.

As a specific embodiment, the dry etch process is reactive ion etching, reactive ion etching process Technological parameter are as follows: etching gas HBr, He and O₂, wherein HBr flow is 100sccm to 600sccm, and He flow is 100sccm to 600sccm, O₂Flow is 2sccm to 20sccm, and reaction chamber pressure is 5 supports to 50 supports, bias voltage 50V To 300V.

The full groove 205 (please referring to Fig. 4) is filled referring to FIG. 5, being formed using mobility chemical vapor deposition process Precursor material layer 206, the precursor material layer 206 is also covered in patterned 203 surface of mask layer.

During carrying out mobility chemical deposition process, substrate 200 is maintained within the scope of predetermined temperature, makes to flow Property chemical vapor deposition process pre-reaction material material it is flowable be filled into groove 205, so that it is full to form filling The precursor material layer 206 of groove 205.Particularly, lower 200 temperature of substrate (being lower than 150 DEG C) can keep pre-reaction material Mobility and viscosity of the material in substrate 200 and groove 205.

Since pre-reaction material material has certain mobility and viscosity, in the pre-reaction material material that will have mobility After material is packed into groove 205,205 bottom of groove fill without cavity, empty so as to avoid generating in 205 bottom of groove Hole；Also, due to the precursor material layer 206 of formation have certain flowability and viscosity, it is subsequent first annealing, adopt After oxygen atom displacement nitrogen-atoms, the chemical bond of 206 material of precursor material layer can occur to be broken and recombinate, and form new chemical bond Or functional group, to convert precursor material layer 206 to the second dielectric layer of isolation structure.

In the present embodiment, during carrying out mobility chemical vapor deposition process, the temperature of substrate 200 less than 150 DEG C, For example, the temperature of substrate 200 is 20 DEG C, 50 DEG C, 70 DEG C or 110 DEG C etc..

The pre-reaction material material that the mobility chemical vapor deposition process uses includes: three silicon substrate nitrogen (TSA), silicon Alkane, disilane, methyl-monosilane, dimethylsilane, trimethyl silane, tetramethylsilane, ethyl orthosilicate, triethoxysilane, Octamethylcy-clotetrasiloxane, tetramethyl disiloxane, tetramethyl-ring tetrasiloxane, trimethylsilyl amine, dimethyl silanyl amine It is one or more of.The pre-reaction materials materials such as other silanamines and its derivative can also be used.

The mobility chemical vapor deposition process carries out under nitrogenous atmosphere, and the nitrogenous atmosphere is H₂And N₂Gaseous mixture Body, N₂、NH₃、NH₄OH、N₂H₄、NO、N₂O、NO₂、O₃、O₂、H₂O₂One or more of atmosphere, and contain including at least one kind The atmosphere of nitrogen.

In the present embodiment, pre-reaction material material using three base silicon nitrogen as mobility chemical vapor deposition process, NH₃The mobility chemical vapor deposition process is carried out under atmosphere.

Specifically, the substrate 200 of specific groove 205 is placed in reaction chamber, mobility chemical vapor deposition process ginseng Number are as follows: pre-reaction material material is entered in reaction chamber with the flow velocity of 100sccm to 3000sccm, NH₃Extremely with 20sccm The flow velocity of 1000sccm enters in reaction chamber, and reaction chamber pressure is 0.1T to 10T, and reaction chamber temperature is 20 DEG C to 150 DEG C, can also be passed through the inert gases such as Ar, He or Xe into reaction chamber, inert gas flow velocity be 1000sccm extremely 10000sccm。

In an embodiment of the present invention, Si is contained in the pre-reaction material, and mobility chemical vapor deposition process exists It is carried out under nitrogenous atmosphere, therefore includes at least silicon atom and nitrogen-atoms in 206 material of precursor material layer, before described Driving in 206 material of material layer further includes hydrogen atom.Specifically, containing Si-H, Si-N or Si- in the precursor material layer 206 formed The chemical bonds such as N-H, in subsequent treatment process, nitrogen-atoms can be replaced these chemical bonds by O atom, make afore mentioned chemical key by O- Replaced Si-O or Si-O, forming material SiO₂Second dielectric layer.

In other embodiments, when substrate includes graphics intensive area (dense) and figure rarefaction (ISO), in figure First groove is formed in the substrate of compact district, while second groove is formed in the substrate of figure rarefaction, and first groove Size is less than second groove；So, the precursor material for filling full first groove is formed using mobility chemical vapor deposition process After layer, since the size of first groove is less than second groove, second groove is not filled full yet, then using high vertical wide than chemistry Gas-phase deposition forms the dielectric material for filling full second groove.

Referring to FIG. 6, the first annealing is carried out to the precursor material layer 206 (please referring to Fig. 5), by precursor material layer 206 are converted into first medium layer 207, nitrogen-atoms are contained in 207 material of first medium layer, and the nitrogen-atoms has first Atomic quantity.

Contain silicon atom, nitrogen-atoms and oxygen atom in 207 material of first medium layer.First annealing is containing It is carried out under oxygen atmosphere, for example, being passed through O into the first annealing chamber₃、O₂Or H₂One of O steam or multiple gases.

Under the effect of the first annealing, Si -- H bond, Si-N key, Si-N-H key in precursor material layer 206 are broken, And the O atom in oxygen-containing atmosphere enters in precursor material layer 206, and Si key, N key and the H key of fracture are in conjunction with the O atom of surrounding New chemical bond is formed, such as Si-O-H key and N-O-H key, to make the materials from oxidizing of precursor material layer 206, by forerunner's material The bed of material 206 is changed into first medium layer 207, includes Si-O key, O-Si-O key, Si-O- in the material of the first medium layer 207 H key, Si -- H bond and N-O-H key.

Since 206 surface of precursor material layer is the region contacted at first with O atom, if in the initial rank of the first annealing Section annealing temperature is excessively high, then the material of 206 surface region of precursor material layer can be rapidly performed by conversion under conditions of high temperature, Cause the compactness of 206 surface region material of precursor material layer good, O atom reaches the difficulty of 206 bottom section of precursor material layer Increase.

For this purpose, in the present embodiment, the anneal duration of the first annealing includes continuous first duration, the second duration and the Three durations, wherein the annealing temperature in the first duration is the first temperature, and the annealing temperature in the second duration is by the first temperature increment To second temperature, the annealing temperature in third duration is second temperature, and the first temperature is less than second temperature.Wherein, first when It grows and when third a length of zero or non-zero duration.

Due to first annealing initial stage (i.e. in the first duration) have lower annealing temperature, avoid due to 206 surface soundness of precursor material layer it is excessively high and caused by adverse effect so that O atom more adequately with precursor material layer 206 Bottom section is in contact, and improves the quality of the first medium layer 207 of formation.

Specifically, first temperature is 200 degree to 450 degree, the second temperature is 550 degree to 650 degree, described to be incremented by Mode are as follows: linear formula is incremented by, parabolic is incremented by or exponential function formula is incremented by.

Referring to FIG. 7, removal is higher than the first medium layer 207 on patterned mask layer 203 (please referring to Fig. 6) surface；It goes Except the patterned mask layer 203.

It is higher than the first medium layer 207 on patterned 203 surface of mask layer using CMP process removal, so that Remaining 207 top surface of first medium layer is flushed with patterned 203 top surface of mask layer.

The patterned mask layer 203 is removed using wet-etching technology etching, it is described as a specific embodiment The etch liquids of wet-etching technology are hot phosphoric acid solution, wherein the mass percent of phosphoric acid is 65% to 85%, solution temperature It is 120 degree to 200 degree.

Referring to FIG. 8, the nitrogen-atoms in first medium layer 207 (the please referring to Fig. 7) material is replaced using oxygen atom, it will First medium layer 207 is converted into second dielectric layer 208, and nitrogen-atoms has the second atomicity in 208 material of second dielectric layer Amount, and the second atomic quantity is less than the first atomic quantity.

Although when experience first makes annealing treatment, precursor material the Si-N key in 206 (please referring to Fig. 5), Si-N-H layer by layer A degree of fracture can occur for key, reconfigure to form Si-O key, Si-O-H key, Si -- H bond and N-O-H key, however due to by To the influence of the factors such as the first annealing annealing temperature, the ability of oxygen atom displacement nitrogen-atoms is still limited, and the first of formation Nitrogen atom content in 207 material of dielectric layer is still higher, that is, the content of Si-N key and Si-N-H key is still higher, the Si- The presence of N key and Si-H-N key, the material property that will cause first medium layer 207 is poor, for example, the cause of first medium layer 207 Density is poor, and quality is softer；If subsequent be directly etched back processing to first medium layer 207, it will lead to and be etched back to handle It is different to the etch rate in each region of first medium layer 207,207 surface irregularity of first medium layer after being etched back to is caused, Thickness of dielectric layers uniformity between the grid that influence is subsequently formed.

For this purpose, the present embodiment is after forming first medium layer 207, it further include step, using oxygen atom displacement first medium Nitrogen-atoms in 207 material of layer, converts second dielectric layer 208,208 material of second dielectric layer for first medium layer 207 Middle nitrogen-atoms has the second atomic quantity, and the second atomic quantity is less than the first atomic quantity.That is, second dielectric layer The quantity of Si-N key and Si-N-H key in 208 materials reduces, to improve the material property of second dielectric layer 208, improves 208 consistency of second dielectric layer and hardness.

In the present embodiment, using the method for nitrogen-atoms in 207 material of oxygen atom displacement first medium layer are as follows: using oxygen containing Deionized water carries out immersion treatment 209 to the first medium layer 207, and the oxonium ion in oxygen-containing deionized water can diffuse into the In one dielectric layer 207, the binding ability between oxonium ion and silicon ion is stronger than the binding ability between Nitrogen ion and silicon ion, because This is after oxonium ion diffuses into first medium layer 207, Si-N key and the fracture of Si-N-H key, and oxonium ion and post-rift Si Bond closes and forms Si-O key or O-Si-O key, 208 material of second dielectric layer is converted by 207 material of first medium layer, to make It is fewer than nitrogen atom content in 207 material of first medium layer to obtain nitrogen atom content in 208 material of second dielectric layer, so that second medium The quantity of Si-N key or Si-N-H key in 208 material of layer greatly reduces, and improves the performance of 208 material of second dielectric layer.

During immersion treatment 209, first medium layer 207 is coated by oxygen containing deionized water completely, it is oxygen containing go from Sub- water diffuses into first medium layer 207 everywhere from 207 surface of first medium layer, to realize oxygen atom displacement nitrogen faster Atom.

Due to active higher, the oxygen containing deionization water oxygen described in the present embodiment of ozone ion in deionized water Element is ozone ion.

If the mass percent of ozone ion is too low, active lower, the oxygen atom displacement nitrogen-atoms of oxygen-containing deionized water Energy it is low；And the mass percent of ozone ion also suffers from the limitation of the solid solubility of ozone ion in deionized water, when When Quality Mgmt Dept's percentage of ozone ion reaches a certain amount of, ozone ion is difficult to continue to be dissolved in deionized water；Meanwhile if ozone The mass percent of ion is excessively high, may cause to aoxidize to the active area in substrate 200, influence the performance of active area.

Therefore in the present embodiment, the mass percent of ozone ion is 5% to 25% in oxygen containing deionized water.

If the duration of immersion treatment 209 is too short, ozone ion diffuses into the limitation in first medium layer 207, It is still higher to will cause number of nitrogen atoms in 208 material of second dielectric layer to be formed；If the duration of immersion treatment 209 is too long, the One dielectric layer 207 due to deionized water effect and generate deformation；If the temperature of immersion treatment 209 is too low, oxygen-containing deionized water In ozone ion activity it is too low, the difficulty diffused into first medium layer 207 is larger；If the temperature mistake of immersion treatment 209 Height, the high temperature can cause other adverse effects to first medium layer 207.

In the present embodiment, the when a length of 30min to 60min of the immersion treatment 209, temperature when immersion treatment 209 is 50 degree to 80 degree.

The present embodiment carries out immersion treatment 209 after carrying out chemical mechanical polish process to first medium layer 207 again, due to The first medium layer 207 higher than patterned exposure mask layer surface is eliminated, the thickness of first medium layer 207 is thinning, therefore ozone The diffusion path of ion shortens, and more ozone ions can be reached faster in first medium layer 207, improves oxygen atom and sets Change the effect and efficiency of nitrogen-atoms.

Referring to FIG. 9, carrying out the second annealing 210 to the second dielectric layer 208.

Second annealing 210 arranges the hydrogen atom in second dielectric layer 208 for drying second dielectric layer 208 Out, the consistency and hardness of second dielectric layer 208 are further increased.

As a specific embodiment, it is described second annealing 210 technological parameter are as follows: annealing temperature be 800 degree extremely 950 degree, anneal duration is 20min to 40min.

In other embodiments, when being formed using high vertical width than chemical vapor deposition process in the groove in figure rarefaction When having dielectric material, second annealing is also used to improve the performance of the dielectric material；Also, using high vertical wide ratio Chemical vapor deposition process is formed before dielectric material, and precursor material layer is also formed in the groove of figure rarefaction, then First annealing above-mentioned and plasma bombardment are also applied for the precursor material layer in the groove of figure rarefaction, make figure Precursor material layer in the groove of rarefaction is converted into the high second dielectric layer of compactness high rigidity.

Referring to FIG. 10, carrying out plasma bombardment 211 to 208 surface of second dielectric layer.

Using 208 surface of ion bombardment second dielectric layer with high-energy, so that 208 surface region of second dielectric layer Compactness is further enhanced, when subsequent when being etched back to second dielectric layer 208, the initial stage for being etched back to technique (i.e. Etch 208 surfacing of second dielectric layer) in, etch rate of the etching technics to each region in 208 surface of second dielectric layer Consistency improves.

As a specific embodiment, the technological parameter of the plasma bombardment 211 are as follows: the plasma by He, Ne, Xe, Kr or Ar gaseous plasma are formed, and He, Ne, Xe, Kr or Ar gas flow are 50sccm to 500sccm, low frequency Radio-frequency power is 100 watts to 1500 watts, and HFRF power is 100 watts to 1500 watts.

After experience immersion treatment 209 and plasma bombardment 211, the performance of second dielectric layer 208 is significantly improved, The compactness and hardness of second dielectric layer 208 are improved.

Figure 11 is please referred to, the second dielectric layer 208 of removal segment thickness is etched back to, pushes up remaining second dielectric layer 208 Portion is lower than 202 top surface of floating gate conductive layer.

In the present embodiment, it is etched back to the second dielectric layer 208 of removal segment thickness, exposes the portion of floating gate conductive layer 202 Divide sidewall surfaces, with the overlapping area controlled between grid conductive layer for increasing floating gate conductive layer 202 and being subsequently formed, raising is partly led The coupling efficiency of body structure reduces the operating voltage of semiconductor structure, optimizes the electric property of semiconductor structure.

The technique being etched back to is wet etching, as a specific embodiment, the etch liquids of the wet etching For hydrofluoric acid solution, wherein the volume ratio of hydrofluoric acid and deionized water is 1:300 to 1:700.

In the present embodiment, due to using oxygen atom displacement nitrogen-atoms, compared with first medium layer 207, second dielectric layer Si-N key and Si-N-H key in 208 materials considerably reduce, and the quantity of Si-O key and O-Si-O key significantly increases, therefore Compared with first medium layer 207, the consistency and hardness of 208 material of second dielectric layer are significantly improved.It is situated between to second When matter layer 208 is etched back processing, since 208 material density of second dielectric layer and hardness are higher, technique is etched back to The etch rate in each region of second medium layer 208 is consistent, therefore works as and be etched back to after the completion of technique, remaining 208 table of second dielectric layer Face flatness with higher, avoids the generation of uneven defect.

Figure 12 is please referred to, in 202 top surface of floating gate conductive layer and sidewall surfaces, 208 surface shape of second dielectric layer At dielectric layer 212 between grid, 212 surface of dielectric layer forms control grid conductive layer 213 between the grid.

Dielectric layer 212 is the insulating layer between floating gate conductive layer 202 and control grid conductive layer 213 between the grid.Between the grid The material of dielectric layer 212 is one or more of silicon oxide or silicon nitride, and dielectric layer 212 can be single layer structure between the grid It may be multilayered structure.

The formation process of dielectric layer 212 is chemical vapor deposition, thermal oxidation method or physical vapour deposition (PVD) between the grid.

In the present embodiment, dielectric layer 212 is multilayered structure between the grid, and dielectric layer 212 is oxide skin(coating), nitrogen between the grid The laminated construction (ONO:oxide-nitride-oxide) of compound layer and oxide skin(coating), between the grid dielectric layer 212 with a thickness of 50 angstroms to 200 angstroms, dielectric layer 212 between the grid is formed using chemical vapor deposition process.

The material of the control grid conductive layer 213 is the polysilicon of polysilicon or doping, the control grid conductive layer 213 With a thickness of 500 angstroms to 2000 angstroms, the control grid conductive layer 213 is formed using chemical vapor deposition.

In the present embodiment, after being etched back to second dielectric layer 208, remaining 208 surface flatness of second dielectric layer is high, because The thickness uniformity that this is located at dielectric layer 212 between the grid on 208 surface of second dielectric layer is good, to improve the electricity of semiconductor structure Performance.

Subsequent processing step includes: graphical dielectric layer 212, floating gate conductive layer between the control grid conductive layer 213, grid 202 and tunneling medium layer 201, form gate structure.

To sum up, the technical solution of the forming method of semiconductor structure provided by the invention has the advantage that

Firstly, the precursor material layer for filling full groove is formed using mobility chemical vapor deposition process, to the forerunner Material layer is made annealing treatment, and converts first medium layer for precursor material layer, nitrogen-atoms is contained in first medium layer material, and Nitrogen-atoms has the first atomic quantity；Using the nitrogen-atoms in atomic substitutions first medium layer material, first medium layer is converted For second dielectric layer, nitrogen-atoms has the second atomic quantity in the second medium layer material, and the second atomic quantity is less than the One atomic quantity.Si-N key and Si-N-H bond number amount are more in first medium layer, and the first medium after using oxygen atom After nitrogen-atoms in layer, Si-N key and Si-N-H bond number amount significantly reduce in the second dielectric layer of formation, and second medium The quantity of Si-O key and O-Si-O key obviously increases in layer, and the compactness and hardness of second dielectric layer are improved, and improves and is formed Second dielectric layer performance, and then optimize semiconductor structure electric property.

Secondly, using the method for oxygen atom displacement nitrogen-atoms to soak using oxygen containing deionized water to first medium layer Bubble processing, since in immersion treatment, first medium layer is enveloped by oxygen containing deionized water completely, oxonium ion can be from first Dielectric layer surface is diffused into everywhere in first medium layer, to improve the effect and efficiency of oxygen atom displacement nitrogen-atoms.

Also, the when a length of 30min to 60min of the immersion treatment guarantees the oxonium ion diffusion in oxygen-containing deionized water Each region into first medium layer；And temperature when immersion treatment is 50 degree to 80 degree, under the conditions of the temperature, is contained The activity of oxonium ion is higher in the deionized water of oxygen, diffuses into first medium layer and the ability for replacing nitrogen-atoms is stronger, make The effect for obtaining oxygen atom displacement nitrogen-atoms is more preferable.

Again, substrate includes substrate, positioned at the tunneling medium layer of substrate surface and positioned at the floating of Tunnel dielectric layer surface Grid conductive layer, after the second dielectric layer for being etched back to removal segment thickness, the partial sidewall surface of floating gate conductive layer is exposed Come, so that the overlapping area between floating gate conductive layer and control grid conductive layer increases, improves the coupling efficiency of semiconductor structure, drop The operating voltage of low semiconductor structure.

Simultaneously as the compactness and hardness of the second dielectric layer formed after oxygen atom displacement nitrogen-atoms are higher, it is etched back to When second dielectric layer, the technique that is etched back to is uniform to the etch rate in each region of second dielectric layer, therefore is etched back to handle High at rear remaining second dielectric layer surface flatness, the thickness of dielectric layer is equal between the grid of remaining second medium layer surface Even property is good, to improve the reliability and electric property of semiconductor structure.

Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the range of restriction.

Claims

1. a kind of forming method of semiconductor structure characterized by comprising

Substrate is provided, is formed with groove in the substrate；

The precursor material layer for filling the full groove is formed using mobility chemical vapor deposition process；

The precursor material is made annealing treatment, converts first medium layer, the first medium layer material for precursor material layer Contain nitrogen-atoms in material, and the nitrogen-atoms has the first atomic quantity；

Nitrogen-atoms in the first medium layer material is replaced using oxygen atom, converts second dielectric layer for first medium layer, Nitrogen-atoms has the second atomic quantity in the second medium layer material, and the second atomic quantity is less than the first atomic quantity；

The anneal duration of the annealing includes continuous first duration, the second duration and third duration, wherein the first duration Interior annealing temperature is the first temperature, and the annealing temperature in the second duration is by the first temperature increment to second temperature, third duration Interior annealing temperature is second temperature, and first temperature is 200 degree to 450 degree, and the second temperature is 550 degree to 650 degree.

2. the forming method of semiconductor structure as described in claim 1, which is characterized in that in the precursor material layer material at least Including silicon atom and nitrogen-atoms.

3. the forming method of semiconductor structure as described in claim 1, which is characterized in that the mobility chemical vapor deposition work The precursor material that skill uses includes three silicon substrate nitrogen, silane, disilane, methyl-monosilane, dimethylsilane, trimethyl silane, four Methyl-monosilane, ethyl orthosilicate, triethoxysilane, octamethylcy-clotetrasiloxane, tetramethyl disiloxane, tetramethyl cyclotetrasiloxane silicon One or more of oxygen alkane, trimethylsilyl amine, dimethyl silanyl amine.

4. the forming method of semiconductor structure as described in claim 1, which is characterized in that the mobility chemical vapor deposition work Skill carries out under nitrogenous atmosphere.

5. the forming method of semiconductor structure as described in claim 1, which is characterized in that be situated between using oxygen atom displacement described first The method of the nitrogen-atoms of matter layer material are as follows: immersion treatment is carried out to the first medium layer using oxygen containing deionized water.

6. the forming method of semiconductor structure as claimed in claim 5, which is characterized in that the oxygen in the oxygen containing deionized water Element is ozone ion.

7. the forming method of semiconductor structure as claimed in claim 6, which is characterized in that the oxygen containing deionization ozone in water The mass percent of ion is 5% to 25%.

8. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that the immersion treatment when it is a length of 30min to 60min, temperature when immersion treatment are 50 degree to 80 degree.

9. the forming method of semiconductor structure as described in claim 1, which is characterized in that further comprise the steps of: and be situated between to described second Matter layer surface carries out plasma bombardment.

10. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that the technique of the plasma bombardment Parameter are as follows: the plasma is formed by He, Ne, Xe, Kr or Ar gaseous plasma, He, Ne, Xe, Kr or Ar gas stream Amount is 50sccm to 500sccm, and low frequency RF power is 100 watts to 1500 watts, and HFRF power is 100 watts to 1500 watts.

11. the forming method of semiconductor structure as described in claim 1, which is characterized in that the annealing is in oxygen-containing atmosphere Lower progress.

12. the forming method of semiconductor structure as described in claim 1, which is characterized in that further comprise the steps of: and be situated between to described second Matter layer carries out the second annealing；It is etched back to the second dielectric layer of removal segment thickness.

13. the forming method of semiconductor structure as claimed in claim 12, which is characterized in that the technique of second annealing Parameter are as follows: annealing temperature is 800 degree to 950 degree, and anneal duration is 20min to 40min.

14. the forming method of semiconductor structure as claimed in claim 12, which is characterized in that the substrate includes substrate, is located at The tunneling medium layer of substrate surface and floating gate conductive layer positioned at Tunnel dielectric layer surface.

15. the forming method of semiconductor structure as claimed in claim 14, which is characterized in that be etched back to the of removal segment thickness Second medium layer makes at the top of remaining second dielectric layer lower than floating gate conductive layer top surface.

16. the forming method of semiconductor structure as claimed in claim 15, which is characterized in that further comprise the steps of: in the floating gate Conductive layer top surface and sidewall surfaces, remaining second medium layer surface form dielectric layer between grid；The dielectric layer between the grid Surface forms control grid conductive layer.

17. the forming method of semiconductor structure as claimed in claim 14, which is characterized in that form the processing step of the groove It include: to form patterned mask layer in the floating gate conductive layer surface；Using the patterned mask layer as exposure mask, institute is etched The substrate of floating gate conductive layer, tunneling medium layer and segment thickness is stated, groove is formed.

18. the forming method of semiconductor structure as claimed in claim 17, which is characterized in that after forming first medium layer, Further comprise the steps of: the first medium layer that removal is higher than patterned exposure mask layer surface；Remove the patterned mask layer.