CN105242435A - Array substrate, manufacturing method and liquid crystal display panel - Google Patents
Array substrate, manufacturing method and liquid crystal display panel Download PDFInfo
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- CN105242435A CN105242435A CN201510732914.1A CN201510732914A CN105242435A CN 105242435 A CN105242435 A CN 105242435A CN 201510732914 A CN201510732914 A CN 201510732914A CN 105242435 A CN105242435 A CN 105242435A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/13338—Input devices, e.g. touch panels
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses an array substrate, a manufacturing method and a liquid crystal display panel. The array substrate comprises a base, a first passivation layer arranged on the base, a touch signal layer arranged on the first passivation layer, a second passivation layer arranged on the touch signal layer and the exposed first passivation layer, a first electrode layer arranged on the second passivation layer, a third passivation layer arranged on the first electrode layer and the exposed second passivation layer and a second electrode layer arranged on the third passivation layer. According to the array substrate, the manufacturing method and the liquid crystal display panel, the storage capacitance value in pixels of the array substrate can be increased.
Description
Technical field
The present invention relates to technical field of liquid crystal display, specifically, relate to a kind of array base palte and method for making, display panels.
Background technology
Because low temperature polycrystalline silicon LTPS has the advantage of high mobility, when carrying out Pixel Design, what adopt the breadth length ratio of the TFT switch of LTPS making just can design is very little, thus be conducive to the design realizing higher PPI (PixelsPerInch, the number of pixels that per inch has) product.In the last few years, the favor of Ge Jia panel factory is subject to owing to adopting the thickness that contact panel processing procedure is simple, liquid crystal cell is overall of LTPS to reduce.When PPI increases, elemental area will obviously reduce.So for single pixel, the memory capacitance of its correspondence also can diminish thereupon.Along with the reduction of memory capacitance, pixel will die down to the storage capacity of electric charge, when electric leakage occurs TFT, will have a strong impact on the display effect of display panels.
Summary of the invention
For overcoming the above problems, the invention provides a kind of array base palte and method for making, display panels, in order to increase the storage capacitance value in the pixel of array base palte.
According to an aspect of the present invention, provide a kind of array base palte, comprising:
Substrate;
First passivation layer, it is arranged in described substrate;
Touching signals layer, it is arranged on described first passivation layer;
Second passivation layer, it is arranged on described touching signals layer and the first exposed passivation layer;
First electrode layer, it is arranged on described second passivation layer;
3rd passivation layer, it is arranged on described first electrode layer and the second exposed passivation layer;
The second electrode lay, it is arranged on described 3rd passivation layer.
According to one embodiment of present invention, described first electrode layer is pixel electrode layer, and described the second electrode lay is common electrode layer.
According to one embodiment of present invention, described first electrode layer is common electrode layer, and described the second electrode lay is pixel electrode layer.
According to one embodiment of present invention, described touching signals layer and described pixel electrode layer have overlapping region, and it is communicated with described common electrode layer with the via hole of described 3rd passivation layer by through described second passivation layer, described first electrode layer.
According to one embodiment of present invention, described touching signals layer and described pixel electrode layer have overlapping region, and it is communicated with described common electrode layer by the via hole of through described second passivation layer.
According to one embodiment of present invention, the electrode in described first electrode layer is plane-shape electrode, and the electrode in described the second electrode lay is strip shaped electric poles.
According to one embodiment of present invention, described substrate comprises:
Light shield layer, it is arranged on substrate;
First insulation course, it is arranged on described light shield layer and exposed substrate;
Polysilicon active layers, it is arranged on described first insulation course;
Second insulation course, it is arranged on described polysilicon active layers and the first exposed insulation course;
Grid layer, it is arranged on described second insulation course, in order to form the grid of thin film transistor (TFT);
3rd insulation course, it is arranged on described grid layer and the second exposed insulation course;
Signals layer, it is arranged on described 3rd insulation course, in order to the source electrode that forms thin film transistor (TFT) and drain electrode and with described source electrode and the signal wire be connected that drains;
Flatness layer, it is arranged on described signals layer and the 3rd exposed insulation course,
Wherein, described source electrode is communicated with described pixel electrode layer with the via hole of described second passivation layer by through described flatness layer, described first passivation layer, described touching signals layer.
According to one embodiment of present invention, described substrate comprises:
Light shield layer, it is arranged on substrate;
First insulation course, it is arranged on described light shield layer and exposed substrate;
Polysilicon active layers, it is arranged on described first insulation course;
Second insulation course, it is arranged on described polysilicon active layers and the first exposed insulation course;
Grid layer, it is arranged on described second insulation course, in order to form the grid of thin film transistor (TFT);
3rd insulation course, it is arranged on described grid layer and the second exposed insulation course;
Signals layer, it is arranged on described 3rd insulation course, in order to the source electrode that forms thin film transistor (TFT) and drain electrode and with described source electrode and the signal wire be connected that drains;
Flatness layer, it is arranged on described signals layer and the 3rd exposed insulation course,
Wherein, described source electrode is communicated with described pixel electrode layer with the via hole of described 3rd passivation layer by through described flatness layer, described first passivation layer, described touching signals layer, described second passivation layer, described first electrode layer.
According to another aspect of the present invention, additionally provide a kind of method for making for array base palte described in above any one, comprising:
Substrate forms light shield layer;
Described light shield layer and exposed substrate form the first insulation course;
Described first insulation course forms polysilicon active layers;
Described polysilicon active layers and the first exposed insulation course form the second insulation course;
Described second insulation course forms the grid layer corresponding with described polysilicon active layers, in order to form the grid of thin film transistor (TFT);
Described grid layer and the second exposed insulation course form the 3rd insulation course;
Described 3rd insulation course forms signals layer, in order to the source electrode that forms thin film transistor (TFT) and drain electrode and with described source electrode and the signal wire be connected that drains;
Described signals layer and the 3rd exposed insulation course form flatness layer;
Described flatness layer is formed the first passivation layer;
Described first passivation layer forms touching signals layer;
Described touching signals layer and the first exposed passivation layer form the second passivation layer;
Described second passivation layer forms the first electrode layer;
Described first electrode layer and the second exposed passivation layer form the 3rd passivation layer;
Described 3rd passivation layer forms the second electrode lay.
According to another aspect of the present invention, a kind of display panels adopting array base palte described in above any one is additionally provided.
Beneficial effect of the present invention:
Insulation course in traditional array substrate between pixel electrode layer and common electrode layer is not only two-layerly reduced to one deck by original by the present invention, adds somewhat to the storage capacitance value of pixel.Meanwhile, also add the memory capacitance formed between touching signals layer and pixel electrode layer, compared with traditional LTPS pixel embedded touch control panel, in the present invention array base palte pixel in storage capacitance value had and increased considerably.
Other features and advantages of the present invention will be set forth in the following description, and, partly become apparent from instructions, or understand by implementing the present invention.Object of the present invention and other advantages realize by structure specifically noted in instructions, claims and accompanying drawing and obtain.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, do simple introduction by accompanying drawing required in embodiment or description of the prior art below:
Fig. 1 a is the TFT place cross section structure schematic diagram of traditional LTPS pixel embedded touch control panel;
Fig. 1 b is the cross section structure schematic diagram that Fig. 1 a is corresponding at data line place;
Fig. 2 a is the display panels TFT place cross section structure schematic diagram of employing according to an embodiment of the invention array base palte of the present invention; And
Fig. 2 b is the cross section structure schematic diagram that Fig. 2 a is corresponding at data line place.
Embodiment
Describe embodiments of the present invention in detail below with reference to drawings and Examples, to the present invention, how application technology means solve technical matters whereby, and the implementation procedure reaching technique effect can fully understand and implement according to this.It should be noted that, only otherwise form conflict, each embodiment in the present invention and each feature in each embodiment can be combined with each other, and the technical scheme formed is all within protection scope of the present invention.
Being the TFT place cross section structure schematic diagram of traditional LTPS pixel embedded touch control panel as shown in Figure 1a, is cross section structure schematic diagram corresponding to Fig. 1 a data line place as shown in Figure 1 b.From Fig. 1 a and Fig. 1 b, the array base palte side of this traditional LTPS pixel embedded touch control panel is included in the light shield layer 112 that substrate 111 is formed, the first insulation course 113 that light shield layer 112 and exposed substrate 111 are formed, the polysilicon active layers 114 that insulation course 113 is formed, the second insulation course 115 that polysilicon active layers 114 is formed, the grid layer 117 corresponding with polysilicon active layers 114 that second insulation course 115 is formed, the 3rd insulation course 118 that grid layer 117 and the second exposed insulation course 115 are formed, the signals layer 116 comprising source-drain electrode and signal wire that 3rd insulation course 118 is formed, the flatness layer 119 that signals layer 116 and the 3rd exposed insulation course 118 are formed, the common electrode layer 120 that flatness layer 119 is formed, the first passivation layer 121 that common electrode layer 120 and exposed flatness layer 119 are formed, the touching signals layer 122 that first passivation layer 121 is formed, the second passivation layer 123 that touch signal layer 122 and the first exposed passivation layer 121 are formed, at the pixel electrode layer 124 that the second passivation layer 123 is formed, color membrane substrates side is included in the black-matrix layer 127 that substrate 126 is formed, the red resistance layer 128 that black-matrix layer 127 and exposed substrate 126 are formed and green resistance layer 129, the flatness layer 130 that red resistance layer 128 and green resistance layer 129 are formed, the main chock insulator matter 131 that flatness layer 130 is formed and auxiliary chock insulator matter 132, also comprise the liquid crystal molecule 130 between array base palte and color membrane substrates.
From Fig. 1 a and Fig. 1 b, there is passivation layers between pixel electrode 124 and public electrode 120, i.e. the first passivation layer 121 and the second passivation layer 123, these two passivation layers form the dielectric layer of the memory capacitance between pixel electrode 124 and public electrode 120.When carrying out high PPI product design, because passivation layers increases the distance between pixel electrode 124 and public electrode 120, according to capacitance equation: C=ε S/d, C is capacitance, ε is the specific inductive capacity of dielectric material between pole plate, and S is polar plate area, and d is polar plate spacing.Polar plate spacing d increase can cause capacitance to reduce, and this will cause memory capacitance corresponding to pixel cell cannot meet the demand of product.
Therefore, the invention provides a kind of novel array base palte, passivation layer quantity between pixel electrode on it and public electrode is reduced, when carrying out higher PPI product design, effectively can increase the memory capacitance between pixel electrode and public electrode, solve the problem because pixel causes display abnormal due to storage capacity not.
Be the display panels TFT place cross section structure schematic diagram of employing according to an embodiment of the invention array base palte of the present invention as shown in Figure 2 a, Fig. 2 b is depicted as Fig. 2 a cross section structure schematic diagram corresponding at data line place.Below with reference to Fig. 2 a and Fig. 2 b, the present invention is described in detail.
This array base palte comprises the common electrode layer 225 of substrate, the first passivation layer 220 that substrate is formed, the touching signals layer 221 that the first passivation layer 220 is formed, the second passivation layer 222 that touching signals layer 221 and the first exposed passivation layer 220 are formed, the pixel electrode layer 223 that the second passivation layer 222 is formed, the 3rd passivation layer 224 that pixel electrode layer 223 and the second exposed passivation layer 222 are formed, formation on the 3rd passivation layer 224.Herein, for pixel electrode layer 223 as the first electrode layer, common electrode layer 225 is described as the second electrode lay.
From Fig. 2 a, between pixel electrode layer 223 and common electrode layer 225, only has the 3rd passivation layer 224 of insulating effect, the dielectric layer of the memory capacitance that this passivation layer is formed as pixel electrode layer 223 and common electrode layer 225.Owing to only having one deck dielectric material between pixel electrode layer 223 and common electrode layer 225, thus the spacing between pixel electrode layer 223 and common electrode layer 225 is reduced.According to capacitance equation: C=ε S/d, when polar plate spacing d reduces, capacitance C can increase, thus effectively increases the memory capacitance of pixel cell.
In addition, from Fig. 2 a and Fig. 2 b, touching signals layer and pixel electrode layer have overlapping region, also can form a memory capacitance between touching signals layer 221 and pixel electrode layer 223, and the second passivation layer 222 is as the dielectric layer between touching signals layer 221 and pixel electrode layer 223.Because touching signals layer 221 is communicated with the common electrode layer 225 of top layer with the via hole of the 3rd passivation layer 224 by through second passivation layer 222, pixel electrode layer 223, the electric capacity that electric capacity, touching signals layer 221 and pixel electrode layer 223 that pixel electrode layer 223 and common electrode layer 225 are formed are formed is parallel relationship, and the memory capacitance of the formation so between touching signals layer 221 and pixel electrode layer 223 also can increase the storage capacitance value of single pixel.
Therefore the insulation course (i.e. passivation layer) between original pixel electrode layer 223 and common electrode layer 225 is not only two-layerly reduced to one deck by original by the present invention, adds somewhat to the storage capacitance value of pixel.Meanwhile, also add the memory capacitance formed between touching signals layer 221 and pixel electrode layer 223.Compared with traditional LTPS pixel embedded touch control panel, in the present invention array base palte pixel in storage capacitance value had and increased considerably.
Be as shown in Figure 2 a and 2 b pixel electrode layer 223 as the first electrode layer, common electrode layer 225 is as the display panels cross section structure schematic diagram of the second electrode lay.But the position of common electrode layer and pixel electrode layer also can exchange, and namely common electrode layer is as the first electrode layer, and pixel electrode layer is as the second electrode lay.In this case, touch control electrode is connected with common electrode layer by the via hole of through second passivation layer and (should be noted, common electrode layer is now under pixel electrode layer, and pixel electrode layer is communicated with signals layer with the via hole of flatness layer by through 3rd passivation layer, common electrode layer, the second passivation layer, touching signals layer, the first passivation layer).
When common electrode layer as the first electrode layer, pixel electrode layer as the second electrode lay, also only had the 3rd passivation layer of insulating effect between common electrode layer and pixel electrode layer, effectively can increase the memory capacitance of pixel cell.In addition, touching signals layer and pixel electrode layer have overlapping region, also can form a memory capacitance between touching signals layer and pixel electrode layer, and the second passivation layer and the 3rd passivation layer are as the dielectric layer between touching signals layer and pixel electrode layer.Because the via hole of touching signals layer by through second passivation layer is communicated with common electrode layer, the electric capacity that electric capacity, touching signals layer and pixel electrode layer that pixel electrode layer and common electrode layer are formed are formed is parallel relationship, and the memory capacitance of the formation so between touching signals layer and pixel electrode layer also can increase the storage capacitance value of single pixel.
In one embodiment of the invention, the substrate in this array base palte comprises: light shield layer 212, is formed on glass substrate 211; First insulation course 213, is arranged on light shield layer 212 and exposed glass substrate 211; Polysilicon active layers 214, is arranged on the first insulation course 213; Second insulation course 215, is arranged on polysilicon active layers 214 and the first exposed insulation course 213; Grid layer 217, is arranged on the second insulation course 215, in order to form the grid of thin film transistor (TFT); 3rd insulation course 218, is arranged on grid layer 217 and the second exposed insulation course 215; Signals layer 216, is arranged on the 3rd insulation course 218, in order to the source electrode that forms corresponding thin film transistor (TFT) and drain electrode and the signal wire that is communicated with source-drain electrode; Flatness layer 219, is arranged on signals layer 216 and the 3rd exposed insulation course 218.Wherein, when pixel electrode layer 223 is as the first electrode layer, when common electrode layer 225 is as the second electrode lay, the source electrode of thin film transistor (TFT) is communicated with pixel electrode layer 223 with the via hole of the second passivation layer 222 by through flatness layer 219, first passivation layer 220, touching signals layer 221.When common electrode layer is as the first electrode layer, when pixel electrode layer is as the second electrode lay, the source electrode of thin film transistor (TFT) is communicated with the second electrode lay (i.e. pixel electrode layer) with the via hole of the 3rd passivation layer 224 by through flatness layer 219, first passivation layer 220, touching signals layer 221, second passivation layer 222, first electrode layer (i.e. common electrode layer).
In one embodiment of the invention, the electrode in the first electrode layer is plane-shape electrode, in order to increase electrode area, improves driving voltage; Electrode in the second electrode lay is strip shaped electric poles, realizes horizontally rotating of liquid crystal molecule, to increase the display view angle of display panel in order to coordinate with the electrode in the first electrode layer of planar.
According to another aspect of the present invention, additionally providing a kind of method for making above array base palte, being described for Fig. 2 a, this method for making comprises following several steps.
First, substrate forms light shield layer, the light sent in order to avoid backlight is irradiated to the thin film transistor (TFT) formed thereafter.
Then, light shield layer and exposed substrate form the first insulation course.Concrete, deposit SiNx/SOx in this step and form silicon oxynitride conjunction layer, to play an insulating effect.
Then, the first insulation course forms polysilicon active layers.This polysilicon active layers is in order to form the conducting channel in thin film transistor (TFT).
Then, polysilicon active layers and the first exposed insulation course form the second insulation course, form silicon oxynitride by deposition SiNx/SOx and close layer, to play insulating effect.
Then, the grid layer corresponding with polysilicon active layers is formed over the second dielectric, to form the grid of thin film transistor (TFT).
Then, grid layer and the second exposed insulation course form the 3rd insulation course, form silicon oxynitride by deposition SiNx/SOx and close layer, to play insulating effect.
Then, the 3rd insulation course forms signals layer.The source-drain electrode that signals layer herein comprises thin film transistor (TFT) and the signal wire be connected with source-drain electrode.
Then, signals layer and the 3rd exposed insulation course form flatness layer, in order to shield to each tunic under it.
Then, flatness layer forms the first passivation layer, in order to play protection and insulating effect to each tunic under it.
Then, the first passivation layer forms touching signals layer, in order to form touching signals.
Then, touching signals layer and the first exposed passivation layer form the second passivation layer, in order to play protection and insulating effect to each tunic under it.
Then, the second passivation layer forms the first electrode layer.
Then, the first electrode layer and the second exposed passivation layer form the 3rd passivation layer, in order to play protection and insulating effect to each tunic under it.
Finally, the 3rd passivation layer forms the second electrode lay.
Wherein, when pixel electrode layer 223 is as the first electrode layer, when common electrode layer 225 is as the second electrode lay, the source electrode of thin film transistor (TFT) is communicated with pixel electrode layer 223 with the via hole of the second passivation layer 222 by through flatness layer 219, first passivation layer 220, touching signals layer 221; Touching signals layer is communicated with described common electrode layer by the via hole of through second passivation layer with the 3rd passivation layer.When common electrode layer is as the first electrode layer, when pixel electrode layer is as the second electrode lay, the source electrode of thin film transistor (TFT) is communicated with the second electrode lay (i.e. pixel electrode layer) with the via hole of the 3rd passivation layer by through flatness layer, the first passivation layer, touching signals layer, the second passivation layer, the first electrode layer (i.e. common electrode layer); Touching signals layer is communicated with common electrode layer by the via hole of through second passivation layer.
According to a further aspect in the invention, a kind of display panels adopting above-described array base palte is additionally provided.As shown in figures 2 a and 2b, this display panels also comprises the color membrane substrates corresponding with array base palte, this color membrane substrates is included in the black-matrix layer 227 that substrate 226 is formed, the red resistance layer 228 that black-matrix layer 227 and exposed substrate 226 are formed and green resistance layer 229, the flatness layer 230 that red resistance layer 228 and green resistance layer 229 are formed, the main chock insulator matter 231 that flatness layer 230 is formed and auxiliary chock insulator matter 232, also comprises the liquid crystal molecule 230 between array base palte and color membrane substrates.
Although embodiment disclosed in this invention is as above, the embodiment that described content just adopts for the ease of understanding the present invention, and be not used to limit the present invention.Technician in any the technical field of the invention; under the prerequisite not departing from spirit and scope disclosed in this invention; any amendment and change can be done what implement in form and in details; but scope of patent protection of the present invention, the scope that still must define with appending claims is as the criterion.
Claims (10)
1. an array base palte, comprising:
Substrate;
First passivation layer, it is arranged in described substrate;
Touching signals layer, it is arranged on described first passivation layer;
Second passivation layer, it is arranged on described touching signals layer and the first exposed passivation layer;
First electrode layer, it is arranged on described second passivation layer;
3rd passivation layer, it is arranged on described first electrode layer and the second exposed passivation layer;
The second electrode lay, it is arranged on described 3rd passivation layer.
2. array base palte according to claim 1, is characterized in that, described first electrode layer is pixel electrode layer, and described the second electrode lay is common electrode layer.
3. array base palte according to claim 1, is characterized in that, described first electrode layer is common electrode layer, and described the second electrode lay is pixel electrode layer.
4. array base palte according to claim 2, it is characterized in that, described touching signals layer and described pixel electrode layer have overlapping region, and it is communicated with described common electrode layer with the via hole of described 3rd passivation layer by through described second passivation layer, described first electrode layer.
5. array base palte according to claim 3, is characterized in that, described touching signals layer and described pixel electrode layer have overlapping region, and it is communicated with described common electrode layer by the via hole of through described second passivation layer.
6. the array base palte according to claim 4 or 5, is characterized in that, the electrode in described first electrode layer is plane-shape electrode, and the electrode in described the second electrode lay is strip shaped electric poles.
7. array base palte according to claim 2, is characterized in that, described substrate comprises:
Light shield layer, it is arranged on substrate;
First insulation course, it is arranged on described light shield layer and exposed substrate;
Polysilicon active layers, it is arranged on described first insulation course;
Second insulation course, it is arranged on described polysilicon active layers and the first exposed insulation course;
Grid layer, it is arranged on described second insulation course, in order to form the grid of thin film transistor (TFT);
3rd insulation course, it is arranged on described grid layer and the second exposed insulation course;
Signals layer, it is arranged on described 3rd insulation course, in order to the source electrode that forms thin film transistor (TFT) and drain electrode and with described source electrode and the signal wire be connected that drains;
Flatness layer, it is arranged on described signals layer and the 3rd exposed insulation course,
Wherein, described source electrode is communicated with described pixel electrode layer with the via hole of described second passivation layer by through described flatness layer, described first passivation layer, described touching signals layer.
8. array base palte according to claim 3, is characterized in that, described substrate comprises:
Light shield layer, it is arranged on substrate;
First insulation course, it is arranged on described light shield layer and exposed substrate;
Polysilicon active layers, it is arranged on described first insulation course;
Second insulation course, it is arranged on described polysilicon active layers and the first exposed insulation course;
Grid layer, it is arranged on described second insulation course, in order to form the grid of thin film transistor (TFT);
3rd insulation course, it is arranged on described grid layer and the second exposed insulation course;
Signals layer, it is arranged on described 3rd insulation course, in order to the source electrode that forms thin film transistor (TFT) and drain electrode and with described source electrode and the signal wire be connected that drains;
Flatness layer, it is arranged on described signals layer and the 3rd exposed insulation course,
Wherein, described source electrode is communicated with described pixel electrode layer with the via hole of described 3rd passivation layer by through described flatness layer, described first passivation layer, described touching signals layer, described second passivation layer, described first electrode layer.
9., for a method for making for array base palte according to any one of above claim 1-8, comprising:
Substrate forms light shield layer;
Described light shield layer and exposed substrate form the first insulation course;
Described first insulation course forms polysilicon active layers;
Described polysilicon active layers and the first exposed insulation course form the second insulation course;
Described second insulation course forms the grid layer corresponding with described polysilicon active layers, in order to form the grid of thin film transistor (TFT);
Described grid layer and the second exposed insulation course form the 3rd insulation course;
Described 3rd insulation course forms signals layer, in order to the source electrode that forms thin film transistor (TFT) and drain electrode and with described source electrode and the signal wire be connected that drains;
Described signals layer and the 3rd exposed insulation course form flatness layer;
Described flatness layer is formed the first passivation layer;
Described first passivation layer forms touching signals layer;
Described touching signals layer and the first exposed passivation layer form the second passivation layer;
Described second passivation layer forms the first electrode layer;
Described first electrode layer and the second exposed passivation layer form the 3rd passivation layer;
Described 3rd passivation layer forms the second electrode lay.
10. one kind adopts the display panels of array base palte according to any one of above claim 1-8.
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