CN105227259B - A kind of parallel production method of M sequence and device - Google Patents

Abstract

The invention provides a parallel generation method of M sequence, comprising: 1) obtaining the recursive formula of M sequence, determining the degree of parallelism w, and inputting initial M sequence bits; 2) synchronously reading w groups of known M sequence bits as input Data, according to the recursive formula, w-way recursive calculation is performed synchronously, and the previously unknown w M-sequence bits are obtained; among them, a set of known M-sequence bits corresponds to each power item on the right side of the recursive formula for one-way recursive calculation ; 3) Record the w M-sequence bits calculated in step 2) and output the w M-sequence bits synchronously, and then re-execute step 2) to calculate the next group of w M-sequence bits. The invention also provides a corresponding M-sequence parallel generation device. The invention has the advantages of high parallelism, simple feedback and simple initialization, and is suitable for both hardware and software realization.

Description

A method and device for generating M-sequence in parallel

technical field

The present invention relates to the field of communications, and more specifically, the present invention relates to a method and device for generating M sequences in parallel.

Background technique

The M sequence is the abbreviation of the longest linear shift register sequence, which is a pseudo-random sequence, pseudo-noise (PN) code or pseudo-random code. A sequence that can be predetermined and can be repeated is called a definite sequence; a sequence that can neither be predetermined nor repeated is called a random sequence; a sequence that cannot be predetermined but can be repeatedly generated is called a pseudo-random sequence. M sequence is widely used in wireless communication scrambling technology.

Scrambling technology is a commonly used technology in digital communication. Its purpose is to make the data transmitted in the channel random, so as to effectively avoid interference between data. The scrambling code sequence is usually composed of a pseudo-random sequence M sequence. With the development of mobile communication, the transmission rate is getting higher and higher, and the required scrambling code rate is also getting higher and higher, and the parallelization of scrambling codes is a good solution to increase the generation rate of scrambling codes.

Traditional parallel scrambling techniques mainly include look-up table method, matrix method, and sampling method. The table look-up method uses memory to implement parallelization. A scrambling code sequence with a period of 2 ^r -1 (r is the order of the generator polynomial). If the parallelism is W, then W*(2 ^r -1) is also the scrambling code sequence cycle. A memory with a bit width of W is used to store (2 ^r -1) columns, one column is extracted each time for scrambling, and the last column is cycled to the first column. The advantages of the look-up table method are fast speed and low complexity, but the storage overhead is very large, and it is suitable for occasions where the order of the generator polynomial is low. However, with the development of mobile communications, the generator polynomial of the scrambling code sequence has become more complex. For example, in the fourth-generation mobile communication LTE, the generator polynomial of the scrambling code sequence has reached order 31, and the look-up table method is no longer applicable.

The matrix method adopts the method of matrix state machine transfer, and obtains a multi-step transfer matrix through self-multiplication of multiple one-step transfer matrices, so that multiple state machines can be updated at one time, and the scrambling code is parallelized. The matrix method is suitable for hardware implementation based on register banks. However, although the matrix method can theoretically achieve any degree of parallelism, due to the need to realize the transition of the matrix state machine, the feedback between some register units in the matrix method scrambling code generation device is often relatively complicated, resulting in some The delay of the scrambling code bit is relatively long, and the delay of generating the entire scrambling code word is also relatively long due to the barrel effect, thereby reducing the overall operating frequency of the system. When the order of the scrambling code is relatively high (for example, the scrambling code of the 31-order LTE system) and the degree of parallelism is relatively high, the above defects are particularly obvious. In addition, the matrix method is not suitable for SIMD (Single Instruction Multiple Data) DSP implementation. When a new scrambling code is needed, special hardware is often required, and its versatility is weak.

The sampling method is to sample the scrambling code sequence, decompose the original scrambling code sequence into w sampling sequences (i.e. sub-sequences), design an independent generation unit for each sampling sequence, and output a scrambling code in the same clock cycle, so W sampling sequences can output w-bit scrambling codes in one clock cycle, thereby increasing the generation rate of scrambling codes. The advantage of the sampling method is that the degree of parallelism can be very high, and the scrambling code sequence generation speed can be very fast, but each independent generation unit requires independent resources, and the resource overhead is large, and each independent generation unit needs to calculate the initial value separately, which leads to The implementation complexity of the initial value is also relatively large.

Contents of the invention

The object of the present invention is to provide a method and device for parallel generation of M-sequences capable of overcoming the above-mentioned defects in the prior art.

According to one aspect of the present invention, a kind of M-sequence parallel generation method is provided, comprising the following steps:

1) Obtain the recursive formula of the M sequence, determine the degree of parallelism w, and input the initial M sequence bits;

2) Synchronously read w groups of known M-sequence bits as input data, and perform w-way recursive calculations synchronously according to the recursive formula, and obtain w previously unknown M-sequence bits; wherein, a group of known M-sequence bits corresponds to one Each power item on the right side of the recursive formula for recursive calculation;

3) Record the w M-sequence bits calculated in step 2) and output the w M-sequence bits synchronously, and then re-execute step 2) to calculate the next group of w M-sequence bits.

Wherein, in the step 1), the degree of parallelism w is not greater than the maximum degree of parallelism P=r-q, where r represents the order of the recurrence formula, and q represents the sequence number of the highest power item on the right side of the recurrence formula.

Wherein, in the step 1), the M sequence is the first M sequence in the LTE protocol or the second M sequence in the LTE protocol.

According to another aspect of the present invention, there is also provided an M-sequence parallel generation device for realizing the aforementioned M-sequence parallel generation method, assuming that the order of the recursive formula of the M-sequence is r, the highest power on the right side of the recursive formula The sequence number of the sub-item is q, then the M sequence parallel generating device includes r registers and w recursive operation units, wherein w is not greater than the maximum degree of parallelism P=r-q;

The r registers are respectively recorded as: 0~r-1 registers, each register includes an output terminal, an input terminal and a clock terminal, and the w recursive operation units are respectively recorded as: 0~w-1 recursive operation unit;

Among them, the output terminals of the i-i+q registers whose corresponding power term coefficients are not 0 and the output terminals of the i-th registers are connected to the input terminals of the i-th recursive operation unit at the same time, and the i-th recursive operation unit The push operation unit is used to complete the operation of the i-th recursive formula, and the output of the i-th recursive operation unit is connected to the input of the i+r-w register to form the first set of feedback connections, where i is 0 to an integer enumeration of w-1;

The output end of the j+wth register is connected to the input end of the jth register to form a second set of feedback connections, where j is an enumeration of integers from 0 to r-w-1.

Wherein, the output terminals of the 0~w-1 registers are used as the output terminals of the M sequence bits.

Wherein, the registers 0 to w-1 output w-bit M-sequence codes in parallel in each cycle.

According to yet another aspect of the present invention, another method M sequence parallel generation method is also provided, and the M sequence parallel generation method is realized based on a vector DSP with a SIMD structure, wherein the order of the recursive formula of the M sequence is r , the serial number of the highest power item on the right side of the recursive formula is q, then the vector length of the vector instruction in the DSP is w, and w is not greater than the maximum parallelism P=r-q, wherein, r, q, w are natural numbers;

The M-sequence parallel generation method comprises the following steps:

1) Read w groups of known M-sequence bits from the memory to at least two read-in data vector registers through multiple vector read instructions, wherein each of the read-in data vector registers receives w known M-sequences bit;

2) then carry out XOR operation to the data of at least two read-in data vector registers by vector XOR instruction to obtain w new M sequence bits, and write vector XOR operation result to output data vector register;

3) cache the data of the output data vector register to the corresponding location in the memory through the vector storage instruction, and then return to step 1) to start the calculation of the next group of M sequence bits.

Wherein, the M sequence is the first M sequence in the LTE protocol or the second M sequence in the LTE protocol.

Wherein, the step 3) further includes: outputting the w M sequence bits buffered in the memory while buffering the data of the output data vector register to a corresponding position in the memory through a vector storage instruction.

Compared with the prior art, the present invention has the following technical effects:

1. The M-sequence generation scheme of the present invention has high parallelism, simple feedback and simple initialization, and is suitable for both hardware implementation and DSP-based software implementation.

2. The M-sequence generation scheme of the present invention is particularly suitable for high-speed, high-parallel, high-order scrambling code generation.

Description of drawings

Fig. 1 is a schematic diagram of the M sequence parallel generation method;

Fig. 2 shows a schematic structural diagram of a device for generating scrambling code sequences in parallel according to an embodiment of the present invention;

Fig. 3 shows a schematic diagram of execution of program instructions of a device for parallel generation of scrambling code sequences provided by the device according to another embodiment of the present invention.

Detailed ways

In the prior art, the scrambling code sequences can be generated serially or in parallel. However, in the serial generation technology, usually based on a recursive formula, the known scrambling code bits are used to push the unknown new scrambling code bits, and the new scrambling code bits are output one by one. The inventor of this case conducted in-depth research on the recursive formula of the serial scrambling code, transferred the recursive formula to the parallel scrambling code sequence generation device, and then proposed a parallel scrambling code sequence generation scheme, compared with the traditional parallel scrambling code technology , the scheme has simple feedback and simple initialization, and is suitable for both hardware implementation and software implementation based on software DSP, especially suitable for high-speed, high-parallel, high-order scrambling code generation. For ease of understanding, the recursive formula for generating the scrambling code sequence is firstly introduced below.

As mentioned above, the scrambling code sequence is usually composed of a pseudo-random sequence M sequence. In mathematics, the primitive polynomial can be used to represent the pseudo-random sequence M sequence, and the primitive polynomial can be used to generate the M sequence recursively, so the polynomial is also called the generator polynomial of the M sequence. A general generator polynomial can be expressed as:

f(x)＝x ^r +c _r-1 x ^r-1 +...+c ₁ x+1

Where r is the order of the generator polynomial, c _i is the coefficient of each item in the generator polynomial, i=1,2,...,r-1; and c _i ∈{0,1}. This polynomial is capable of generating M-sequences with a period of 2 ^r -1. This generator polynomial corresponds to the recurrence formula:

x(n+r)=c _r-1 x(n+r-1)+...+c ₁ x(n+1)+x(n),n=0,1,2,...,N

where r is the order of the generator polynomial, c _i is the coefficient of each item in the generator polynomial, and c _i ∈ {0,1}, N is the length of the M sequence to be generated, and the "+ "Indicates the "modulo 2 addition" operation, and the "^" symbol, that is, the "exclusive or" symbol can also be used to represent the same operation.

The inventor conducted an in-depth analysis of the currently commonly used M-sequence generator polynomials, and found that in a general M-sequence generation system, only the first q coefficients of the generator polynomials have values, and the remaining coefficients are 0, namely c ₁ , c ₂ ,…, c _q has a value, and c _q+1 , c _q+2 ,…,c _r-1 are all 0. Using this property to achieve parallelization of the scrambling code sequence, the maximum degree of parallelism P=rq, where q is equal to the sequence number corresponding to the highest power item with a coefficient of 1.

The present invention will be further described below in conjunction with an embodiment of the present invention for realizing scrambling code generation in an LTE system.

According to one embodiment of the present invention, a parallel generation method of a scrambling code sequence is proposed, comprising the following steps:

Step 1: Obtain the recursive formula x(n+r)=c _q x(n+q)^...^c ₁ x(n+1)^x ₁ (n) of the M sequence, and determine the degree of parallelism w. Among them, the symbol "^" represents the "exclusive OR" operation (that is, the "modulo 2 addition" operation). In this step, r initial values of the scrambling code sequence are also generated, that is, an initialization sequence is generated.

In LTE, two M-sequence XOR operations are used to generate scrambling code sequences. First, the first M-sequence is used as an example to illustrate. The recursive formula of the first M-sequence in the LTE protocol is:

x(n+31)=x(n+3)^x(n), n=0,1,...,N

Analyzing the recursive formula, it can be seen that the order r of the first M sequence in the LTE protocol is equal to 31, the sequence number q of the highest power item is equal to 3, and the maximum degree of parallelism P is 28. Assuming that the degree of parallelism used in the actual system is w, then it is necessary to ensure that w is not greater than 28.

On the other hand, in this embodiment, the first M-sequence of LTE provides 31 initial values, but in the actual application of the LTE protocol, the required M-sequence starts from the 1600th M-sequence, so the first M-sequence in the sequence 1600 are useless, and it will be wasteful to output these 1600 values. In this embodiment, before the M-sequence is generated, 31 values starting from the 1600th are derived by iterative calculation using a recursive formula directly based on the 31 initial values. Then use the deduced 31 values as initial values to input hardware or software to generate M sequence, thus saving related resources for generating M sequence.

Step 2: Synchronously read w groups of known scrambling code bits (the scrambling code bits in this paper actually refer to the bits of the M sequence, that is, the M sequence code) as input data, and perform w-way recursive calculation synchronously according to the recursive formula, and obtain Unknown w scrambling code bits. Wherein, each group of known scrambling code bits corresponds to an unknown scrambling code bit. In the present invention, the data bits in the M sequence used to generate the scrambling code are referred to as scrambling code bits. The following example illustrates.

When the parallelism w used by the first M sequence in the LTE protocol is 16, the corresponding multi-path recursive formula is as follows:

Referring to the above multi-path recursive formula, each set of input data is two scrambling code bits with a sequence number difference of 3, for example: x(n+3), x(n) is the first known scrambling code bit as the input data , x(n+4), x(n+1) are the 2nd group of known scrambling code bits as input data, x(n+18), x(n+15) are the 16th group of known scrambling bits as input data Knowing the scrambling code bits, each round of recursive calculation needs to read 16 sets of scrambling code bits synchronously as input data. After a round of parallelized recursive calculation is completed, the data from x(n+31) to x(n+46) will be obtained 16 new scrambling bits.

When the parallelism w used by the first M sequence in the LTE protocol is 28, the multi-path recursive formula is as follows:

The scheme of performing parallelized recursive calculation according to the multi-path recursive formula is similar to that when w=16, and will not be repeated here.

It can be seen that corresponding to the general system, the generalized multi-path recursive formula can be obtained:

Where r is the coefficient of the generator polynomial, c _q is the coefficient of the largest power item with a coefficient of 1 in the generator polynomial, c _q is always equal to 1, w is the actual parallelism, the maximum parallelism P=rq, w is not greater than P, so w+q is not greater than r.

The scheme of performing parallelized recursive calculation according to the generalized multi-path recursive formula is similar to that when w=16, and will not be repeated here.

Step 3: Record the calculated w scrambling code bits and output the w scrambling code bits synchronously, and re-execute step 2 to read the input data of the next round of recursive calculation.

By continuously performing the above steps 2 and 3, the scrambling codes can be continuously generated and output in parallel.

In the parallel generation method of the above-mentioned scrambling code sequence, for each round of operation, the recursive formula of the w-way operation is completely consistent, so the w-way operation can use the same connection mode and computing unit when the hardware is implemented, so that w-bit new The delay of the scrambling codes is the same, which can avoid limiting the hardware frequency due to the barrel effect, and helps to further increase the generation rate of parallel scrambling codes. On the other hand, parallel data will undergo the same operation and storage, so the parallel generation method of the scrambling code sequence is also easy to use vector instructions for programming, so it is suitable for implementation in vector DSP with SIMD structure.

Further, FIG. 2 shows a schematic structural diagram of a device for parallel generation of scrambling code sequences according to an embodiment of the present invention. The embodiment is a device for parallel generation of scrambling code sequences for the first M-sequence in an LTE system. In this embodiment, the device for generating scrambling code sequences in parallel includes 31 registers, which are coded as registers 0 to 30 from top to bottom in FIG. 2 . Among them, the D terminal of each register is the input terminal, the Q terminal is the output terminal, and the CLK terminal is the clock input port. The whole device conforms to the sequential logic. Whenever a clock cycle ends, the data at the Q terminal of the register will be updated to the data at the D terminal. The XOR function is performed by a combinational logic unit. Since the recursive formula of the first M-sequence in the LTE system contains only one XOR operation, it can be considered that the recursive operation takes effect immediately.

With reference to Fig. 2, the hardware design based on this register and XOR circuit is described as follows: at first, for the structure of hardware design, because the order number of M sequence is r (r=31) in the present embodiment, so need in hardware design The length of the register is also r (ie 31), and the register number is set to 0~r-1 (ie 0~30). Secondly, for the wiring of the hardware design, since the sequence number of the highest power item on the right side of the recursive formula is q (q=3 in this embodiment), it is necessary to separate the output terminals of the registers whose numbers differ by q (that is, 3). The number of registers required for XOR depends on the degree of parallelism designed. Again, for the output of hardware design, since the designed hardware parallelism is w (w=16), registers 0～w-1 (ie 0～15) and registers q～w+q-1 (ie 3～ 18) is XORed, and after one clock cycle, w (that is, 16) scrambling code bits can be output at the same time. Finally, for the feedback of hardware design, since the designed hardware parallelism is w (w=16), it is necessary to assign the values of registers w～r-1 (ie 16～30) to registers 0～r-w-1 (ie 0 to 14), and at the same time, it is necessary to feed back the output w (ie 16) bits to registers numbered r-w ~ r-1 (ie 15 to 30). In such a hardware design, it can be guaranteed that one clock cycle will generate w operation results and w channels of feedback, so that scrambling code sequences can be generated in parallel. The hardware or software implementation of the second M-sequence is consistent with the principle of the first M-sequence, and will not be repeated here.

Based on the embodiment in FIG. 2 , a generalized parallel scrambling hardware implementation solution based on a recursive formula can be further obtained.

Suppose the generalized multi-path recursion formula is as follows:

Where r is the coefficient of the generator polynomial, c _q is the coefficient of the largest power item with a coefficient of 1 in the generator polynomial, c _q is always equal to 1, w is the actual parallelism, the maximum parallelism P=rq, w is not greater than P, so w+q is not greater than r.

Based on the above generalized multi-path recursive formula, combined with reference to the embodiment of FIG. 2 , the corresponding generalized parallel generating device for scrambling code sequences includes r registers and w recursive operation units. The r registers are respectively recorded as registers 0 to r-1, and each register includes a Q terminal (output terminal), a D terminal (input terminal) and a CLK terminal (clock terminal). The w recursive operation units are respectively recorded as: 0~w-1 recursive operation units, which are used to complete the modulo two addition operation.

Among them, the Q terminal of the i-i+q register whose corresponding coefficient of the power term is not 0 and the Q terminal of the i-th register are connected to the input terminal of the i-th recursive operation unit at the same time, and i is 0 to The integer enumeration of w-1, q is the serial number corresponding to the highest power item whose coefficient is not 0 in the M sequence recurrence formula. The i-th recursive operation unit is used to complete the operation of the i-th recursive formula, and the output terminal of the i-th recursive operation unit is connected to the D terminal of the i+r-w-th register to form a first group of feedback connections. On the other hand, the Q terminal of the j+wth register is connected to the D terminal of the jth register to form a second group of feedback connections. where j is an enumeration of integers from 0 to r-w-1.

In addition, in this embodiment, the Q terminals of registers 0 to w-1 are used as output terminals of scrambling code bits, and w-bit scrambling codes are output in parallel in each cycle. In another embodiment, the output terminals of the 0~w-1 recursive operation units can also be used as the output terminals of the scrambling code bits.

In the above embodiments, since the delays for generating w-bit new scrambling codes are the same, it is possible to avoid limiting the hardware frequency due to the barrel effect, which helps to further increase the generation rate of parallel scrambling codes.

According to another embodiment of the present invention, a vector DSP using a SIMD structure is provided to realize parallel scrambling sequence generation of the first M sequence in an LTE system based on a program. FIG. 3 shows a schematic diagram of program instruction execution of the device. For parallelized software programming, it is necessary for the software environment to support the vector memory access mechanism and the vector operation mechanism. Taking this embodiment as an example, if the degree of parallelism w=16, the software environment should at least support vector memory access and vector memory with a vector width of 16. Computation, that is, a software instruction can read and write 16 data from the memory at the same time, and can also allow 16 data in two vector registers to participate in the operation at the same time. The vector DSP with SIMD structure meets the above requirements. Using software programming, firstly, through two vector read instructions, read w (that is, 16) data from the memory to the vector registers vr1 and vr2 each time, and the numbers of the data read into vr1 and vr2 are 0~ w-1 (ie 0-15) and q-w+q-1 (ie 3-18). Secondly, through a vector XOR operation instruction, the w (namely 16) data in the two vector registers are respectively subjected to XOR operation to obtain a partial scrambling code sequence with a length of w (namely 16), and the obtained partial scrambling sequence The code sequence is stored in another vector register vr3. Finally, a vector storage instruction is used to store part of the scrambling code sequence in vr3 to the corresponding location of the memory. Using the method to perform multiple operations can realize the generation of scrambling code sequences in parallel.

The hardware or software implementation of the second M-sequence in the LTE system is consistent with the principle of the first M-sequence, and will not be repeated here.

Finally, it should be noted that the above embodiments are only used to describe the technical solutions of the present invention rather than limit the technical methods of the present invention. The present invention can be extended to other modifications, changes, applications and embodiments in application, and therefore it is considered that all such Modifications, changes, applications, and embodiments are all within the spirit and teaching scope of the present invention.

Claims (9)

1. a kind of parallel production method of M sequence, which is characterized in that include the following steps：

1) recurrence formula x (n+r)=c of M sequence is obtained_qx(n+q)^…^c₁x(n+1)^x₁(n), degree of parallelism w is determined, input is just Gather as initial known M sequence position the M sequence position of beginning；Wherein, r is generator polynomial exponent number, c_qIt is in generator polynomial The coefficient of each single item, and c_q∈ { 0,1 }, N are the length for the M sequence to be generated, " ^ " table wherein between generator polynomial items Show that " mould 2 adds " operation, q are equal to the corresponding serial number of highest power item that coefficient is 1；

2) the synchronous known M sequence position of w groups of reading is synchronized as input data according to recurrence formula in gathering from known M sequence position The roads w recurrence calculation is carried out, original w unknown M sequence position is obtained；Wherein, M sequence position known to one group corresponds to recursion meter all the way Each power item in the recurrence formula calculated on the right side of equal sign；

3) known M sequence position set is added in step 2) institute's calculated w M sequence position, and this w M sequence bit synchronization is defeated Go out, then re-executes step 2) to calculate next group of w unknown M sequence positions.

2. the parallel production method of M sequence according to claim 1, which is characterized in that in the step 1), the degree of parallelism W is not more than maximum parallelism degree P=r-q, and wherein r indicates that the exponent number of the recurrence formula, q indicate the right side highest power of recurrence formula The serial number of secondary item.

3. the parallel production method of M sequence according to claim 2, which is characterized in that in the step 1), the M sequence For the second M sequence in the first M sequence or LTE protocol in LTE protocol.

4. a kind of parallel generation device of M sequence for realizing the parallel production method of M sequence described in claim 1, wherein M sequences The exponent number of the recurrence formula of row is r, the serial number q of the highest power item in the recurrence formula on the right side of equal sign, then the M Sequential parallel generation device includes being denoted as r register of 0~r-1 registers respectively, and remember 0~w-1 recursion respectively W recursive operation unit of arithmetic element, wherein w is not more than maximum parallelism degree P=r-q, and r, q, w are natural number；

Wherein, each register includes output end, input terminal and clock end；Corresponding power term coefficient is not 0 i-th~i+ The output end of the output end of q registers and No. i-th register is linked into the input terminal of No. i-th recursive operation unit simultaneously, and i-th Number recursive operation unit is used to complete the operation of the i-th road recurrence formula, and the output end of No. i-th recursive operation unit connect i-th+ The input terminal of r-w registers, forms first group of feedback line, and wherein i is that 0 to w-1 integer is enumerated；

The input terminal of the output end connection jth register of jth+w registers, forms second group of feedback line, wherein j is 0 Integer to r-w-1 is enumerated.

5. the parallel generation device of M sequence according to claim 4, which is characterized in that 0~w-1 registers it is defeated Output end of the outlet as M sequence position.

6. the parallel generation device of M sequence according to claim 5, which is characterized in that 0~w-1 registers are each Parallel output w M sequence code of period.

7. a kind of parallel production method of M sequence, the parallel production method of M sequence is real based on the vectorial DSP with SIMD architecture It is existing；

Wherein, recurrence formula x (n+r)=c of M sequence_qx(n+q)^…^c₁x(n+1)^x₁(n) exponent number is r, and the recursion is public The serial number q of highest power item in formula on the right side of equal sign, then the vector length of vector instruction is w in DSP, and w is simultaneously no more than maximum Row degree P=r-q, wherein r, q, w are natural number；

Wherein, r is generator polynomial exponent number, c_qIt is the coefficient of each single item in generator polynomial, and c_q∈ { 0,1 }, N are to be given birth to At M sequence length, " ^ " expression wherein between generator polynomial items " mould 2 plus " operation, q is equal to the highest power that coefficient is 1 The corresponding serial number of secondary item；

The parallel production method of M sequence includes the following steps：

1) by repeatedly vector read instruction read from memory respectively M sequence position known to w groups at least two reading data to Measure register, wherein each reading data vector register receives w known M sequence positions；

2) and then the data in data vector register are read in by the instruction of vectorial xor operation to described at least two to carry out Xor operation obtains w new M sequence positions, and output data vector registor is written in vectorial xor operation result；

3) by vectorial store instruction then the corresponding position in the data buffer storage to memory of output data vector registor is returned Step 1) is returned, the calculating of next group of M sequence position is proceeded by.

8. the parallel production method of M sequence according to claim 7, which is characterized in that the M sequence is in LTE protocol The second M sequence in first M sequence or LTE protocol.

9. the parallel production method of M sequence according to claim 7, which is characterized in that the step 3) further includes：Passing through While vectorial store instruction is by corresponding position in the data buffer storage to memory of output data vector registor, by institute in memory W M sequence position of caching exports.