CN105226183B - A kind of resistance-variable storing device and the method for improving its positive negative sense current difference - Google Patents
A kind of resistance-variable storing device and the method for improving its positive negative sense current difference Download PDFInfo
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Abstract
本发明涉及一种阻变存储器及提高其正负向电流差的方法，所示阻变存储器包括：一衬底；一第一端电极，设置于所述衬底上，并与衬底形成良好电接触；一阻变介质层，设置于所述第一端电极的左侧或上方；一第二端电极，若所述阻变介质层设置于所述第一端电极的左侧，则所述第二端电极设置于所述阻变介质层的左侧；若所述阻变介质层设置于所述第一端电极的上方，则所述第二端电极设置于所述阻变介质层的上方。其中，所述的阻变介质层可为双层阻变介质，所述的双层阻变介质是由第一阻变层与第二阻变层组成的叠层结构。本发明采用等离子修饰，在介质中或介质表面处引入缺陷，从而有效抑制负向电流值并极大提高正负向电流差值。
The invention relates to a resistive variable memory and a method for increasing its positive and negative current difference. The resistive variable memory includes: a substrate; a first terminal electrode arranged on the substrate and formed well with the substrate Electrical contact; a resistive variable medium layer arranged on the left side or above the first terminal electrode; a second terminal electrode, if the resistive variable medium layer is arranged on the left side of the first terminal electrode, the The second terminal electrode is set on the left side of the resistive medium layer; if the resistive medium layer is set above the first terminal electrode, the second terminal electrode is set on the resistive medium layer above. Wherein, the resistive switchable medium layer may be a double-layer resistive switchable medium, and the double-layer resistive switchable medium is a laminated structure composed of a first resistive switchable layer and a second resistive switchable layer. The invention adopts plasma modification to introduce defects in the medium or on the surface of the medium, thereby effectively suppressing the negative current value and greatly increasing the positive and negative current difference.
Description
技术领域technical field
本发明属于半导体存储器技术领域，特别涉及一种阻变存储器及提高其正负向电流差的方法。The invention belongs to the technical field of semiconductor memory, in particular to a resistive variable memory and a method for increasing its positive and negative current difference.
背景技术Background technique
阻变存储器（RRAM）通常由简单三明治结构（电极/存储介质/电极）构成，通过施加电信号，改变存储材料的电阻状态，从而实现双稳态的存储功能。随着技术发展，存储器趋向于采用十字交叉的三维集成，以便获取更高的存储密度。然而，该构架中的串扰电流会导致存储信息的误读。因此，提高阻变存储器正负向电流差（或整流特性）并获取电流-电压特性的非线性，能够较好抑制流经低阻存储单元的串扰电流，从而提高数据读取的可靠性。Resistive RAM (RRAM) is usually composed of a simple sandwich structure (electrode/storage medium/electrode). By applying an electrical signal, the resistance state of the storage material is changed to achieve a bistable storage function. With the development of technology, memory tends to adopt criss-cross three-dimensional integration in order to obtain higher storage density. However, crosstalk currents in this architecture can lead to misreading of stored information. Therefore, improving the positive and negative current difference (or rectification characteristics) of the RRAM and obtaining the nonlinearity of the current-voltage characteristics can better suppress the crosstalk current flowing through the low-resistance memory cells, thereby improving the reliability of data reading.
发明内容Contents of the invention
有鉴于此，本发明的目的是提供一种阻变存储器及提高其正负向电流差的方法，该存储器由两个端电极和夹于两电极间的阻变介质组成，并采用等离子修饰引入缺陷，从而有效抑制负向电流值并极大提高正负向电流差值。In view of this, the object of the present invention is to provide a resistive variable memory and a method for increasing its positive and negative current difference. defects, thereby effectively suppressing the negative current value and greatly increasing the difference between positive and negative currents.
本发明采用以下方案实现：一种阻变存储器，包括：一衬底；一第一端电极，设置于所述衬底上，并与衬底形成良好电接触；一阻变介质层，设置于所述第一端电极的左侧或上方；一第二端电极，若所述阻变介质层设置于所述第一端电极的左侧，则所述第二端电极设置于所述阻变介质层的左侧；若所述阻变介质层设置于所述第一端电极的上方，则所述第二端电极设置于所述阻变介质层的上方；其中，所述阻变介质层的表面经过等离子处理。The present invention is realized by adopting the following scheme: a resistive variable memory, comprising: a substrate; a first terminal electrode disposed on the substrate and forming a good electrical contact with the substrate; a resistive variable medium layer disposed on the substrate On the left side or above the first terminal electrode; a second terminal electrode, if the resistive variable medium layer is arranged on the left side of the first terminal electrode, the second terminal electrode is arranged on the resistive variable medium layer On the left side of the dielectric layer; if the resistive dielectric layer is disposed above the first terminal electrode, the second terminal electrode is disposed above the resistive dielectric layer; wherein, the resistive dielectric layer The surface is plasma treated.
进一步地，所述衬底为聚合物、金属、半导体或绝缘体；所述端电极为导电金属、金属合金、导电金属化合物或半导体；所述的阻变介质层为半导体或绝缘体。Further, the substrate is polymer, metal, semiconductor or insulator; the terminal electrode is conductive metal, metal alloy, conductive metal compound or semiconductor; the resistive medium layer is semiconductor or insulator.
进一步地，所述聚合物包括塑料、橡胶、PET、PEN、PEEK、PC、PES、PAR、PCO、PMMA以及PI；所述导电金属包括Ta、Cu、Pt、Ti、Au、W、Ni、Al以及Ag；所述金属合金包括Pt/Ti、Ti/Ta、Cu/Ti、Cu/Au、Ti/W以及Al/Zr；所述导电金属化合物包括TiN、TiW、TaN以及WSi；所述半导体包括Si、ZrOx、Ge、ZnO、ITO、GZO、AZO、TiOx、TaOx、HfOx、GeOx以及FTO；所述绝缘体包括AlOx、MgO、ZrOx、HfOx、GeOx以及SiOx。Further, the polymer includes plastic, rubber, PET, PEN, PEEK, PC, PES, PAR, PCO, PMMA and PI; the conductive metal includes Ta, Cu, Pt, Ti, Au, W, Ni, Al and Ag; the metal alloys include Pt/Ti, Ti/Ta, Cu/Ti, Cu/Au, Ti/W, and Al/Zr; the conductive metal compounds include TiN, TiW, TaN, and WSi; the semiconductors include Si, ZrO x , Ge, ZnO, ITO, GZO, AZO, TiO x , TaO x , HfO x , GeO x and FTO; the insulators include AlO x , MgO, ZrO x , HfO x , GeO x and SiO x .
本发明可实现一种提高上述阻变存储器正负向电流差的方法，采用等离子处理所述阻变介质层的表面，包括以下步骤：The present invention can realize a method for improving the positive and negative current difference of the above-mentioned resistive variable memory, and adopts plasma to treat the surface of the resistive variable medium layer, including the following steps:
步骤S11：在衬底上通过磁控溅射、PECVD、MOCVD、 ALD、MBE、PLD或蒸发法制作第一端电极；Step S11: making a first terminal electrode on the substrate by magnetron sputtering, PECVD, MOCVD, ALD, MBE, PLD or evaporation;
步骤S12：在所述第一端电极的左侧或上方通过磁控溅射、PECVD、MOCVD、 ALD、MBE、PLD、溶胶凝胶法或蒸发法制作阻变介质层，并与所述第一端电极形成良好电接触；Step S12: Fabricate a resistive medium layer on the left side or above the first terminal electrode by magnetron sputtering, PECVD, MOCVD, ALD, MBE, PLD, sol-gel method or evaporation method, and combine with the first terminal electrode The terminal electrodes form good electrical contact;
步骤S13：通过等离子处理所述阻变介质层的表面；Step S13: treating the surface of the resistive medium layer by plasma;
步骤S14：在所述阻变介质层的左侧或上方通过磁控溅射、PECVD、MOCVD、 ALD、MBE、PLD或蒸发法制作第二端电极，并形成良好电接触；Step S14: making a second terminal electrode on the left side or above the resistive medium layer by magnetron sputtering, PECVD, MOCVD, ALD, MBE, PLD or evaporation method, and forming a good electrical contact;
若所述步骤S12中，在所述第一端电极的左侧制作阻变介质层，则所述步骤S14中，在所述阻变介质层的左侧制作第二端电极；若所述步骤S12中，在所述第一端电极的上方制作阻变介质层，则所述步骤S14中，在所述阻变介质层的上方制作第二端电极。If in the step S12, a resistive variable medium layer is formed on the left side of the first terminal electrode, then in the step S14, a second terminal electrode is formed on the left side of the resistive variable medium layer; if the step In S12, a resistive variable medium layer is formed above the first terminal electrode, and in the step S14, a second terminal electrode is formed above the resistive variable medium layer.
进一步地，所述步骤S13中进行等离子处理采用的等离子源是Ar、N2、O2、CF4、SF6、NH3、H2、CHF3气体中的一种或几种。Further, the plasma source used for plasma treatment in step S13 is one or more of Ar, N 2 , O 2 , CF 4 , SF 6 , NH 3 , H 2 , CHF 3 gases.
本发明还可采用以下方案实现：一种阻变存储器，包括：一衬底；一第一端电极，设置于所述衬底上，并与所述衬底形成良好电接触；一双层阻变介质，设置于所述第一端电极的左侧或上方；一第二端电极，若所述双层阻变介质设置于所述第一端电极的左侧，则所述第二端电极设置于所述双层阻变介质的左侧；若所述双层阻变介质设置于所述第一端电极的上方，则所述第二端电极设置于所述双层阻变介质的上方；其中，所述的双层阻变介质是由第一阻变层与第二阻变层组成的叠层结构，其中一个阻变层的表面经过等离子处理。The present invention can also be realized by the following solutions: a resistive variable memory, comprising: a substrate; a first terminal electrode disposed on the substrate and forming a good electrical contact with the substrate; a double-layer resistive variable medium, arranged on the left side or above the first terminal electrode; a second terminal electrode, if the double-layer resistive variable medium is arranged on the left side of the first terminal electrode, the second terminal electrode It is arranged on the left side of the double-layer resistive medium; if the double-layer resistive medium is arranged above the first end electrode, then the second end electrode is arranged above the double-layer resistive medium ; Wherein, the double-layer resistive switchable medium is a laminated structure composed of a first resistive switchable layer and a second resistive switchable layer, wherein the surface of one resistive switchable layer is treated with plasma.
进一步地，所述衬底为聚合物、金属、半导体或绝缘体；所述端电极为导电金属、金属合金、导电金属化合物或半导体；所述的双层存储介质为半导体或绝缘体。Further, the substrate is polymer, metal, semiconductor or insulator; the terminal electrode is conductive metal, metal alloy, conductive metal compound or semiconductor; the double-layer storage medium is semiconductor or insulator.
进一步地，所述聚合物包括塑料、橡胶、PET、PEN、PEEK、PC、PES、PAR、PCO、PMMA以及PI；所述导电金属包括Ta、Cu、Pt、Ti、Au、W、Ni、Al以及Ag；所述金属合金包括Pt/Ti、Ti/Ta、Cu/Ti、Cu/Au、Ti/W以及Al/Zr；所述导电金属化合物包括TiN、TiW、TaN以及WSi；所述半导体包括Si、ZrOx、Ge、ZnO、ITO、GZO、AZO、TiOx、TaOx、HfOx、GeOx以及FTO；所述绝缘体包括AlOx、MgO、ZrOx、HfOx、GeOx以及SiOx。Further, the polymer includes plastic, rubber, PET, PEN, PEEK, PC, PES, PAR, PCO, PMMA and PI; the conductive metal includes Ta, Cu, Pt, Ti, Au, W, Ni, Al and Ag; the metal alloys include Pt/Ti, Ti/Ta, Cu/Ti, Cu/Au, Ti/W, and Al/Zr; the conductive metal compounds include TiN, TiW, TaN, and WSi; the semiconductors include Si, ZrO x , Ge, ZnO, ITO, GZO, AZO, TiO x , TaO x , HfO x , GeO x and FTO; the insulators include AlO x , MgO, ZrO x , HfO x , GeO x and SiO x .
本发明可实现一种提高上述阻变存储器正负向电流差的方法，采用等离子处理所述双层阻变介质的内部，包括以下步骤：The present invention can realize a method for improving the positive and negative current difference of the above-mentioned resistive variable memory, and adopts plasma to treat the inside of the double-layer resistive variable medium, including the following steps:
步骤S21：在衬底上通过磁控溅射、PECVD、MOCVD、 ALD、MBE、PLD或蒸发法制作第一端电极；Step S21: making a first terminal electrode on the substrate by magnetron sputtering, PECVD, MOCVD, ALD, MBE, PLD or evaporation;
步骤S22：在所述第一端电极的左侧或上方通过磁控溅射、PECVD、MOCVD、 ALD、MBE、PLD、溶胶凝胶法或蒸发法制作第二阻变层，并与所述第一端电极形成良好电接触；Step S22: Fabricate a second resistive layer on the left side or above the first terminal electrode by magnetron sputtering, PECVD, MOCVD, ALD, MBE, PLD, sol-gel method or evaporation method, and combine with the first terminal electrode The electrode at one end forms a good electrical contact;
步骤S23：通过等离子处理所述第二阻变层的表面；Step S23: treating the surface of the second resistive layer with plasma;
步骤S24：在所述等离子处理过第二阻变层的左侧或上方通过磁控溅射、PECVD、MOCVD、 ALD、MBE、PLD、溶胶凝胶法或蒸发法制作第一阻变层，并与所述第二阻变层形成良好电接触；Step S24: making the first resistive layer on the left side or above the plasma-treated second resistive layer by magnetron sputtering, PECVD, MOCVD, ALD, MBE, PLD, sol-gel method or evaporation method, and forming good electrical contact with the second resistive variable layer;
步骤S25：在所述第一阻变层的左侧或上方通过磁控溅射、PECVD、MOCVD、 ALD、MBE、PLD或蒸发法制作第二端电极，并形成良好电接触；Step S25: making a second terminal electrode on the left side or above the first resistive layer by magnetron sputtering, PECVD, MOCVD, ALD, MBE, PLD or evaporation method, and forming a good electrical contact;
若所述步骤S22中，在所述第一端电极的左侧制作第二阻变层，则所述步骤S24中，在所述第二阻变层的左侧制作第一阻变层；若所述步骤S22中，在所述第一端电极的上方制作第二阻变层，则所述步骤S24中，在所述第二阻变层的上方制作第一阻变层；If in the step S22, the second resistive switch layer is fabricated on the left side of the first terminal electrode, then in the step S24, the first resistive switch layer is fabricated on the left side of the second resistive switch layer; if In the step S22, a second resistive switch layer is fabricated above the first terminal electrode, and in the step S24, a first resistive switch layer is fabricated above the second resistive switch layer;
若所述步骤S24中，在所述第二阻变层的左侧制作第一阻变层，则所述步骤S25中，在所述第一阻变层的左侧制作第二端电极；若所述步骤S24中，在所述第二阻变层的上方制作第一阻变层，则所述步骤S25中，在所述第一阻变层的上方制作第二端电极。If in the step S24, the first resistive layer is fabricated on the left side of the second resistive layer, then in the step S25, a second terminal electrode is fabricated on the left side of the first resistive layer; if In the step S24, a first resistive switch layer is formed above the second resistive switch layer, and in the step S25, a second terminal electrode is formed above the first resistive switch layer.
进一步地，所述步骤S23中进行等离子处理采用的等离子源是Ar、N2、O2、CF4、SF6、NH3、H2、CHF3气体中的一种或几种。Further, the plasma source used for the plasma treatment in the step S23 is one or more of Ar, N 2 , O 2 , CF4, SF 6 , NH 3 , H 2 , CHF 3 gases.
与现有技术相比，本发明的有益效果是提供了一种提高阻变存储器正负向电流差的工艺方法，从而实现阻变存储器的内嵌整流功能，提高阻变存储器读写的可靠性。该方法采用等离子处理在阻变介质内部或表面引入缺陷，提高了正负向电流差，改善了整流特性，具有很强的实用性和广阔的应用前景。Compared with the prior art, the beneficial effect of the present invention is to provide a process method for improving the positive and negative current difference of the resistive variable memory, thereby realizing the built-in rectification function of the resistive variable memory, and improving the reliability of reading and writing of the resistive variable memory . The method uses plasma treatment to introduce defects inside or on the surface of the resistive medium, which increases the difference between positive and negative currents and rectification characteristics, and has strong practicability and broad application prospects.
附图说明Description of drawings
图1为本发明中阻变存储器的结构示意图。FIG. 1 is a schematic structural diagram of a resistive variable memory in the present invention.
图2为本发明中经等离子处理和未经等离子处理ZnO表面的XPS谱图。Fig. 2 is the XPS spectra of ZnO surfaces treated by plasma and not treated by plasma in the present invention.
图3为本发明中经不同参数Ar等离子处理的HfOx/ZnO阻变介质的电流-电压特性。Fig. 3 is the current-voltage characteristics of the HfO x /ZnO resistive medium treated with Ar plasma with different parameters in the present invention.
图4为本发明中经等离子处理和未经等离子处理Ti/ZnO纳米线/Ti阻变存储器的电流-电压特性。Fig. 4 shows the current-voltage characteristics of the Ti/ZnO nanowire/Ti resistive variable memory after plasma treatment and without plasma treatment in the present invention.
图示说明：1-第二端电极，2-阻变介质层，21-第一阻变层，22-第二阻变层，3-第一端电极，4-衬底。Illustration: 1 - second terminal electrode, 2 - resistive variable medium layer, 21 - first resistive variable layer, 22 - second resistive variable layer, 3 - first terminal electrode, 4 - substrate.
具体实施方式Detailed ways
下面结合附图及实施例对本发明做进一步说明。本发明提供优选实施例，只用于本发明做进一步的说明，不应该被认为仅限于在此阐述的实施例，也不能理解为对本发明保护范围的限制，该领域技术熟练人员根据上述发明内容对本发明做出的一些非本质的改进和调整，仍属于本发明的保护范围。下述优选实施例中所使用的实验方法如无特殊说明，均为常规方法；所用的材料、试剂等，如无特殊说明，均可从商业途径获得。在图示中，衬底、第一端电极、阻变存储介质、第二端电极等结构为理想化模型，不应该被认为严格规定其参数、几何尺寸。在此，参考图是本发明理想化实施例的示意图，本发明所示的实施例不应该被认为仅限于图中所示区域的特定形状，而是包括能够实现相同功能的其他形状。The present invention will be further described below in conjunction with the accompanying drawings and embodiments. The present invention provides preferred embodiments, which are only used for further description of the present invention, and should not be considered as being limited to the embodiments set forth herein, nor can they be interpreted as limiting the protection scope of the present invention. Some non-essential improvements and adjustments made to the present invention still belong to the protection scope of the present invention. Unless otherwise specified, the experimental methods used in the following preferred embodiments are conventional methods; the materials, reagents, etc. used, unless otherwise specified, can be obtained from commercial sources. In the diagram, the structures of the substrate, the first terminal electrode, the resistive storage medium, and the second terminal electrode are idealized models, and should not be regarded as strictly stipulating their parameters and geometric dimensions. Here, the referenced figures are schematic diagrams of idealized embodiments of the present invention, and the illustrated embodiments of the present invention should not be construed as limited to the particular shapes of the regions shown in the figures, but include other shapes that can perform the same function.
本实施例提供一种阻变存储器，如图1中（c）和（d）所示，包括一衬底4；一第一端电极3，设置于所述衬底4上，并与衬底4形成良好电接触；一阻变介质层2，设置于所述第一端电极3的左侧或上方；一第二端电极1，若所述阻变介质层2设置于所述第一端电极3的左侧，则所述第二端电极1设置于所述阻变介质层2的左侧；若所述阻变介质层2设置于所述第一端电极3的上方，则所述第二端电极1设置于所述阻变介质层2的上方，其中，所述阻变介质层2的表面经过等离子处理。This embodiment provides a resistive variable memory, as shown in (c) and (d) in FIG. 4 Form a good electrical contact; a resistive variable dielectric layer 2 is arranged on the left side or above the first terminal electrode 3; a second terminal electrode 1, if the resistive variable dielectric layer 2 is arranged on the first terminal On the left side of the electrode 3, the second terminal electrode 1 is arranged on the left side of the resistive variable medium layer 2; if the resistive variable medium layer 2 is arranged above the first terminal electrode 3, then the The second terminal electrode 1 is disposed above the resistive variable medium layer 2 , wherein the surface of the resistive variable medium layer 2 is treated with plasma.
在本实施例中，所述衬底4为聚合物、金属、半导体或绝缘体；所述端电极1和3为导电金属、金属合金、导电金属化合物或半导体；所述的阻变介质层2为半导体或绝缘体。In this embodiment, the substrate 4 is a polymer, metal, semiconductor or insulator; the terminal electrodes 1 and 3 are conductive metal, metal alloy, conductive metal compound or semiconductor; the resistive variable medium layer 2 is semiconductor or insulator.
在本实施例中，所述聚合物包括塑料、橡胶、PET、PEN、PEEK、PC、PES、PAR、PCO、PMMA以及PI；所述导电金属包括Ta、Cu、Pt、Ti、Au、W、Ni、Al以及Ag；所述金属合金包括Pt/Ti、Ti/Ta、Cu/Ti、Cu/Au、Ti/W以及Al/Zr；所述导电金属化合物包括TiN、TiW、TaN以及WSi；所述半导体包括Si、ZrOx、Ge、ZnO、ITO、GZO、AZO、TiOx、TaOx、HfOx、GeOx以及FTO；所述绝缘体包括AlOx、MgO、ZrOx、HfOx、GeOx以及SiOx。In this embodiment, the polymer includes plastic, rubber, PET, PEN, PEEK, PC, PES, PAR, PCO, PMMA, and PI; the conductive metal includes Ta, Cu, Pt, Ti, Au, W, Ni, Al, and Ag; the metal alloys include Pt/Ti, Ti/Ta, Cu/Ti, Cu/Au, Ti/W, and Al/Zr; the conductive metal compounds include TiN, TiW, TaN, and WSi; Said semiconductors include Si, ZrO x , Ge, ZnO, ITO, GZO, AZO, TiO x , TaO x , HfO x , GeO x and FTO; said insulators include AlO x , MgO, ZrO x , HfO x , GeO x and SiO x .
在本实施例中，一种上述提高阻变存储器正负向电流差的方法，采用等离子处理所述阻变介质层的表面，包括以下步骤：In this embodiment, a method for increasing the positive and negative current difference of the resistive variable memory, using plasma to treat the surface of the resistive variable medium layer, includes the following steps:
步骤S11：在衬底4上通过磁控溅射、PECVD、MOCVD、 ALD、MBE、PLD或蒸发法制作第一端电极3；Step S11: making the first terminal electrode 3 on the substrate 4 by magnetron sputtering, PECVD, MOCVD, ALD, MBE, PLD or evaporation;
步骤S12：在所述第一端电极3的左侧或上方通过磁控溅射、PECVD、MOCVD、 ALD、MBE、PLD、溶胶凝胶法或蒸发法制作阻变介质层2，并与所述第一端电极3形成良好电接触；Step S12: Fabricate a resistive medium layer 2 on the left side or above the first terminal electrode 3 by magnetron sputtering, PECVD, MOCVD, ALD, MBE, PLD, sol-gel method or evaporation method, and combine with the The first terminal electrode 3 forms a good electrical contact;
步骤S13：通过等离子处理所述阻变介质层2的表面；Step S13: treating the surface of the resistive medium layer 2 with plasma;
步骤S14：在所述阻变介质层2的左侧或上方通过磁控溅射、PECVD、MOCVD、 ALD、MBE、PLD或蒸发法制作第二端电极1，并形成良好电接触；Step S14: making the second terminal electrode 1 on the left side or above the resistive medium layer 2 by magnetron sputtering, PECVD, MOCVD, ALD, MBE, PLD or evaporation method, and forming a good electrical contact;
若所述步骤S12中，在所述第一端电极3的左侧制作阻变介质层2，则所述步骤S14中，在所述阻变介质层2的左侧制作第二端电极1；若所述步骤S12中，在所述第一端电极3的上方制作阻变介质层2，则所述步骤S14中，在所述阻变介质层2的上方制作第二端电极1。If in the step S12, the resistive variable medium layer 2 is formed on the left side of the first terminal electrode 3, then in the step S14, the second terminal electrode 1 is formed on the left side of the resistive variable medium layer 2; If in the step S12 , the resistive variable medium layer 2 is formed above the first terminal electrode 3 , then in the step S14 , the second terminal electrode 1 is formed above the resistive variable medium layer 2 .
进一步地，所述步骤S13中进行等离子处理采用的等离子源是Ar、N2、O2、CF4、SF6、NH3、H2、CHF3气体中的一种或几种。Further, the plasma source used for plasma treatment in step S13 is one or more of Ar, N 2 , O 2 , CF 4 , SF 6 , NH 3 , H 2 , CHF 3 gases.
本实施例还提供一种阻变存储器，如图1中（a）和（b）所示，包括一衬底4；一第一端电极3，设置于所述衬底4上，并与所述衬底4形成良好电接触；一双层阻变介质，设置于所述第一端电极3的左侧或上方；一第二端电极1，若所述双层阻变介质设置于所述第一端电极3的左侧，则所述第二端电极1设置于所述双层阻变介质的左侧；若所述双层阻变介质设置于所述第一端电极3的上方，则所述第二端电极1设置于所述双层阻变介质的上方；其中，所述的双层阻变介质是由第一阻变层21与第二阻变层22组成的叠层结构。This embodiment also provides a resistive variable memory, as shown in (a) and (b) in FIG. The substrate 4 forms a good electrical contact; a double-layer resistive medium is arranged on the left side or above the first terminal electrode 3; a second terminal electrode 1, if the double-layer resistive medium is arranged on the On the left side of the first terminal electrode 3, the second terminal electrode 1 is arranged on the left side of the double-layer resistive medium; if the double-layer resistive medium is arranged above the first terminal electrode 3, Then the second terminal electrode 1 is arranged above the double-layer resistive medium; wherein, the double-layer resistive medium is a laminated structure composed of a first resistive layer 21 and a second resistive layer 22 .
在本实施例中，所述衬底4为聚合物、金属、半导体或绝缘体；所述端电极1和3为导电金属、金属合金、导电金属化合物或半导体；所述的双层存储介质为半导体或绝缘体。In this embodiment, the substrate 4 is a polymer, metal, semiconductor or insulator; the terminal electrodes 1 and 3 are conductive metal, metal alloy, conductive metal compound or semiconductor; the double-layer storage medium is a semiconductor or insulators.
在本实施例中，所述聚合物包括塑料、橡胶、PET、PEN、PEEK、PC、PES、PAR、PCO、PMMA以及PI；所述导电金属包括Ta、Cu、Pt、Ti、Au、W、Ni、Al以及Ag；所述金属合金包括Pt/Ti、Ti/Ta、Cu/Ti、Cu/Au、Ti/W以及Al/Zr；所述导电金属化合物包括TiN、TiW、TaN以及WSi；所述半导体包括Si、ZrOx、Ge、ZnO、ITO、GZO、AZO、TiOx、TaOx、HfOx、GeOx以及FTO；所述绝缘体包括AlOx、MgO、ZrOx、HfOx、GeOx以及SiOx。In this embodiment, the polymer includes plastic, rubber, PET, PEN, PEEK, PC, PES, PAR, PCO, PMMA, and PI; the conductive metal includes Ta, Cu, Pt, Ti, Au, W, Ni, Al, and Ag; the metal alloys include Pt/Ti, Ti/Ta, Cu/Ti, Cu/Au, Ti/W, and Al/Zr; the conductive metal compounds include TiN, TiW, TaN, and WSi; Said semiconductors include Si, ZrO x , Ge, ZnO, ITO, GZO, AZO, TiO x , TaO x , HfO x , GeO x and FTO; said insulators include AlO x , MgO, ZrO x , HfO x , GeO x and SiO x .
在本实施例中，提供一种提高上述阻变存储器正负向电流差的方法，采用等离子处理所述双层阻变介质的内部，包括以下步骤：In this embodiment, a method for increasing the positive and negative current difference of the above-mentioned resistive variable memory is provided, and plasma is used to treat the inside of the double-layer resistive variable medium, including the following steps:
步骤S21：在衬底4上通过磁控溅射、PECVD、MOCVD、 ALD、MBE、PLD或蒸发法制作第一端电极；Step S21: making a first terminal electrode on the substrate 4 by magnetron sputtering, PECVD, MOCVD, ALD, MBE, PLD or evaporation;
步骤S22：在所述第一端电极3的左侧或上方通过磁控溅射、PECVD、MOCVD、 ALD、MBE、PLD、溶胶凝胶法或蒸发法制作第二阻变层22，并与所述第一端电极3形成良好电接触；Step S22: Fabricate the second resistive layer 22 on the left side or above the first terminal electrode 3 by magnetron sputtering, PECVD, MOCVD, ALD, MBE, PLD, sol-gel method or evaporation method, and combine with the The first terminal electrode 3 forms a good electrical contact;
步骤S23：通过等离子处理所述第二阻变层22的表面；Step S23: treating the surface of the second resistive variable layer 22 with plasma;
步骤S24：在所述等离子处理过第二阻变层22的左侧或上方通过磁控溅射、PECVD、MOCVD、 ALD、MBE、PLD、溶胶凝胶法或蒸发法制作第一阻变层21，并与所述第二阻变层22形成良好电接触；Step S24: Fabricate the first resistive layer 21 on the left side or above the plasma-treated second resistive layer 22 by magnetron sputtering, PECVD, MOCVD, ALD, MBE, PLD, sol-gel method or evaporation method , and form a good electrical contact with the second resistive switch layer 22;
步骤S25：在所述第一阻变层21的左侧或上方通过磁控溅射、PECVD、MOCVD、 ALD、MBE、PLD或蒸发法制作第二端电极1，并形成良好电接触；Step S25: Fabricate the second terminal electrode 1 on the left side or above the first resistive layer 21 by magnetron sputtering, PECVD, MOCVD, ALD, MBE, PLD or evaporation method, and form a good electrical contact;
若所述步骤S22中，在所述第一端电极3的左侧制作第二阻变层22，则所述步骤S24中，在所述第二阻变层22的左侧制作第一阻变层21；若所述步骤S22中，在所述第一端电极3的上方制作第二阻变层22，则所述步骤S24中，在所述第二阻变层22的上方制作第一阻变层21；If in the step S22, the second resistive switch layer 22 is fabricated on the left side of the first terminal electrode 3, then in the step S24, the first resistive switch layer 22 is fabricated on the left side of the second resistive switch layer 22 layer 21; if in the step S22, the second resistive layer 22 is fabricated above the first terminal electrode 3, then in the step S24, the first resistive layer 22 is fabricated above the second resistive layer 22. variable layer 21;
若所述步骤S24中，在所述第二阻变层22的左侧制作第一阻变层21，则所述步骤S25中，在所述第一阻变层21的左侧制作第二端电极1；若所述步骤S24中，在所述第二阻变层22的上方制作第一阻变层21，则所述步骤S25中，在所述第一阻变层21的上方制作第二端电极1。If in the step S24, the first resistive layer 21 is formed on the left side of the second resistive layer 22, then in the step S25, the second end is formed on the left side of the first resistive layer 21 Electrode 1; if in the step S24, the first resistive layer 21 is fabricated above the second resistive layer 22, then in the step S25, a second resistive layer 21 is fabricated above the first resistive layer 21. terminal electrode 1.
在本实施例中，所述步骤S23中进行等离子处理采用的等离子源是Ar、N2、O2、CF4、SF6、NH3、H2、CHF3气体中的一种或几种。In this embodiment, the plasma source used for plasma treatment in step S23 is one or more of Ar, N 2 , O 2 , CF 4 , SF 6 , NH 3 , H 2 , and CHF 3 gases.
在本实施例中，如图2所示，未经等离子处理ZnO表面处氧空位（Ob）在总氧（Oa+Ob+Oc）的占比明显小于经等离子处理后ZnO表面处氧空位在总氧中的占比。因此，等离子处理在ZnO表面处引入了氧空位缺陷。而正是由于这些氧空位缺陷的存在调整了界面处的势垒，这将影响电荷的输运行为并改变电流的正负向电流差，进而影响整流特性。In this example, as shown in Figure 2, the proportion of oxygen vacancies (Ob) in the total oxygen (Oa+Ob+Oc) on the ZnO surface without plasma treatment is significantly smaller than that in the total oxygen (Oa+Ob+Oc) on the ZnO surface after plasma treatment. proportion of oxygen. Therefore, plasma treatment introduces oxygen vacancy defects at the ZnO surface. It is precisely because of the existence of these oxygen vacancy defects that the potential barrier at the interface is adjusted, which will affect the charge transport behavior and change the positive and negative current difference of the current, thereby affecting the rectification characteristics.
以下结合优选的实施例进行详细说明。The following describes in detail in conjunction with preferred embodiments.
实施例1：Example 1:
一种阻变存储器，其结构如图1中的（a）所示，由玻璃衬底4、厚度为200 nm的ITO作为第一端电极3、厚度为15nm的ZnO作为第二阻变层22、厚度为30nm的HfOx作为第一阻变层21和厚度为200nm的Ti作为第二端电极1构成。A resistive variable memory, the structure of which is shown in (a) in Figure 1, consists of a glass substrate 4, ITO with a thickness of 200 nm as the first terminal electrode 3, and ZnO with a thickness of 15 nm as the second resistive variable layer 22 , HfO x with a thickness of 30 nm as the first resistive layer 21 and Ti with a thickness of 200 nm as the second terminal electrode 1 .
为了提高该阻变存储器正负向电流差，其具体制作步骤如下：In order to increase the positive and negative current difference of the resistive variable memory, the specific manufacturing steps are as follows:
将具有ITO导电薄膜的玻璃衬底放入真空室中，采用磁控溅射制备15nm的ZnO作为第二阻变层22；随后用具有（60瓦、120秒）、（100瓦、120秒）和（100瓦、200秒）三对参数的Ar等离子处理ZnO第二阻变层22；接着采用磁控溅射制备30nm的HfOx作为第一阻变层21，从而形成双层存储介质；其后，在HfOx之上溅射200nm的Ti电极。最后，通过微电子加工工艺，加工出分离的阻变存储器，其电极面积约为40000平方微米。Put the glass substrate with the ITO conductive film into the vacuum chamber, and prepare 15nm ZnO as the second resistive layer 22 by magnetron sputtering; and (100 watts, 200 seconds) Ar plasma treatment of three pairs of parameters to treat the ZnO second resistive layer 22; then use magnetron sputtering to prepare 30nm HfO x as the first resistive layer 21, thereby forming a double-layer storage medium; Afterwards, a 200 nm Ti electrode was sputtered on top of the HfOx . Finally, through the microelectronic processing technology, a separate resistive variable memory is processed, and its electrode area is about 40,000 square microns.
图3是三种不同参数处理后HfOx/ZnO阻变存储器的电流-电压特性。从图上可以看出，随着Ar等离子处理能量（功率×作用时间）的增加，正向电流与负向电流的比率增大（由~10倍增强到~60倍），体现出整流效果的增强。Fig. 3 is the current-voltage characteristics of the HfO x /ZnO RRAM after processing with three different parameters. It can be seen from the figure that with the increase of Ar plasma treatment energy (power × action time), the ratio of positive current to negative current increases (from ~10 times to ~60 times), reflecting the rectification effect. enhanced.
实施例2：Example 2:
一种阻变存储器，其结构如图1中的（d）所示，由PET衬底4、厚度为200 nm的Ti作为第一端电极3、长度为10 μm直径为50 nm的ZnO纳米线作为阻变介质层2，厚度为200 nm的Ti作为第二端电极1构成。A resistive variable memory, the structure of which is shown in (d) in Figure 1, consists of a PET substrate 4, Ti with a thickness of 200 nm as the first terminal electrode 3, and ZnO nanowires with a length of 10 μm and a diameter of 50 nm As the resistive dielectric layer 2 , Ti with a thickness of 200 nm is used as the second terminal electrode 1 .
为了提高该阻变存储器正负向电流差，其具体制作步骤如下：In order to increase the positive and negative current difference of the resistive variable memory, the specific manufacturing steps are as follows:
将ZnO纳米线撒在PET衬底之上，然后通过磁控溅射的方式将第一端电极制作在ZnO纳米线上，接着采用100瓦Ar等离子处理ZnO纳米线120秒，随后在ZnO纳米线另一端用磁控溅射制备第二端电极。Sprinkle the ZnO nanowires on the PET substrate, and then make the first end electrode on the ZnO nanowires by magnetron sputtering, then use 100 watts Ar plasma to treat the ZnO nanowires for 120 seconds, and then place the ZnO nanowires on the ZnO nanowires. On the other end, the second end electrode is prepared by magnetron sputtering.
通过测试可以看到，如图4所示，未经Ar等离子处理ZnO纳米线正负向电流差几乎可以忽略，然而经过Ar等离子处理之后的ZnO纳米线具有极其明显正负向电流的差异性，正负向电流比为1000倍，体现出极强的整流效应。It can be seen from the test that, as shown in Figure 4, the difference between the positive and negative currents of ZnO nanowires without Ar plasma treatment is almost negligible, but the difference between the positive and negative currents of ZnO nanowires after Ar plasma treatment is extremely obvious, The ratio of positive and negative currents is 1000 times, showing a strong rectification effect.
以上是本发明的较佳实施例，凡依本发明技术方案所作的改变，所产生的功能作用未超出本发明技术方案的范围时，均属于本发明的保护范围。The above are the preferred embodiments of the present invention, and all changes made according to the technical solution of the present invention, when the functional effect produced does not exceed the scope of the technical solution of the present invention, all belong to the protection scope of the present invention.
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| CN101878530A (en) * | 2008-10-01 | 2010-11-03 | 松下电器产业株式会社 | Nonvolatile memory element and nonvolatile memory device using same |
| CN103794718A (en) * | 2012-10-31 | 2014-05-14 | 上海华虹宏力半导体制造有限公司 | Preparation method of tungsten oxide variable-resistance material in resistive random access memory |
| CN103325941A (en) * | 2013-06-03 | 2013-09-25 | 清华大学 | Forming method of metallic oxide layer in resistive random access memory |
| CN104103756A (en) * | 2014-07-25 | 2014-10-15 | 福州大学 | Resistive random access memory and method for realizing multi-value storage through the same |
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