CN105226094B - Semiconductor structure - Google Patents

Abstract

The present invention discloses a semiconductor structure. The semiconductor structure includes a substrate, a first well formed in the substrate, a first heavily doped region formed in the first well, a second heavily doped region formed in the substrate and separated from the first well, a second well formed under the second heavily doped region in the substrate, a gate dielectric formed on the substrate between the first heavily doped region and the second heavily doped region, and a gate electrode formed on the gate dielectric. The gate dielectric has a substantially uniform thickness at least across a portion extending from one side close to the second heavily doped region. The first well has a first doping type. The first heavily doped region, the second heavily doped region, and the second well have a second doping type.

Description

semiconductor structure

technical field

The present invention relates to a semiconductor structure, and more particularly, the invention relates to a semiconductor structure including an electrostatic discharge (ESD) protection element.

Background technique

Electrostatic discharge can lead to the destruction of sensitive electronic components. Therefore, ESD protection components are often provided in semiconductor structures. High-voltage electronic components, such as extended drain metal oxide semiconductor field effect transistor (ExtendedDrain MOSFET, EDMOSFET), lateral double-diffused metal oxide semiconductor field effect transistor (Lateral Double-diffused MOSFET, LDMOSFET) and application of reduced surface field , RESURF) technology components, etc., can be used as electrostatic discharge protection components.

The ESD protection performance of high-voltage electronic components is generally related to the overall width of the component and the surface/lateral rule. However, limited by the requirement of low on-resistance for high voltage electronic components, the surface/lateral scale cannot be increased.

Although low on-resistance is required, low on-resistance causes current to concentrate on the surface or drain side during electrostatic discharge. High currents and intense electric fields can cause physical damage to surface junctions.

High breakdown voltage is another requirement for high-voltage electronic components, which is always higher than the operating voltage. In addition, the driving voltage of ESD protection components is generally much higher than the breakdown voltage. Therefore, during electrostatic discharge, the protected component may be destroyed before the protective component is opened. Therefore, it is necessary to reduce the driving voltage of the ESD protection element.

Contents of the invention

In the present invention, a semiconductor structure comprising an improved electrostatic discharge protection element is proposed.

According to some embodiments, a semiconductor structure includes a substrate, a first well, a first heavily doped region, a second heavily doped region, a second well, a gate dielectric and a gate electrode. The first well is formed in the substrate. The first well has a first doping type. The first heavily doped region is formed in the first well. The first heavily doped region has a second doping type. The second heavily doped region is formed in the substrate and separated from the first well. The second heavily doped region has a second doping type. The second well is formed under the second heavily doped region in the substrate. The second well has a second doping type. The gate dielectric is formed on the substrate between the first heavily doped region and the second heavily doped region, and is at least partially formed on the first well. The gate dielectric has a substantially uniform thickness at least across a portion extending from a side proximate to the second heavily doped region. A gate electrode is formed on the gate dielectric.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the preferred embodiments are specifically cited below, together with the attached drawings, and are described in detail as follows:

Description of drawings

FIG. 1 is a schematic top view of a semiconductor structure according to an embodiment.

FIG. 2 is a schematic cross-sectional view of a semiconductor structure according to an embodiment.

3-4 are graphs illustrating characteristics of a semiconductor structure according to an example of the present invention.

FIG. 5 is a graph showing characteristics of a semiconductor structure according to a comparative example.

FIG. 6 is a schematic cross-sectional view of a semiconductor structure according to an embodiment.

FIG. 7 is a schematic cross-sectional view of a semiconductor structure according to an embodiment.

FIG. 8 is a schematic cross-sectional view of a semiconductor structure according to an embodiment.

FIG. 9 is a schematic cross-sectional view of a semiconductor structure according to an embodiment.

FIG. 10 is a schematic top view of a semiconductor structure according to an embodiment.

【Symbol Description】

100, 100': Electrostatic discharge protection components

102: Substrate

104, 204, 304: the first well

106, 306: the first heavily doped region

108, 308: the second heavily doped region

110, 310: second well

112, 212: gate dielectric

112s: One side of the gate dielectric

114, 314: gate electrode

116: the first doped region

118, 318: the second doped region

120, 320: the third heavily doped region

122, 322: deep well

124: Source contact

126: Drain contact

128: Gate contact point

130: field oxide

232: Buried layer

d: distance

t, t1, t2: Thickness

Detailed ways

A semiconductor structure including an electrostatic discharge protection element and a method of manufacturing the same will now be described. Some elements in the drawings may be enlarged or omitted for clarity. Where possible, like elements are indicated with like element numbers.

Please refer to FIG. 1 , which shows a schematic diagram of a semiconductor structure according to an embodiment. A cross section taken along line AA' in FIG. 1 may have the morphology shown in FIG. 2 .

The semiconductor structure includes an ESD protection device 100 and a substrate 102 . The substrate 102 may be a silicon substrate or a silicon-on-insulator (SOI) substrate, etc., and optionally includes layers formed thereon. The substrate 102 can be fabricated by epitaxial or non-epitaxial methods. The substrate 102 may have a p-type doping type or an n-type doping type. Here, the substrate 102 has, for example, a p-type doping type.

In FIG. 2 , the ESD protection device 100 is exemplarily shown in the form of an EDMOSFET. However, the present embodiment is not limited thereto. For example, the ESD protection device 100 may have an LDMOSFET form. The ESD protection device 100 includes a first well 104 , a first heavily doped region 106 , a second heavily doped region 108 , a second well 110 , a gate dielectric 112 and a gate electrode 114 . The first well 104 is formed in the substrate 102 . The first well 104 has a first doping type. The first heavily doped region 106 is formed in the first well 104 . The first heavily doped region 106 has a second doping type. The second heavily doped region 108 is formed in the substrate 102 and separated from the first well 104 . The second heavily doped region 108 has a second doping type. In some examples, the first heavily doped region 106 is connected to the source, and the second heavily doped region 108 is connected to the drain. The distance d from the edge of the second heavily doped region 108 to the gate can be used to adjust the breakdown voltage and driving voltage of the ESD protection device 100 , for example, the breakdown voltage can be adjusted in the range of 18V to 50V. More specifically, the reduction of the distance d can reduce the breakdown voltage and driving voltage. The second well 110 is formed under the second heavily doped region 108 in the substrate 102 . The second well 110 has a second doping type. The placement of the second well 110 allows the current flow down and away from the surface. In this way, the ESD protection performance can be improved. In this embodiment, the first doping type may be a p-type doping type, and the second doping type may be an n-type doping type. Alternatively, in another embodiment, the first doping type may be an n-type doping type, and the second doping type may be a p-type doping type.

A gate dielectric 112 is formed on the substrate 102 between the first heavily doped region 106 and the second heavily doped region 108 and at least partially formed on the first well 104 . The gate dielectric 112 is formed such that it has a substantially uniform thickness t across at least a portion extending from the side 112 s proximate to the second heavily doped region 108 . In the present embodiment, the gate dielectric 112 has a substantially uniform thickness t across the entire gate dielectric 112 . In some examples, the thickness t is approximately to In this embodiment, a dielectric layer such as an oxide layer formed on the substrate 102 can be used as the gate dielectric 112 to replace the field oxide gate dielectric widely used in conventional EDMOSFETs. As a result, the thickness of the gate dielectric is greatly reduced, for example from about reduced to approx. Therefore, the electrostatic discharge protection performance can be improved. A gate electrode 114 is formed on the gate dielectric 112 .

The ESD protection device 100 may further include a first doped region 116 formed in the first well 104 and adjacent to the first heavily doped region 106 . The first doped region 116 has a first doping type. The first doping region 116 may be a field implantation region. Alternatively, in another embodiment, the first doped region 116 may be formed by body implantation, and the ESD protection device 100 has an LDMOSFET form.

The ESD protection device 100 may further include a second doped region 118 extending from the second heavily doped region 108 and the second well 110 along a top surface of the substrate 102 . The second doped region 118 has a second doping type. A portion of the gate dielectric 112 having a substantially uniform thickness t is formed on the second doped region 118 . The second doped region 118 may be a drift region. The breakdown voltage and driving voltage can be adjusted by the length of the drift region.

The ESD protection device 100 may further include a third heavily doped region 120 formed in the first heavily doped region 106 . The third heavily doped region 120 has the first doping type. Such an arrangement can improve the ESD protection performance.

The ESD protection device 100 may further include a deep well 122 formed in the substrate 102 . Deep well 122 has a second doping type. The first well 104 and the second well 110 are formed in the deep well 122 .

As shown in FIG. 1 , another ESD protection element 100' may be formed symmetrically to the ESD protection element 100. Referring to FIG. Moreover, the ESD protection device 100 can share the second heavily doped region 108, the second well 110 and the deep well 122 with the ESD protection device 100'. The symmetrical ESD protection components 100 and 100' work together for ESD protection.

The semiconductor structure may further include a source contact 124 , a drain contact 126 and a gate contact 128 . The semiconductor structure may also include a field oxide 130 for insulation, as shown in FIG. 2 . However, the present embodiment is not limited thereto, and any insulating structure known in the technical field of the present invention, such as shallow trench isolation (Shallow Trench Isolation, STI), can be used.

Here, the semiconductor structure can be fabricated by any standard process, such as single poly process or double poly process, or epitaxial process or non-epitaxial process, without using additional masks.

Please refer to FIGS. 3-4 , which illustrate features of a semiconductor structure according to an example of the present invention. As shown in FIG. 3 , the breakdown voltage of the semiconductor structure including the ESD protection device according to an example of the present invention is about 33.5V. As shown in FIG. 4, the driving voltage of the electrostatic discharge protection element is about 27V, which is lower than the breakdown voltage. The characteristics of the conventional ESD protection element with the same gate-to-drain distance (d value) are shown in FIG. The holding voltage remained almost the same, the breakdown voltage was close to that of the comparative example, and the driving voltage was greatly reduced.

Referring now to FIG. 6 , a cross-sectional view shows a semiconductor structure according to another embodiment. In this embodiment, the first doped region 116 and the second doped region 118 are not included in the semiconductor structure. The doping range of the first well 204 is reduced, and the first well 204 is separated from the second well 110 .

In another embodiment, as shown in FIG. 7, the deep well 122 can be removed from the semiconductor structure. As such, no insulation is provided at the bottom of the first well 104 and the second well 110 .

In another embodiment, as shown in FIG. 8 , a buried layer 232 is formed under the first well 104 and the second well 110 in the substrate 102 . The buried layer 232 has a second doping type. The buried layer 232 replaces the deep well 122 to provide isolation for the semiconductor structure.

In another embodiment, as shown in FIG. 9 , the gate dielectric 212 may have two different thicknesses t1 and t2 . The thickness t2 of the portion of the gate dielectric 212 directly on the channel region (the first doped region 116 in FIG. 9 ) is smaller than the thickness t1 of other portions. That is, the portion of the gate dielectric 212 directly on the channel region is thinner. In this way, the turn-on voltage can be reduced.

Please refer to FIG. 10 , which shows a semiconductor structure according to another embodiment in a top view. In this embodiment, the semiconductor structure has an octagonal configuration. Unlike the strip configuration shown in Figure 1, the octagonal configuration inherently has symmetry. Therefore, there is no need to arrange two symmetrical electrostatic discharge protection components. In FIG. 10, the first well 304, the first heavily doped region 306, the second heavily doped region 308, the second well 310, the gate electrode 314, the second doped region 318, the third heavily doped region 320 and deep well 322 . The cross-section taken along line B-B' in Fig. 10 may have the form shown in any one of Figs. 2-9.

Although only a striped configuration (FIG. 1) and an octagonal configuration (FIG. 10) are shown, other configurations, such as rectangular, hexagonal, circular or square configurations, etc. may be used.

To sum up, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (8)

1. A semiconductor structure comprising: a substrate; a first well formed in the substrate, the first well having a first doping type; a first heavily doped region formed in the first well, the first heavily doped region having a second doping type; a second heavily doped region formed in the substrate and separated from the first well, the second heavily doped region having the second doping type; a second well formed under the second heavily doped region in the substrate, the second well having the second doping type; a gate dielectric, formed on the substrate between the first heavily doped region and the second heavily doped region, and at least partially formed on the first well, the gate dielectric at least in having a uniform thickness across a portion extending from a side proximate the second heavily doped region; and a gate electrode formed on the gate dielectric; Wherein, the first heavily doped region is located in a first doped region, the second heavily doped region is located on the right side of a second doped region and partially above it, the first doped region and the second doped region The doped region is in direct contact with the left and right neighbors, and the gate dielectric spans between the first doped region and the second doped region; the gate dielectric has two different thicknesses t1 and t2, and the gate dielectric The thickness t2 of the portion of the dielectric directly on the channel region is smaller than the thickness t1 of the other portions, that is, the portion of the gate dielectric directly on the channel region is thinner. 2. The semiconductor structure of claim 1, wherein: The first doped region is formed in the first well and has the first doping type. 3. The semiconductor structure of claim 1, wherein: The second doped region extends from the second heavily doped region and the second well along a top surface of the substrate, the second doped region has the second doping type, wherein the gate dielectric The portion with the uniform thickness is formed on the second doped region. 4. The semiconductor structure according to claim 1, further comprising: A third heavily doped region is formed in the first heavily doped region, the third heavily doped region has the first doping type. 5. The semiconductor structure according to claim 1, further comprising: A deep well is formed in the substrate, the deep well has the second doping type, wherein the first well and the second well are formed in the deep well. 6. The semiconductor structure of claim 1, further comprising: A buried layer is formed under the first well and the second well in the substrate, the buried layer has the second doping type. 7. The semiconductor structure of claim 1, further comprising: An electrostatic discharge protection device includes the first well, the first heavily doped region, the second heavily doped region, the second well, the gate dielectric and the gate electrode. 8. The semiconductor structure of claim 7, further comprising: Another ESD protection element is formed symmetrically to the ESD protection element, wherein the ESD protection element shares the second heavily doped region and the second well with the other ESD protection element.