CN105207169A - Design method for system power protection - Google Patents

Abstract

The invention discloses a design method for system power supply protection. A P-MOS transistor Q1 with a specification higher than the system power supply current is added to the input end of the system power supply to control the switch of the system power supply; a voltage dividing resistor and a N-MOS transistor Q2 is used to control the switch of P-MOS transistor Q1, N-MOS transistor Q2 is turned on, and there is a certain voltage difference between the gate and source of P-MOS transistor Q1, then P-MOS Q1 is turned on; N-MOS transistor Q1 is turned on; When the MOS transistor Q2 is turned off, there is no voltage difference between the gate and the source of the P-MOS transistor Q1, and the P-MOS transistor Q1 is turned off; the N-MOS is controlled by a low-level active protection signal PROTECT#? The switch of Q2. The invention can effectively guarantee the safety of the system, prevent safety events such as smoke emission and fire under abnormal conditions, and provide a fast protection function for each component.

Description

A Design Method for System Power Protection

technical field

The invention relates to the technical field of server power supply, in particular to a design method for system power supply protection.

Background technique

In recent years, with the vigorous development of cloud computing, big data and other technologies, the role of servers in the entire Internet field has become more and more important, and the requirements for the security and stability of servers have also increased. This paper designs a server from the perspective of power supply security. A scheme for system power protection.

When there are some abnormal conditions in the system (such as sudden rise in system temperature, hardware logic error, system back-end short circuit, power supply error, etc.), the server hopes to cut off the power immediately to prevent burning of the back-end CPU, hard disk, memory and other main components. At the same time, prevent more serious safety regulations (smoke, fire, explosion, etc.) incidents. In the traditional design, the fuse is mainly used for protection, but the fuse can only protect the system from excessive current or high temperature, and the reaction speed is slow after an abnormality occurs, and the protection is irreversible after the protection occurs. Therefore, pure fuse protection is far from enough for the safety and stability of the system.

Contents of the invention

The technical problem to be solved by the present invention is: in order to solve this problem, the present invention provides a switch circuit for power protection. When the system works normally and no protection occurs, the switch is turned on; Quickly turn off the switch, cut off the power supply, and protect the entire system.

The technical scheme adopted in the present invention is:

A design method for system power supply protection, adding a P-MOS transistor Q1 with a specification higher than the system power supply current at the input end of the system power supply to control the switch of the system power supply;

Using a voltage dividing resistor and an N-MOS transistor Q2 to control the switch of the P-MOS transistor Q1, the N-MOS transistor Q2 is turned on, and there is a certain voltage difference between the gate and the source of the P-MOS transistor Q1, then P -MOSQ1 is turned on; N-MOS transistor Q2 is turned off, then there is no voltage difference between the gate and source of P-MOS transistor Q1, and P-MOS transistor Q1 is turned off;

A low-level effective protection signal PROTECT# is used to control the switch of N-MOSQ2, cut off the power supply, and protect the system. This design can enable various abnormal signals to realize the protection function without mutual influence.

When the system is abnormal, such as hardware abnormality, the relevant detection element sends out the corresponding low-level active protection signal DISABLE_PC#, and outputs a low-level active protection signal PROTECT# through two N-MOS transistors Q3 and Q4B;

Among them, the D pole of Q4B outputs the PROTECT# signal, the S pole is grounded, and the G pole is connected to the D pole of Q3; the S pole of Q3 is grounded, and the G pole is connected to the DISABLE_PC# signal; 3_3VSB is connected to the G pole of Q3 after connecting resistor R4, 5VSB After connecting the resistor R5, it is connected to the D pole of Q3.

When an abnormality occurs in the system, such as temperature abnormality, the relevant detection element sends out a corresponding low-level effective protection signal THERMAL#, and outputs a low-level effective protection signal through the conversion of two N-MOS transistors Q5 and Q6B. signal PROTECT#;

Among them, the D pole of Q6B outputs the PROTECT# signal, the S pole is grounded, and the G pole is connected to the D pole of Q5; the S pole of Q5 is grounded, and the G pole is connected to the THERMAL# signal; 3_3VSB is connected to the G pole of Q5 after connecting resistor R6, 5VSB After connecting the resistor R7, it is connected to the D pole of Q5.

The beneficial effects of the present invention are:

In the present invention, when the system is working normally without protection, the switch is turned on; when an abnormal situation occurs in the system, a power-off signal is sent to quickly turn off the switch, cut off the power supply, and protect the entire system, which can effectively ensure the safety of the system and prevent Safety events such as smoke and fire occur under abnormal conditions, providing a fast protection function for each component.

Description of drawings

Fig. 1 is a schematic diagram of the system protection circuit of the present invention;

Figure 2 is a schematic diagram of the system hardware forced shutdown protection circuit;

FIG. 3 is a schematic diagram of a system temperature forced shutdown protection circuit.

Detailed ways

The present invention will be further described below in conjunction with specific embodiments according to the accompanying drawings of the description:

Example 1:

A design method for system power supply protection, adding a P-MOS transistor Q1 with a specification higher than the system power supply current at the input end of the system power supply to control the switch of the system power supply;

Using a voltage dividing resistor and an N-MOS transistor Q2 to control the switch of the P-MOS transistor Q1, the N-MOS transistor Q2 is turned on, and there is a certain voltage difference between the gate and the source of the P-MOS transistor Q1, then P -MOSQ1 is turned on; N-MOS transistor Q2 is turned off, then there is no voltage difference between the gate and source of P-MOS transistor Q1, and P-MOS transistor Q1 is turned off;

A low-level effective protection signal PROTECT# is used to control the switch of N-MOSQ2, cut off the power supply, and protect the system. This design can enable various abnormal signals to realize the protection function without mutual influence.

Example 2:

On the basis of Embodiment 1, in this embodiment, when an abnormality occurs in the system, such as hardware abnormality, the relevant detection element sends a corresponding low-level active protection signal DISABLE_PC#, through two N-MOS transistors Q3, Q4B, Output a low-level active protection signal PROTECT#;

Among them, the D pole of Q4B outputs the PROTECT# signal, the S pole is grounded, and the G pole is connected to the D pole of Q3; the S pole of Q3 is grounded, and the G pole is connected to the DISABLE_PC# signal; 3_3VSB is connected to the G pole of Q3 after connecting resistor R4, 5VSB After connecting the resistor R5, it is connected to the D pole of Q3.

Example 3:

On the basis of Embodiment 1, in this embodiment, when an abnormality occurs in the system, such as abnormal temperature, etc., the relevant detection element sends out a corresponding low-level active protection signal THERMAL#, through two N-MOS transistors Q5, Q6B conversion, output a low-level active protection signal PROTECT#;

Among them, the D pole of Q6B outputs the PROTECT# signal, the S pole is grounded, and the G pole is connected to the D pole of Q5; the S pole of Q5 is grounded, and the G pole is connected to the THERMAL# signal; 3_3VSB is connected to the G pole of Q5 after connecting resistor R6, 5VSB After connecting the resistor R7, it is connected to the D pole of Q5.

The specific implementation steps are as follows:

1) If the system is normal, all trigger signals, such as DISABLE_PC# and THERMAL# in Fig. 2 and Fig. 3, are at high level, then N-MOS transistors Q3 and Q5 are turned on, and the gates of N-MOS transistors Q4B and Q6B If the voltage is pulled to a low level, Q4B and Q6B cannot be turned on;

As shown in Figure 1, the PROTECT# signal maintains the voltage of the Zener diode (3.1~3.4V), and the N-MOS transistor Q2 is normally turned on; after Q2 is turned on, R1 and R3 divide the voltage, and the gate of the P-MOS transistor Q1 The pole and the source generate a pressure difference and open, and the system supplies power normally;

2) If there is a problem with any detection signal of the system, take the overheating protection of the system as an example, as shown in Figure 3, if the THERMAL# signal sends out a low level, then the gate voltage of the N-MOS transistor Q5 is low level, Q5 cannot be turned on, and the gate of N-MOS transistor Q6B is 5V. If Q6B can be turned on, PROTECT# is pulled to low level;

3) As shown in Figure 1, when PROTECT# is pulled to a low level, the N-MOS transistor Q2 cannot be turned on, so that the gate and source voltages of the P-MOS transistor Q1 are the same, and voltage division cannot be performed, and the P-MOS transistor Q1 cannot be divided. MOS tube Q1 is closed, and the system cuts off the power supply for protection.

The above embodiments are only used to illustrate the present invention, but not to limit the present invention. Those of ordinary skill in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, all Equivalent technical solutions also belong to the category of the present invention, and the scope of patent protection of the present invention should be defined by the claims.

Claims (3)

1. a method for designing for system power supply protection, is characterized in that: add a P-MOS pipe Q1 higher than the specification of system power supply electric current, for the switch of control system power supply at the input of system power supply;

Utilize the control that divider resistance and N-MOS pipe Q2 realize P-MOS pipe Q1 switch, N-MOS pipe Q2 opens, and there is certain pressure reduction between the grid of P-MOS pipe Q1 and source electrode, then P-MOSQ1 opens; N-MOS pipe Q2 closes, then do not have pressure reduction between the grid of P-MOS pipe Q1 and source electrode, then P-MOS pipe Q1 closes;

By the switch of the guard signal PROTECT# control N-MOSQ2 of a Low level effective.

2. the method for designing of a kind of system power supply protection according to claim 1, it is characterized in that: when system occurs abnormal, relevant detecing element sends corresponding Low level effective guard signal DISABLE_PC#, by two N-MOS pipes Q3, Q4B, export a Low level effective guard signal PROTECT#;

Wherein, the D pole of Q4B exports PROTECT# signal, S pole ground connection, and G pole connects the D pole of Q3; The S pole ground connection of Q3, G pole access DISABLE_PC# signal; Access the G pole of Q3 after 3_3VSB contact resistance R4, after 5VSB contact resistance R5, access the D pole of Q3.

3. the method for designing of a kind of system power supply protection according to claim 1, it is characterized in that: when system occurs abnormal, relevant detecing element sends the guard signal THERMAL# of corresponding Low level effective, by the conversion of two N-MOS pipes Q5, Q6B, export the guard signal PROTECT# of a Low level effective;

Wherein, the D pole of Q6B exports PROTECT# signal, S pole ground connection, and G pole connects the D pole of Q5; The S pole ground connection of Q5, G pole access THERMAL# signal; Access the G pole of Q5 after 3_3VSB contact resistance R6, after 5VSB contact resistance R7, access the D pole of Q5.