CN105206529A - Fin type field effect transistor and manufacturing method thereof - Google Patents

Abstract

The invention discloses a method for manufacturing a fin field effect transistor, which comprises the following steps: providing a semiconductor substrate, wherein fins, a gate dielectric layer and a dummy gate are formed on the substrate; removing the dummy gate to form an opening; filling the opening to form a metal gate stack; removing part of the thickness of the metal gate stack above the fin and in the opening to form an opening again; the opening is refilled to form a top metal layer. The invention improves the influence of the metal gate stack pore filling, reduces the resistance of the metal gate and improves the performance of the device.

Description

Fin field effect transistor and manufacturing method thereof

technical field

The invention belongs to the field of semiconductor manufacturing, and in particular relates to a fin field effect transistor and a manufacturing method thereof.

Background technique

With the high integration of semiconductor devices, the channel length of MOSFET continues to shorten, and a series of effects that can be ignored in the long channel model of MOSFET become more and more significant, and even become the dominant factor affecting the performance of the device. This phenomenon is collectively called short channel road effect. The short channel effect will deteriorate the electrical performance of the device, such as causing a decrease in the gate threshold voltage, an increase in power consumption, and a decrease in the signal-to-noise ratio.

In order to solve the problem of short channel effect, a three-dimensional device structure of Fin Field Effect Transistor (Fin-FET) is proposed, which is a transistor with a fin-shaped channel structure, which uses several surfaces of a thin fin as a channel , can increase the operating current, which can prevent the short channel effect in conventional transistors.

With the continuous reduction of device size, Fin-FET devices with high-k metal gate structure have increasingly become the focus of research. However, when the metal gate is formed, since the gate trench is very narrow, it is difficult to control the filling of the metal gate, and the resistance will be large, which affects the performance of the device.

Contents of the invention

The object of the present invention is to overcome the deficiencies in the prior art, and provide a fin field effect transistor and a manufacturing method thereof.

To achieve the above object, the technical solution of the present invention is:

A method of manufacturing a fin field effect transistor, comprising:

A semiconductor substrate is provided, and a fin, a gate dielectric layer, and a dummy gate are formed on the substrate;

removing the dummy gate to form an opening;

filling the opening to form a metal gate stack;

Removing part of the thickness of the metal gate stack above the fin and within the opening to reform the opening;

Refill the opening to form the top metal layer.

Optionally, in the step of removing the dummy gate, the gate dielectric layer under the dummy gate is simultaneously removed to form an opening, and the gate dielectric layer is re-formed on the inner wall of the opening.

Optionally, the step of forming a metal gate stack specifically includes:

forming a first metal layer on the inner wall of the opening, the first metal layer is a work function adjustment layer;

forming a diffusion barrier layer on the first metal layer;

The opening is filled with the second metal layer to form a metal gate stack.

Optionally, the top metal layer and the second metal layer are made of the same material.

Optionally, between removing part of the metal gate stack inside the opening and forming the top metal layer, further steps are included:

A second diffusion barrier layer is formed on the inner wall of the reformed opening.

In addition, the present invention also provides a fin field effect transistor, including

a substrate on which fins are formed;

openings are formed on both sides of the fin;

a gate dielectric layer formed at least on the surface of the fin in the opening;

A metal gate stack formed within the opening to fill the lower portion of the opening, the lower portion of the opening being higher than the height of the fin;

Fill the top metal layer above the opening.

Optionally, a gate dielectric layer is formed on the inner wall of the opening.

Optionally, the metal gate stack includes:

a first metal layer formed on the lower inner wall of the opening;

a first diffusion barrier layer formed on the first metal layer;

Fill the second metal layer below the opening.

Optionally, the top metal layer and the second metal layer are made of the same material.

Optionally, the top metal layer and the second metal layer are made of the same material.

In the fin field effect transistor and its manufacturing method of the present invention, after the metal gate stack is formed in the opening, the gate stack on the upper part of the opening is further removed, and then the metal is filled, so as to improve the influence of the hole filling of the metal gate stack, and at the same time, reduce the Smaller metal gate resistance improves device performance.

Description of drawings

In order to more clearly illustrate the technical solutions implemented by the present invention, the following will briefly introduce the accompanying drawings that need to be used in the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those skilled in the art Ordinary technicians can also obtain other drawings based on these drawings on the premise of not paying creative work.

Fig. 1 shows the flow chart of the manufacturing method of the fin field effect transistor of the present invention;

2-11 are schematic cross-sectional views of gates along the fin direction during each manufacturing process of manufacturing a fin field effect transistor according to an embodiment of the present invention.

Detailed ways

In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

In the following description, a lot of specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described here, and those skilled in the art can do it without departing from the meaning of the present invention. By analogy, the present invention is therefore not limited to the specific examples disclosed below.

Secondly, the present invention is described in detail in combination with schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, and it should not be limited here. The protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production.

In order to better understand the present invention, the manufacturing method of the embodiment of the present invention will be described in detail below in conjunction with the flowchart of FIG. 1 and the schematic diagrams of the embodiment of the present invention FIGS. 2-11. All the following cross-sectional schematics are cross-sectional schematics along the fin direction.

First, a substrate (not shown in the figure) is provided.

In this embodiment, the substrate is an SOI substrate, and the SOI substrate includes a back substrate, a buried oxide layer and a top silicon layer. In other embodiments, the substrate may also be other substrate structures including semiconductor layers.

Then, a fin 100 is formed in the substrate, as shown in FIG. 2 .

In this embodiment, specifically, a cap layer (not shown) can be formed on the top layer of silicon, and then the cap layer can be patterned, and the cap layer can be used as a hard mask, using an etching technique such as RIE (reaction Ion etching) method, etch the top layer of silicon to form fins 100 in the top layer of silicon, and then further remove the hard mask.

Next, a gate dielectric layer 102 and a dummy gate 104 are formed on the fin 100 , as shown in FIGS. 2-4 .

Specifically, the gate dielectric material, the dummy gate material and the hard mask material are respectively formed first. As shown in FIG. Silicon can be formed by thermal oxidation. The dummy gate can be amorphous silicon, polysilicon, etc., and in this embodiment, it is amorphous silicon. Then, under the cover of the hard mask, the dummy gate material is etched to form a dummy gate 104 across the fin. In this embodiment, the silicon dioxide formed by thermal oxidation is used as a gate dielectric layer, and also as a stop layer for subsequent formation of sidewalls and etching of dummy gates.

Next, spacer walls 106 are formed on the sidewalls of the dummy gate and cover both sides of the dummy gate to form an interlayer dielectric layer 108 , as shown in FIG. 5 .

The sidewall can have a single-layer or multi-layer structure, and can be made of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, fluoride-doped silicon glass, low-k dielectric materials and combinations thereof, and/or other suitable material formed. In this embodiment, the sidewall 106 is a single-layer silicon nitride sidewall.

Dielectric materials can be deposited by suitable deposition methods, such as undoped silicon oxide (SiO ₂ ), doped silicon oxide (such as borosilicate glass, borophosphosilicate glass, etc.), silicon nitride (Si ₃ N ₄ ) or other low-k dielectric materials, and then perform planarization, such as CMP (Chemical Mechanical Polishing), until the dummy gate is exposed to form the interlayer dielectric layer (ILD) 108 , as shown in FIG. 5 .

Next, the dummy gate 104 is removed to form an opening 110 , as shown in FIG. 6 .

The dummy gate can be removed by wet etching. In this embodiment, the amorphous silicon is removed by tetramethylammonium hydroxide (TMAH), thereby forming an opening 110 in the area of the original dummy gate, as shown in FIG. 6 .

Next, in order to improve the quality of the gate dielectric layer, the gate dielectric layer under the dummy gate can be further removed, and then a new gate dielectric layer can be re-formed. Specifically, the interface layer 112 can be formed in the opening first, and the gate dielectric layer can be formed by thermal Oxidation method is formed, then, deposition dielectric material layer 114, for example is high-k dielectric material (for example, compared with silicon oxide, has the material of high dielectric constant) or other suitable dielectric material, high-k dielectric material such as hafnium Based oxides, HFO2, HfSiO, HfSiON, HfTaO, HfTiO, etc.

Next, a metal gate stack is formed in the opening 110 , as shown in FIG. 8 .

The metal gate stack is a gate stack including a metal layer, such as Ti, TiAl _x , TiN, TaN _x , HfN, TiC _x , TaC _x , polysilicon and their combinations.

In this embodiment, specifically, first, the first metal layer 120 is deposited, and the first metal layer is a work function adjustment layer. For NMOS, Al and TiAl can be selected, and for PMOS, Ta and TaN can be selected. . Then, a diffusion barrier layer is deposited to block the diffusion of the upper metal layer to the first metal layer and the gate dielectric layer. The first diffusion barrier layer can be a Ti layer 124 and a TiN layer 126. Then, the second metal layer 128 is filled. For example, it is W, as shown in FIG. 7 . Then, planarization, such as chemical mechanical polishing, is performed until the interlayer dielectric layer 108 is exposed, thereby forming a metal gate stack in the opening 110 , as shown in FIG. 8 .

Then, the metal gate stack above the fin and inside the opening is partially removed to re-form the opening 130 , as shown in FIG. 9 .

In this embodiment, RIE (Reactive Ion Etching) method can be used to remove part of the thickness of the metal gate stack in the opening above the fin, that is, to remove the metal gate stack on the upper part of the opening to re-form part of the opening 130. In this embodiment, During the etching, the gate dielectric layer 114 is simultaneously removed, as shown in FIG. 9 .

Next, the opening is refilled to form a top metal layer 138 as shown in FIG. 11 .

In this embodiment, firstly, deposit the second diffusion barrier layer, the second diffusion barrier layer can be Ti layer 134, TiN layer 136, then, deposit the top metal layer 138, and this top metal layer 138 adopts and the second metal layer 128 the same material or a different material, such as W, as shown in FIG. 10 . Then, planarization, such as chemical mechanical polishing, is performed until the interlayer dielectric layer 108 is exposed, so that the top metal layer 138 is re-formed on the upper part of the opening, as shown in FIG. 11 .

So far, the fin field effect transistor formed according to the manufacturing method of the present invention is formed.

In addition, the present invention also provides a fin field effect transistor formed by using the manufacturing method and the embodiment of the present invention.

As shown in FIG. 11 , the fin field effect transistor includes: a substrate on which a fin 100 is formed; openings 110 are formed on both sides of the fin; a gate dielectric layer 114 is formed at least on the surface of the fin in the opening ; a metal gate stack formed in the opening to fill the lower part of the opening, the lower part of the opening is higher than the height of the fin; a top metal layer 138 to fill the upper part of the opening.

In the above embodiment, as shown in FIG. 11 , a gate dielectric layer 114 is formed on the entire inner wall of the opening, and the gate dielectric layer is a high-k gate dielectric layer.

The metal gate stack includes: a first metal layer 120 formed on the inner wall of the lower part of the opening; first diffusion barrier layers 124 and 126 formed on the first metal layer; and a second metal layer 128 filling the lower part of the opening. The top metal layer 138 and the second metal layer 128 are made of the same material or different materials, such as W.

A second diffusion barrier layer 134, 136 is formed between the inner wall of the upper portion of the opening and the top metal layer.

The above descriptions are only preferred embodiments of the present invention, and do not limit the present invention in any form.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person familiar with the art, without departing from the scope of the technical solution of the present invention, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent implementation of equivalent changes example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (10)

1. a manufacture method for fin formula field effect transistor, is characterized in that, comprising:

Semiconductor substrate is provided, described substrate is formed with fin and gate dielectric layer, dummy grid;

Remove dummy grid, to form opening;

Fill up opening stacking to form metal gate;

Remove on fin, open interior divides the metal gate of thickness stacking, again to form opening;

Again opening is filled up, to form metal layer at top.

2. manufacture method according to claim 1, is characterized in that, in the step removing dummy grid, removes the gate dielectric layer under dummy grid simultaneously, to form opening, and again forms gate dielectric layer on opening inwall.

3. manufacture method according to claim 1, is characterized in that, the step forming metal gate stacking specifically comprises:

The inwall of opening forms the first metal layer, and described the first metal layer is work function regulating course;

Form diffusion impervious layer on the first metal layer;

Opening is filled up with the second metal level, stacking to form metal gate.

4. manufacture method according to claim 3, is characterized in that, described metal layer at top and the second metal level are same material.

5. manufacture method according to claim 1, is characterized in that, the metal gate heap superimposition divided in removal open interior is formed between metal layer at top, also comprises step:

The inwall of the opening again formed is formed the second diffusion impervious layer.

6. a fin formula field effect transistor, is characterized in that, comprising:

Substrate, substrate is formed with fin;

The both sides of described fin are formed with opening;

At least in opening fin surface on the gate dielectric layer that formed;

The metal gate filling up lower opening portion formed in opening is stacking, and lower opening portion is higher than the height of fin;

Fill up the metal layer at top of upper opening portion.

7. fin formula field effect transistor according to claim 6, is characterized in that, the inwall of opening is formed with gate dielectric layer.

8. fin formula field effect transistor according to claim 1, is characterized in that, described metal gate is stacking to be comprised:

Be formed in the first metal layer on lower opening portion inwall;

Form the first diffusion impervious layer on the first metal layer;

Fill up the second metal level of lower opening portion.

9. fin formula field effect transistor according to claim 8, is characterized in that, described metal layer at top and the second metal level are same material.

10. fin formula field effect transistor according to claim 1, is characterized in that, also comprises: the second diffusion impervious layer formed between the inwall and metal layer at top of upper opening portion.