CN105206307B - A kind of chip restorative procedure and device - Google Patents
A kind of chip restorative procedure and device Download PDFInfo
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Abstract
The present invention provides a kind of chip restorative procedure and devices, and the ECC area to solve chip can not be repaired, and the data that chip is finally read out is caused mistake and the low problem of resources of chip utilization rate occur.The method includes：The first address information of the storage unit to break down in main array is obtained respectively and is stored with the second address information that error coded corrects the storage unit of redundant digit to break down；First address information and the second address information are respectively mapped to the address information of redundant resource, chip is repaired.The present invention can simultaneously repair main array and ECC area, improve the reliability of chip, and then improve product yield.And by the address information of the second mapping address information to redundant resource, redundant resource is taken full advantage of, improves the utilization rate of resources of chip.
Description
Technical field
The present invention relates to electronic technology fields, more particularly to a kind of chip restorative procedure and device.
Background technology
With the reduction of process node, the increase of chip area, the capacity of chip is obviously improved, and the yield of chip faces
Huge challenge.In present chip, there are thousands of to tens Flash storage units, due to the inconsistency of technique, with
And other various extraneous factors, it will inevitably cause individual storage units performance therein poor or even can not make
With.Such case is encountered, if not having repair function in chip, will cause entire chip that can not work, be taken as waste paper.Work as addition
After repair function, redundant resource can be utilized to replace error unit automatically, realize the automatic reparation of bad point, to which bad point is less
Chip become available normal chip, to improve the yield of product.
In the chip of multilevel storage (Multi-Level Cell, MLC), it usually needs repaiied in redundancy (Redundancy)
Error coded is added except multiple and corrects (Error Correcting Code, ECC), the reliable of data is read to improve chip
Property.But due to the fallibility of the chip of MLC itself, the main array of ECC area and storage data for storing ECC redundant digits
There is identical error probability, it is therefore desirable to which Redundancy reparations can also be carried out to ECC area.
The composition of chip storage array is general as shown in Figure 1, by main array, and redundant resource and ECC area form.In tradition
Chip repair process in, redundant resource is only used for the reparation of bad point in main array.When some storage unit in main array
When appearance defect leads to not normal storage, this storage unit is just a bad point, and the address of cache of bad point to redundancy is provided
In source, replacement of the redundant resource to bad point is realized.It realizes after replacing, the data in main array at the time of reading, will not have mistake
Information.But after adding ECC, the data of chip final output by be main array and ECC area numeric field data combinatorial operation after
As a result, therefore, the data reliability of ECC area has same importance with main array, if there is bad point in ECC area,
There is mistake in the equally possible data for causing chip finally to read out.
Invention content
A kind of chip restorative procedure of present invention offer and device, the ECC area to solve chip can not be repaired, and chip is caused
There is mistake and the low problem of resources of chip utilization rate in the data finally read out.
To solve the above-mentioned problems, the present invention provides a kind of chip restorative procedure, the chip includes main array, mistake
Coding corrects region and redundant resource, the method includes：
The first address information of the storage unit to break down in the main array is obtained respectively and stores wrong volume
Code corrects the second address information of the storage unit of redundant digit to break down；
First address information and second address information are respectively mapped to the address information of the redundant resource,
The chip is repaired.
Preferably, second address information includes：Positioned at the error coded correct region, and with the main array
The information of the adjacent address of page address.
Preferably, the acquisition is stored with the second address that error coded corrects the storage unit of redundant digit to break down
Information, including：
It is incrementally accessed from the initial address of the page address of the main array to end address, the error coded is set
The enable signal for correcting region is effective status；
The address that the error coded adjacent with the page address of main array corrects region is accessed, second address is obtained
Information；
Wherein, when the enable signal is effective status, after the page address for accessing the main array, continue access and institute
State the address in the adjacent error coded correction region of page address of main array；When the enable signal is invalid state, institute is accessed
After the page address for stating main array, next group of page address of the main array is accessed.
Preferably, second address information is made of the information of n bit data address；The bit data address is
Positioned at the main array, and in n address being sequentially located in the page address of the main array, store the ground of main array data
The next address of location；
Wherein, n is positive integer；N address in the page address includes multiple bit data addresses.
Preferably, the acquisition is stored with the second address that error coded corrects the storage unit of redundant digit to break down
Information, including：
The page address for traversing the main array obtains the letter of m-th of address in n address in the page address successively
Breath, obtains second address information, n and m are positive integer.
Preferably, the chip includes Nor Flash.
The present invention also provides a kind of chip prosthetic device, the chip include main array, error coded correct region and
Redundant resource, described device include：
Acquisition module, the first address information for obtaining the storage unit to break down in the main array and storage
Wrong coding corrects the second address information of the storage unit of redundant digit to break down；
Repair module is provided for first address information and second address information to be respectively mapped to the redundancy
The address information in source repairs the chip.
Preferably, second address information includes：Positioned at the error coded correct region, and with the main array
The information of the adjacent address of page address.
Preferably, the acquisition module, including：
Submodule is arranged in enable signal, and the initial address for the page address from the main array is incrementally accessed to end ground
After location, it is effective status that the error coded, which is arranged, to correct the enable signal in region；
Submodule is accessed, the address in region is corrected for accessing the error coded adjacent with the page address of main array,
Obtain second address information；
Wherein, when the enable signal is effective status, after the page address for accessing the main array, continue access and institute
State the address in the adjacent error coded correction region of page address of main array；When the enable signal is invalid state, institute is accessed
After the page address for stating main array, next group of page address of the main array is accessed.
Preferably, second address information is made of the information of n bit data address；The bit data address is
Positioned at the main array, and in n address being sequentially located in the page address of the main array, store the ground of main array data
The next address of location；
Wherein, n is positive integer；N address in the page address includes multiple bit data addresses.
Preferably, the acquisition module, including：
Submodule is traversed, the page address for traversing the main array is obtained successively in n address in the page address
M-th of address information, obtain second address information, n and m are positive integer.
Preferably, the chip includes Nor Flash.
Compared with prior art, the present invention includes following advantages：
It when checking chip, not only checks whether the storage unit in main array breaks down, also checks for ECC area
Whether the storage unit in domain breaks down.If there is the storage unit to break down in main array and ECC area, respectively
Obtain the access unit address information (facilitating statement and differentiation, hereinafter referred to as the first address information) to break down in main array and
The access unit address information (facilitating statement and differentiation, hereinafter referred to as the second address information) to break down in ECC area, and handle
First address information and the second address information are respectively mapped to the address information of redundant resource, realize the reparation to chip.
The above-mentioned repair process to chip can simultaneously repair main array and ECC area, and improve chip can
By property, and then improve product yield.
By the address information of the second mapping address information to redundant resource, redundant resource is taken full advantage of, improves chip
The utilization rate of resource.
Description of the drawings
Fig. 1 is a kind of structural schematic diagram of chip storage array；
Fig. 2 is a kind of chip restorative procedure flow chart in the embodiment of the present invention one；
Fig. 3 is another chip restorative procedure flow chart in the embodiment of the present invention two；
Fig. 4 is a kind of ECC redundancies bit allocation schematic diagram in the embodiment of the present invention two；
Fig. 5 is a kind of chip prosthetic device structure chart in the embodiment of the present invention three；
Fig. 6 is another chip prosthetic device structure chart in the embodiment of the present invention four.
Specific implementation mode
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, below in conjunction with the accompanying drawings and specific real
Applying mode, the present invention is described in further detail.
A kind of chip restorative procedure and dress provided by the invention is discussed in detail below by several specific embodiments are enumerated
It sets.
Embodiment one
The embodiment of the present invention one provides a kind of chip restorative procedure.
Chip in the embodiment of the present invention can be made of main array, ECC area and redundant resource.
With reference to Fig. 2, a kind of chip restorative procedure flow chart in the embodiment of the present invention one is shown.
Step 100, the first address information and the storage of the storage unit to break down in the main array are obtained respectively
There is the second address information of the storage unit of ECC redundant digits to break down.
Main array and ECC area in the chip are two independent regions, and the storage unit in main array has specially
Address be used for mark position, but the storage unit in ECC area does not have such address.So if ECC redundant digits store
In ECC area, it is necessary to select special position in ECC area and store ECC redundant digits, conveniently work as and be stored with ECC redundant digits
When certain storage unit breaks down, it can be positioned by its special position.
If ECC redundant digits are stored in ECC area, above-mentioned second address information can be the address of above-mentioned special position
Information.
Step 102, first address information and second address information are respectively mapped to the redundant resource
Address information repairs the chip.
It, can be by the first mapping address information if getting first address information and second address information
To some address information in redundant resource, by another address information of the second mapping address information to redundant resource.Redundancy
The two address informations in resource correspond to two storage units, the two storage units can be by mapping relations to main array
In the storage unit that breaks down and the storage unit to break down for being stored with ECC redundant digits be replaced.
If the storage unit to break down for being stored with ECC redundant digits is the storage unit of ECC area, realize simultaneously
Reparation to main array and ECC area.
In conclusion in the embodiment of the present invention, when checking chip, the storage unit in main array is not only checked
Whether break down, also checks for whether the storage unit in ECC area breaks down.If existing in main array and ECC area
When the storage unit to break down, obtain respectively break down in main array access unit address information (facilitate statement and
Distinguish, hereinafter referred to as the first address information) and ECC area in the access unit address information that breaks down (facilitate statement and area
Point, hereinafter referred to as the second address information), and the first address information and the second address information be respectively mapped to the address of redundant resource
Information realizes the reparation to chip.
The above-mentioned repair process to chip can simultaneously repair main array and ECC area, and improve chip can
By property, and then improve product yield.
By the address information of the second mapping address information to redundant resource, redundant resource is taken full advantage of, improves chip
The utilization rate of resource.
Embodiment two
Second embodiment of the present invention provides a kind of chip restorative procedures.
Chip in the embodiment of the present invention can be made of main array, ECC area and redundant resource, and the embodiment of the present invention
In chip may include Nor Flash.
With reference to Fig. 3, a kind of chip restorative procedure flow chart in the embodiment of the present invention two is shown.
Step 200, the storage unit in main array is detected, and to be stored with the storage units of ECC redundant digits into
Row detection.
The storage unit for being stored with ECC redundant digits can be located at ECC area, can also be located at main array region.
Step 202, the first address information and the storage of the storage unit to break down in the main array are obtained respectively
There is the second address information of the storage unit of ECC redundant digits to break down.
According to the different location for the storage unit for being stored with ECC redundant digits, second address information can be following two
Kind situation：
(1) storage unit for being stored with ECC redundant digits is located at ECC area.
Second address information may include：Positioned at the ECC area, and it is adjacent with the page address of main array
The information of address.
In above-mentioned steps 202, the second address information of the storage unit to break down for being stored with ECC redundant digits is obtained
Process may include：
Sub-step 2021 is incrementally accessed to end address from the initial address of the page address of the main array, setting
The enable signal of the ECC area is effective status.
For example, the range of the page address of a main array is 0000~1111, wherein each address can store a word
8bit data are saved, and a total of 9bit data of ECC redundant digits need then being stored with the ECC area of ECC redundant digits to access
The address of page address is first incremented to 1111 from 0000, after 1111, there are one the enable signal ECC_ of ECC area for meeting
SEL is asserted state, while address is reset as 0000.
Above-mentioned enable signal ECC_SEL can also be regarded as a bit address, when being addressed to main array, enable signal ECC_
SEL=0 is invalid state, i.e. page address may be considered 00000~01111, after main array data, enable signal ECC_
SEL=1 is effective status, i.e. page address is 10000, and what is accessed at this time is exactly the address of ECC area, this address is corresponding
The main array data that ECC redundant digits data are 00000~01111 with address is one group, collectively constitutes one group of data.
Sub-step 2022 accesses the address of the ECC area adjacent with the page address of main array, obtains second ground
Location information.
Wherein, when the enable signal is effective status, after the page address for accessing the main array, continue access and institute
State the address of the adjacent ECC area of page address of main array；When the enable signal is invalid state, the main array is accessed
After page address, next group of page address of the main array is accessed.
By the combination of 10000 addresses and enable signal ECC_SEL=1 in above-mentioned sub-step 2021, can choose and master
The address of the adjacent ECC area of page address of array obtains the information of the address to carry out directly accessing to it, that is, obtains the
Double-address information.
(2) storage unit for being stored with ECC redundant digits is located at main array.
Second address information can be made of the information of n bit data address；The bit data address can be with
To be located at the main array, and in n address being sequentially located in the page address of the main array, store main array data
The next address of address.
Wherein, n is positive integer；N address in the page address includes multiple bit data addresses.
In above-mentioned steps 202, the second address information of the storage unit to break down for being stored with ECC redundant digits is obtained
Process can also include：
Sub-step 2023 traverses the page address of the main array, obtains the in n address in the page address successively
The information of m address obtains second address information, and n and m are positive integer.
For example, ECC redundant digits have 9bit data, the second address information that can be made of the information of 9 bit data addresses.
The ECC redundant digit data of 9bit are separately dispensed into the page address of 9 main arrays, i.e., in 0000~1,000 9 addresses,
Each address increases 1bit data, forms the nonstandard numbers of a 9bit according to (when each address of main array stores 8bit data
When, form the nonstandard numbers evidence of a 9bit；When each address of main array stores (m-1) bit data, a mbit is formed
Nonstandard numbers evidence), as shown in figure 4, in wherein 9 addresses 0000~1000, preceding part 8bit data are main array data, after
Part 1bit data are the data of increased ECC redundant digits, and increased 9 1bit data collectively constitute as ECC redundant digits.Successively
The information for obtaining the 9th address in 9 page address, obtains the second address information.This mode is exactly in order not to increase main battle array
9 bit of ECC redundant digits are dismantled and are stored to respectively in 9 main array address by the address of row, in this way in this 9 main array address
With regard to much more each 1bit data, that is, the nonstandard numbers evidence.
ECC redundant digits data can successfully be read out when normally carrying out address searching in this way.Without individually in page
Recur enable signal ECC_SEL after end of address (EOA), without can just read out ECC redundant digits after main array data every time
Data.
It should be noted that in above-mentioned steps 202, sub-step 2021 and sub-step 2022 are ordinal relation, sub-step
2021, sub-step 2022 is jointly coordination with sub-step 2023.
Step 204, first address information and second address information are respectively mapped to the redundant resource
Address information repairs the chip.
When the storage unit for being stored with ECC redundant digits is located at ECC area, by the second mapping address information to redundant resource
Address information, complete the reparation of ECC area.
In conclusion in the embodiment of the present invention, when checking chip, the storage unit in main array is not only checked
Whether break down, also checks for whether the storage unit in ECC area breaks down.If existing in main array and ECC area
When the storage unit to break down, obtain respectively break down in main array access unit address information (facilitate statement and
Distinguish, hereinafter referred to as the first address information) and ECC area in the access unit address information that breaks down (facilitate statement and area
Point, hereinafter referred to as the second address information), and the first address information and the second address information be respectively mapped to the address of redundant resource
Information realizes the reparation to chip.
The above-mentioned repair process to chip can simultaneously repair main array and ECC area, and improve chip can
By property, and then improve product yield.
Redundancy reparation is combined with ECC error correction mechanism so that the degree of freedom of redundancy reparation greatly improves, by the second address
Information MAP takes full advantage of redundant resource to the address information of redundant resource, improves the reliability and core of ECC area numeric field data
The utilization rate of piece resource.
Embodiment three
The embodiment of the present invention three provides a kind of chip prosthetic device.
Chip in the embodiment of the present invention can be made of main array, ECC area and redundant resource.
With reference to Fig. 5, a kind of chip prosthetic device structure chart in the embodiment of the present invention three is shown.
Described device may include：Acquisition module 300 and repair module 302.
The relationship between the function and each module of each module is discussed in detail separately below.
Acquisition module 300, for obtain the storage unit to break down in the main array the first address information and
It is stored with the second address information that error coded corrects the storage unit of redundant digit to break down.
Repair module 302, it is described superfluous for first address information and second address information to be respectively mapped to
The address information of remaining resource repairs the chip.
In conclusion in the embodiment of the present invention, when checking chip, the storage unit in main array is not only checked
Whether break down, also checks for whether the storage unit in ECC area breaks down.If existing in main array and ECC area
When the storage unit to break down, obtain respectively break down in main array access unit address information (facilitate statement and
Distinguish, hereinafter referred to as the first address information) and ECC area in the access unit address information that breaks down (facilitate statement and area
Point, hereinafter referred to as the second address information), and the first address information and the second address information be respectively mapped to the address of redundant resource
Information realizes the reparation to chip.
The above-mentioned repair process to chip can simultaneously repair main array and ECC area, and improve chip can
By property, and then improve product yield.
By the address information of the second mapping address information to redundant resource, redundant resource is taken full advantage of, improves chip
The utilization rate of resource.
Example IV
The embodiment of the present invention four provides a kind of chip prosthetic device.
Chip in the embodiment of the present invention can be made of main array, ECC area and redundant resource, and the embodiment of the present invention
In chip may include Nor Flash.
With reference to Fig. 6, a kind of chip prosthetic device structure chart in the embodiment of the present invention four is shown.
Described device may include：Acquisition module 400 and repair module 402.
Wherein, the acquisition module 400 may include：
Submodule 4001 is arranged in enable signal, accesses submodule 4002, and, traverse submodule 4003.
The relationship between each module, the function of each submodule and each module, each submodule is discussed in detail separately below.
Acquisition module 400, for obtain the storage unit to break down in the main array the first address information and
It is stored with the second address information that error coded corrects the storage unit of redundant digit to break down.
Preferably, second address information may include：Positioned at the error coded correct region, and with the main battle array
The information of the adjacent address of page address of row.
Preferably, the acquisition module 400 may include：
Submodule 4001 is arranged in enable signal, and the initial address for the page address from the main array is incrementally accessed to knot
After beam address, it is effective status that the error coded, which is arranged, to correct the enable signal in region.
Submodule 4002 is accessed, the ground in region is corrected for accessing the error coded adjacent with the page address of main array
Location obtains second address information.
Wherein, when the enable signal is effective status, after the page address for accessing the main array, continue access and institute
State the address in the adjacent error coded correction region of page address of main array；When the enable signal is invalid state, institute is accessed
After the page address for stating main array, next group of page address of the main array is accessed.
Preferably, second address information can also be made of the information of n bit data address；The bit data
Address is and in n address being sequentially located in the page address of the main array, to store main number of arrays positioned at the main array
According to address next address.
Wherein, n is positive integer；N address in the page address includes multiple bit data addresses.
Preferably, the acquisition module 400 can also include：
Submodule 4003 is traversed, the page address for traversing the main array obtains n ground in the page address successively
The information of m-th of address in location obtains second address information, and n and m are positive integer.
Repair module 402, it is described superfluous for first address information and second address information to be respectively mapped to
The address information of remaining resource repairs the chip.
In conclusion in the embodiment of the present invention, when checking chip, the storage unit in main array is not only checked
Whether break down, also checks for whether the storage unit in ECC area breaks down.If existing in main array and ECC area
When the storage unit to break down, obtain respectively break down in main array access unit address information (facilitate statement and
Distinguish, hereinafter referred to as the first address information) and ECC area in the access unit address information that breaks down (facilitate statement and area
Point, hereinafter referred to as the second address information), and the first address information and the second address information be respectively mapped to the address of redundant resource
Information realizes the reparation to chip.
The above-mentioned repair process to chip can simultaneously repair main array and ECC area, and improve chip can
By property, and then improve product yield.
Redundancy reparation is combined with ECC error correction mechanism so that the degree of freedom of redundancy reparation greatly improves, by the second address
Information MAP takes full advantage of redundant resource to the address information of redundant resource, improves the reliability and core of ECC area numeric field data
The utilization rate of piece resource.
For device embodiments, since it is basically similar to the method embodiment, so fairly simple, the correlation of description
Place illustrates referring to the part of embodiment of the method.
For embodiment of the method above-mentioned, for simple description, therefore it is all expressed as a series of combination of actions, still
Those skilled in the art should understand that the present invention is not limited by the described action sequence, because according to the present invention, it is certain
Step can be performed in other orders or simultaneously.Next, those skilled in the art should also know that, it is described in the specification
Embodiment belong to preferred embodiment, involved action and module are not necessarily essential to the invention.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with
The difference of other embodiment, the same or similar parts between the embodiments can be referred to each other.
It is provided for the embodiments of the invention a kind of chip restorative procedure and device above, is described in detail, herein
In apply specific case principle and implementation of the present invention are described, the explanation of above example is only intended to sides
Assistant solves the method and its core concept of the present invention；Meanwhile for those of ordinary skill in the art, think of according to the present invention
Think, there will be changes in the specific implementation manner and application range, in conclusion the content of the present specification should not be construed as pair
The limitation of the present invention.
Claims (10)
1. a kind of chip restorative procedure, which is characterized in that the chip includes main array, error coded corrects region and redundancy provides
Source, the method includes：
The first address information of the storage unit to break down in the main array is obtained respectively and is stored with error coded entangles
Second address information of the storage unit of positive redundant digit to break down；
First address information and second address information are respectively mapped to the address information of the redundant resource, to institute
Chip is stated to be repaired；
Wherein, second address information is made of the information of n bit data address；The bit data address is positioned at institute
In the n address stated main array, and be sequentially located in the page address of the main array, under the address for storing main array data
One address；Wherein, n is positive integer；N address in the page address includes multiple bit data addresses.
2. according to the method described in claim 1, it is characterized in that, second address information includes：It is compiled positioned at the mistake
Code corrects region, and the information of the address adjacent with the page address of main array.
3. according to the method described in claim 2, it is characterized in that, the acquisition is stored with the hair that error coded corrects redundant digit
Second address information of the storage unit of raw failure, including：
It is incrementally accessed from the initial address of the page address of the main array to end address, the error coded is set and is corrected
The enable signal in region is effective status；
The address that the error coded adjacent with the page address of main array corrects region is accessed, the second address letter is obtained
Breath；
Wherein, when the enable signal is effective status, after the page address for accessing the main array, continue to access and the master
The address in the adjacent error coded correction region of page address of array；When the enable signal is invalid state, the master is accessed
After the page address of array, next group of page address of the main array is accessed.
4. according to the method described in claim 1, it is characterized in that, the acquisition is stored with the hair that error coded corrects redundant digit
Second address information of the storage unit of raw failure, including：
The page address for traversing the main array obtains the information of m-th of address in n address in the page address successively,
Second address information is obtained, n and m are positive integer.
5. according to the method described in claim 1, it is characterized in that, the chip includes Nor Flash.
6. a kind of chip prosthetic device, which is characterized in that the chip includes main array, error coded corrects region and redundancy provides
Source, described device include：
Acquisition module, the first address information and storage for obtaining the storage unit to break down in the main array are wrong
Accidentally coding corrects the second address information of the storage unit of redundant digit to break down；
Repair module, for first address information and second address information to be respectively mapped to the redundant resource
Address information repairs the chip；
Wherein, second address information is made of the information of n bit data address；The bit data address is positioned at institute
In the n address stated main array, and be sequentially located in the page address of the main array, under the address for storing main array data
One address；Wherein, n is positive integer；N address in the page address includes multiple bit data addresses.
7. device according to claim 6, which is characterized in that second address information includes：It is compiled positioned at the mistake
Code corrects region, and the information of the address adjacent with the page address of main array.
8. device according to claim 7, which is characterized in that the acquisition module, including：
Enable signal be arranged submodule, the initial address for the page address from the main array incrementally access to end address it
Afterwards, it is effective status that the error coded, which is arranged, to correct the enable signal in region；
Submodule is accessed, the address in region is corrected for accessing the error coded adjacent with the page address of main array, is obtained
Second address information；
Wherein, when the enable signal is effective status, after the page address for accessing the main array, continue to access and the master
The address in the adjacent error coded correction region of page address of array；When the enable signal is invalid state, the master is accessed
After the page address of array, next group of page address of the main array is accessed.
9. device according to claim 7, which is characterized in that the acquisition module, including：
Submodule is traversed, the page address for traversing the main array obtains the in n address in the page address successively
The information of m address obtains second address information, and n and m are positive integer.
10. device according to claim 6, which is characterized in that the chip includes Nor Flash.
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| CN201410262145.9A CN105206307B (en) | 2014-06-12 | 2014-06-12 | A kind of chip restorative procedure and device |
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| CN201410262145.9A CN105206307B (en) | 2014-06-12 | 2014-06-12 | A kind of chip restorative procedure and device |
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| CN105206307B true CN105206307B (en) | 2018-08-21 |
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| KR102650154B1 (en) * | 2016-12-08 | 2024-03-22 | 삼성전자주식회사 | Memory device comprising virtual fail generator and memory cell repair method thereof |
| CN107240421B (en) * | 2017-05-19 | 2020-09-01 | 上海华虹宏力半导体制造有限公司 | Memory test method and device, storage medium and test terminal |
| CN109698008B (en) * | 2017-10-23 | 2021-01-15 | 北京兆易创新科技股份有限公司 | Method and device for repairing NOR type memory bit line fault |
| CN110349617B (en) * | 2019-07-16 | 2024-09-17 | 中国科学院微电子研究所 | A memory |
| KR102657760B1 (en) * | 2019-09-23 | 2024-04-17 | 에스케이하이닉스 주식회사 | Memory system and method of operating the memory system |
| CN116343883A (en) * | 2021-12-22 | 2023-06-27 | 浙江驰拓科技有限公司 | A memory and memory repair method |
| CN114297005A (en) * | 2021-12-29 | 2022-04-08 | 成都博尔微晶科技有限公司 | Small-area and repeated row redundancy replacement method for Norflash |
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| CN101477480A (en) * | 2009-02-05 | 2009-07-08 | 华为技术有限公司 | Memory control method, apparatus and memory read-write system |
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| US7702831B2 (en) * | 2000-01-06 | 2010-04-20 | Super Talent Electronics, Inc. | Flash memory controller for electronic data flash card |
| US6807106B2 (en) * | 2001-12-14 | 2004-10-19 | Sandisk Corporation | Hybrid density memory card |
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| CN1153984A (en) * | 1994-11-17 | 1997-07-09 | 三星电子株式会社 | Redundant circuit of semiconductor memory device and method thereof |
| CN101477480A (en) * | 2009-02-05 | 2009-07-08 | 华为技术有限公司 | Memory control method, apparatus and memory read-write system |
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