CN105187078B - The digital display circuit and its implementation that a kind of low intermediate frequency receiver mirror image suppresses - Google Patents

Abstract

The invention discloses the digital display circuit and its implementation that a kind of low intermediate frequency receiver mirror image suppresses, digital display circuit includes direct current computing module, the first subtracter, conjugation computing module, power computation module, adaptive-filtering computing module and plural bandpass filtering modules block；Direct current computing module receives I, Q two paths of data and exports I0, Q0 data, first subtracter receives I, Q two paths of data and I0, Q0 data obtain I1, Q1 data, conjugation computing module receives I1, Q1 data and obtains I2, Q2 data, power computation module receives I1, Q1 data and obtains IQ_POW data, sef-adapting filter computing module receives I1, Q1, I2, Q2 and IQ_POW data and obtains I4, Q4 data, and complex filter module receives I4, Q4 data and obtains I5, Q5 data.The digital systems architecture of the present invention is relatively easy but improvement that IQ mismatches can be made significantly to be stablized.

Description

Digital system for image rejection of low-intermediate frequency receiver and implementation method thereof

Technical Field

The present invention relates to the field of wireless communications technologies, and in particular, to a digital system suitable for, but not limited to, image rejection in a low-if receiver.

Background

The radio frequency part of modern digital wireless communication receiver systems typically includes the following analog circuitry: band pass filter, mixer, low pass filter, gain control (AGC), analog to digital converter (ADC). When the system uses the modulation scheme of in-phase (I) and quadrature (Q) signals, then we need to generate I and Q signals respectively from the modulation signal near the high frequency carrier at the rf end by mixing and filtering (as shown in fig. 1). In an ideal IQ signal, the signal amplitudes are identical and the phases are 90 degrees apart (as shown in fig. 2). However, when the analog circuit is implemented on a chip, the I and Q signals are unbalanced or mismatched due to the IQ link corresponding to different physical positions and process deviations, especially errors of the mixer, so that the complex signal synthesized by the I/Q signals has an image frequency (as shown in fig. 3). In the receiver with the low intermediate frequency architecture, if different modulation signals are respectively arranged at positive and negative intermediate frequencies, when a high-frequency signal is mixed to the intermediate frequency through a mismatched mixer, corresponding image frequency and an original signal are superposed at the positive and negative intermediate frequencies. If the mismatch is severe, the communication quality will be severely affected. Therefore, a corresponding technique is needed to suppress the mirror frequency generated by the IQ mismatch, i.e., compensate the mismatch of the IQ signal.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention aims to provide a simple and feasible fully-digital IQ mismatch compensation and image rejection system with obvious effect.

In order to solve the problems, the technical scheme adopted by the invention is as follows:

the first scheme is as follows:

a digital system for image rejection in a low intermediate frequency receiver, comprising: the device comprises a direct current calculation module, a first subtracter, a conjugate calculation module, a power calculation module, an adaptive filtering calculation module and a complex band-pass filtering module; the direct current calculation module receives I, Q two paths of data for direct current calculation and outputs I0 data and Q0 data to a first subtracter, I, Q two paths of data are total input of the system, the first subtracter receives I path data and subtracts I0 data output by the direct current calculation module to obtain I1 data, the first subtracter receives Q path data and subtracts Q0 data output by the direct current calculation module to obtain Q1 data, the conjugate calculation module receives I1 data and Q1 data and performs conjugate calculation to obtain I2 data and Q2 data, the power calculation module receives I1 data and Q1 data and performs power calculation to obtain IQ _ POW data, the adaptive filter calculation module receives I1 data, Q1 data, I2 data, Q2 data and IQ _ POW data and performs filtering calculation to obtain I4 and Q4 data after image rejection filtering, the complex filter module receives I4 and Q4 data and performs complex band-pass filtering to obtain I5 and Q5 data, the I5 and Q5 data are the total output of the system.

Preferably, the adaptive filtering calculation module includes: a first register, a second register, a third register, a fourth register, a fifth register, a sixth register, a seventh register, an eighth register, a ninth register, a tenth register, an eleventh register, a twelfth register, a thirteenth register, a fourteenth register, a fifteenth register, a sixteenth register, a seventeenth register, an eighteenth register, a nineteenth register, a twentieth register, a twenty-first register, a twenty-second register, a twenty-third register, a twenty-fourth register, a first multiplexer, a second multiplexer, a third multiplexer, a fourth multiplexer, a fifth multiplexer, a sixth multiplexer, a seventh multiplexer, an eighth multiplexer, a ninth multiplexer, a tenth multiplexer, an eleventh multiplexer, a fifteenth multiplexer, A sixteenth multiplexer, a first complex multiplier, a second complex multiplier, a first adder, a second subtractor, a third subtractor, a first divider, a second decoder, a third decoder, a fourth decoder and a step coefficient module; the first register, the second register and the third register form a shift register chain and are respectively used for storing currently received I2 data, last received I2 data and last received I2 data, and the fourth register, the fifth register and the sixth register also form a shift register chain and are respectively used for storing currently received Q2 data, last received Q2 data and last received Q2 data;

the filtering calculation process includes 4 clock cycles, which are respectively marked as cyc1, cyc2, cyc3 and cyc4, and a calculation cycle is composed of the 4 clock cycles, and the specific calculation cycle process is as follows:

in cyc1, data in a first register and a fourth register are respectively input into a first complex multiplier through a first multiplexer and a second multiplexer, data in a twentieth register and a seventeenth register are respectively input into the first complex multiplier through a seventh multiplexer and a sixth multiplexer, the first complex multiplier obtains a Q-path operation result through operation and inputs the Q-path operation result into a first adder, the first complex multiplier obtains an I-path operation result through operation and inputs the I-path operation result into a second adder, the tenth multiplexer inputs Q1 data into the first adder, the eleventh multiplexer inputs I1 data into the second adder, the operation result of the first adder is stored in the seventh register, and the operation result of the second adder is stored in an eighth register; the third multiplexer and the fourth multiplexer respectively input data in the ninth register and the twelfth register into a second complex multiplier, data in the fifteenth register and the sixteenth register are input into a second complex multiplier, the second complex multiplier operates to obtain an I-path operation result and stores the I-path operation result in a twenty-third register, and the second complex multiplier operates to obtain a Q-path operation result and stores the Q-path operation result in a twenty-fourth register;

in cyc2, the data in the second register and the fifth register are input to the first complex multiplier through the first multiplexer and the second multiplexer, respectively, the data in the twenty-first register and the eighteenth register are respectively input into the first complex multiplier through the seventh multiplexer and the sixth multiplexer, the first complex multiplier obtains Q-path operation results through operation and inputs the Q-path operation results into the first adder, the first complex multiplier obtains I-path operation results through operation and inputs the I-path operation results into the second adder, the tenth multiplexer inputs data in the seventh register into the first adder, the eleventh multiplexer inputs data in the eighth register into the second adder, the operation results of the first adder are stored in the seventh register, and the operation results of the second adder are stored in the eighth register; the third multiplexer and the fourth multiplexer input the data in the ninth register and the twelfth register into the second complex multiplier respectively, the data in the fifteenth register and the sixteenth register are input into a second complex multiplier, the second complex multiplier obtains an I-path operation result through operation and inputs the I-path operation result into a third subtracter, the second complex multiplier obtains a Q-path operation result through operation and inputs the Q-path operation result into the second subtracter, a sixteenth multiplexer inputs the data in the twentieth register into the third subtracter to subtract the I-path operation result, a fifteenth multiplexer inputs the data in the seventeenth register into the second subtracter to subtract the Q-path operation result, the operation result of the third subtracter is stored in a twentieth register through a third decoder, and the operation result of the second subtracter is stored in a seventeenth register through the second decoder; the fifth multiplexer inputs the data obtained by operation in cyc1 and stored in the twenty-third register into the first divider as a dividend, the step coefficient in the step coefficient module is input into the first divider as the dividend, and the operation result of the first divider is stored in the twenty-third register through the fourth decoder and the eighth multiplexer;

in cyc3, the data in the third register and the sixth register are input to the first complex multiplier through the first multiplexer and the second multiplexer, respectively, the data in the twenty-second register and the nineteenth register are input into the first complex multiplier through the seventh multiplexer and the sixth multiplexer respectively, the first complex multiplier obtains Q-path operation results through operation and inputs the Q-path operation results into the first adder, the first complex multiplier obtains I-path operation results through operation and inputs the I-path operation results into the second adder, the tenth multiplexer inputs data in the seventh register into the first adder, the eleventh multiplexer inputs data in the eighth register into the second adder, the operation results of the first adder are stored in the seventh register, and the operation results of the second adder are stored in the eighth register; the third multiplexer and the fourth multiplexer input the data in the tenth register and the thirteenth register to the second complex multiplier, the data in the fifteenth register and the sixteenth register are input into a second complex multiplier, the I-path operation result obtained by the operation of the second complex multiplier is input into a third subtracter, the Q-path operation result obtained by the operation of the second complex multiplier is input into the second subtracter, the data in the twenty-first register is input into the third subtracter to be subtracted from the I-path operation result by a sixteenth multiplexer, the data in the eighteenth register is input into the second subtracter to be subtracted from the Q-path operation result by a fifteenth multiplexer, the operation result of the third subtracter is stored in the twenty-first register through a third decoder, and the operation result of the second subtracter is stored in the eighteenth register through the second decoder; the fifth multiplexer inputs the data obtained by operation in cyc1 and stored in the twenty-fourth register into the first divider as a dividend, the step coefficient in the step coefficient module is input into the first divider as the dividend, and the operation result of the first divider is stored in the twenty-fourth register through the fourth decoder and the ninth multiplexer;

in cyc4, the third multiplexer and the fourth multiplexer input data in the eleventh register and the fourteenth register to the second complex multiplier, data in the fifteenth register and the sixteenth register to the second complex multiplier, the second complex multiplier operates to obtain an I-path operation result and inputs the I-path operation result to the third subtractor, the second complex multiplier operates to obtain a Q-path operation result and inputs the Q-path operation result to the second subtractor, the sixteenth multiplexer inputs data in the twenty-second register to the third subtractor and subtracts the I-path operation result, the fifteenth multiplexer inputs data in the nineteenth register to the second subtractor and subtracts the Q-path operation result, the operation result of the third subtractor is stored in the twenty-second register through the third decoder, and the operation result of the second subtractor is stored in the nineteenth register through the second decoder;

then, data in the tenth register is shifted into the eleventh register, data in the ninth register is shifted into the tenth register, data in the eighth register is stored in the ninth register, and the data in the eighth register is I4 data output by the adaptive filtering calculation module; shifting the data in the thirteenth register to the fourteenth register, shifting the data in the twelfth register to the thirteenth register, saving the data in the seventh register in the twelfth register, and outputting the data in the seventh register as Q4 data by the adaptive filtering calculation module; shifting the data in the second register into a third register, shifting the data in the first register into the second register, reading in new I2 data by the first register, shifting the data in the fifth register into a sixth register, shifting the data in the fourth register into the fifth register, and reading in new Q2 data by the fourth register; the data in the twenty-third register is saved into the fifteenth register, and the data in the twenty-fourth register is saved into the sixteenth register.

Preferably, the step coefficient module receives the IQ _ POW data, and performs fixed scaling on the IQ _ POW data to obtain a step coefficient meeting the convergence rate and the filtering performance.

Preferably, the dc calculating module includes a thirteenth multiplexer, a first multiplier, a third adder, a second multiplier, a fourteenth multiplexer, a twenty-fifth register, a twenty-sixth register, and a fifth decoder; the operation process of the direct current calculation module is as follows:

firstly, a thirteenth multiplexer selects total input I-path data to input into a first multiplier, the result obtained by multiplying the data input by the thirteenth multiplexer by the fixed coefficient dc _ a1 read by the first multiplier is input into a third adder, the I0 data obtained by the last direct current calculation is currently stored in a twenty-fifth register, the data in the twenty-fifth register is input into a second multiplier by a fourteenth multiplexer, the result obtained by multiplying the data input by the fourteenth multiplexer by the fixed coefficient dc _ b1 read by the second multiplier is input into the third adder, and the result obtained by adding by the third adder is input into the twenty-fifth register through a fifth decoder and is used as the I0 data output by a direct current calculation module; then, the thirteenth multiplexer selects Q paths of data of the total input to input the Q paths of data into the first multiplier, the result obtained by multiplying the data input by the thirteenth multiplexer by the fixed coefficient dc _ a1 read by the first multiplier is input into the third adder, the Q0 data obtained by the last direct current calculation is currently stored in the twenty-sixth register, the fourteenth multiplexer inputs the data in the twenty-sixth register into the second multiplier, the result obtained by multiplying the data input by the fourteenth multiplexer by the fixed coefficient dc _ b1 read by the second multiplier is input into the third adder, and the result obtained by adding by the third adder is input into the twenty-sixth register through the fifth decoder and is used as the Q0 data output by the direct current calculation module.

Preferably, the power calculation module comprises a third multiplier, a fourth adder, a fifth multiplier, a sixth multiplier, a fifth adder and a twenty-seventh register; the operation process of the power calculation module is as follows:

the third multiplier reads the I1 data and performs the square operation of the I1 data and inputs it to the fourth adder, the fourth multiplier reads the Q1 data and performs the square operation of the Q1 data and inputs it to the fourth adder, the fourth adder adds the data output from the third multiplier and the fourth multiplier and inputs the result to the fifth multiplier, the fifth multiplier reads the fixed coefficient pow _ a1 to multiply the data output from the fourth adder and inputs the result to the fifth adder, the IQ _ POW data obtained by last power calculation is currently stored in the twenty-seventh register, the IQ _ POW data currently stored in the twenty-seventh register is read by the sixth multiplier, multiplied by the read fixed coefficient POW _ b1 and input into the fifth adder, the data output by the fifth multiplier and the data output by the sixth multiplier are added by the fifth adder, the obtained result is stored in a twenty-seventh register and is used as IQ _ POW data output by the power calculation module.

Scheme II:

a digital system for image rejection of a low-intermediate frequency receiver is provided, wherein the digital system comprises a direct current calculation module, a first subtracter, a conjugate calculation module, a power calculation module, a self-adaptive filtering calculation module and a complex band-pass filtering module; the method comprises the following steps:

the direct current calculation module receives I, Q paths of data to perform direct current calculation and outputs I0 data and Q0 data to the first subtracter, wherein I, Q paths of data are the total input of the system;

the first subtracter receives I-path data and subtracts I0 data output by the direct current calculation module to obtain I1 data, and the first subtracter receives Q-path data and subtracts Q0 data output by the direct current calculation module to obtain Q1 data;

the conjugate calculation module receives the I1 data and the Q1 data to carry out conjugate calculation to obtain I2 data and Q2 data;

the power calculation module receives the I1 data and the Q1 data to carry out power calculation to obtain IQ _ POW data;

the adaptive filter calculation module receives I1 data, Q1 data, I2 data, Q2 data and IQ _ POW data, and performs filtering calculation to obtain I4 and Q4 data after image rejection filtering;

the complex filtering module receives the I4 and Q4 data and carries out complex band-pass filtering to obtain I5 and Q5 data, and the I5 and Q5 data are the total output of the system.

Preferably, the adaptive filtering calculation module includes: a first register, a second register, a third register, a fourth register, a fifth register, a sixth register, a seventh register, an eighth register, a ninth register, a tenth register, an eleventh register, a twelfth register, a thirteenth register, a fourteenth register, a fifteenth register, a sixteenth register, a seventeenth register, an eighteenth register, a nineteenth register, a twentieth register, a twenty-first register, a twenty-second register, a twenty-third register, a twenty-fourth register, a first multiplexer, a second multiplexer, a third multiplexer, a fourth multiplexer, a fifth multiplexer, a sixth multiplexer, a seventh multiplexer, an eighth multiplexer, a ninth multiplexer, a tenth multiplexer, an eleventh multiplexer, a fifteenth multiplexer, A sixteenth multiplexer, a first complex multiplier, a second complex multiplier, a first adder, a second subtractor, a third subtractor, a first divider, a second decoder, a third decoder, a fourth decoder and a step coefficient module; the first register, the second register and the third register form a shift register chain and are respectively used for storing currently received I2 data, last received I2 data and last received I2 data, and the fourth register, the fifth register and the sixth register also form a shift register chain and are respectively used for storing currently received Q2 data, last received Q2 data and last received Q2 data;

the calculation process of the adaptive filtering calculation module includes 4 clock cycles, which are respectively marked as cyc1, cyc2, cyc3 and cyc4, and a calculation cycle is composed of 4 clock cycles, and the step of executing one calculation cycle is as follows:

in cyc1, data in a first register and a fourth register are respectively input into a first complex multiplier through a first multiplexer and a second multiplexer, data in a twentieth register and a seventeenth register are respectively input into the first complex multiplier through a seventh multiplexer and a sixth multiplexer, the first complex multiplier obtains a Q-path operation result through operation and inputs the Q-path operation result into a first adder, the first complex multiplier obtains an I-path operation result through operation and inputs the I-path operation result into a second adder, the tenth multiplexer inputs Q1 data into the first adder, the eleventh multiplexer inputs I1 data into the second adder, the operation result of the first adder is stored in the seventh register, and the operation result of the second adder is stored in an eighth register; the third multiplexer and the fourth multiplexer respectively input data in the ninth register and the twelfth register into a second complex multiplier, data in the fifteenth register and the sixteenth register are input into a second complex multiplier, the second complex multiplier operates to obtain an I-path operation result and stores the I-path operation result in a twenty-third register, and the second complex multiplier operates to obtain a Q-path operation result and stores the Q-path operation result in a twenty-fourth register;

in cyc2, the data in the second register and the fifth register are input to the first complex multiplier through the first multiplexer and the second multiplexer, respectively, the data in the twenty-first register and the eighteenth register are respectively input into the first complex multiplier through the seventh multiplexer and the sixth multiplexer, the first complex multiplier obtains Q-path operation results through operation and inputs the Q-path operation results into the first adder, the first complex multiplier obtains I-path operation results through operation and inputs the I-path operation results into the second adder, the tenth multiplexer inputs data in the seventh register into the first adder, the eleventh multiplexer inputs data in the eighth register into the second adder, the operation results of the first adder are stored in the seventh register, and the operation results of the second adder are stored in the eighth register; the third multiplexer and the fourth multiplexer input the data in the ninth register and the twelfth register into the second complex multiplier respectively, the data in the fifteenth register and the sixteenth register are input into a second complex multiplier, the second complex multiplier obtains an I-path operation result through operation and inputs the I-path operation result into a third subtracter, the second complex multiplier obtains a Q-path operation result through operation and inputs the Q-path operation result into the second subtracter, a sixteenth multiplexer inputs the data in the twentieth register into the third subtracter to subtract the I-path operation result, a fifteenth multiplexer inputs the data in the seventeenth register into the second subtracter to subtract the Q-path operation result, the operation result of the third subtracter is stored in a twentieth register through a third decoder, and the operation result of the second subtracter is stored in a seventeenth register through the second decoder; the fifth multiplexer inputs the data obtained by operation in cyc1 and stored in the twenty-third register into the first divider as dividend, the step coefficient in the step coefficient module is input into the first divider as divisor, and the operation result of the first divider is stored in the twenty-third register through the fourth decoder and the eighth multiplexer;

in cyc3, the data in the third register and the sixth register are input to the first complex multiplier through the first multiplexer and the second multiplexer, respectively, the data in the twenty-second register and the nineteenth register are input into the first complex multiplier through the seventh multiplexer and the sixth multiplexer respectively, the first complex multiplier obtains Q-path operation results through operation and inputs the Q-path operation results into the first adder, the first complex multiplier obtains I-path operation results through operation and inputs the I-path operation results into the second adder, the tenth multiplexer inputs data in the seventh register into the first adder, the eleventh multiplexer inputs data in the eighth register into the second adder, the operation results of the first adder are stored in the seventh register, and the operation results of the second adder are stored in the eighth register; the third multiplexer and the fourth multiplexer input the data in the tenth register and the thirteenth register to the second complex multiplier, the data in the fifteenth register and the sixteenth register are input into a second complex multiplier, the I-path operation result obtained by the operation of the second complex multiplier is input into a third subtracter, the Q-path operation result obtained by the operation of the second complex multiplier is input into the second subtracter, the data in the twenty-first register is input into the third subtracter to be subtracted from the I-path operation result by a sixteenth multiplexer, the data in the eighteenth register is input into the second subtracter to be subtracted from the Q-path operation result by a fifteenth multiplexer, the operation result of the third subtracter is stored in the twenty-first register through a third decoder, and the operation result of the second subtracter is stored in the eighteenth register through the second decoder; the fifth multiplexer inputs the data obtained by operation in cyc1 and stored in the twenty-fourth register into the first divider as dividend, the step coefficient in the step coefficient module is input into the first divider as divisor, and the operation result of the first divider is stored in the twenty-fourth register through the fourth decoder and the ninth multiplexer;

in cyc4, the third multiplexer and the fourth multiplexer input data in the eleventh register and the fourteenth register to the second complex multiplier, data in the fifteenth register and the sixteenth register to the second complex multiplier, the second complex multiplier operates to obtain an I-path operation result and inputs the I-path operation result to the third subtractor, the second complex multiplier operates to obtain a Q-path operation result and inputs the Q-path operation result to the second subtractor, the sixteenth multiplexer inputs data in the twenty-second register to the third subtractor and subtracts the I-path operation result, the fifteenth multiplexer inputs data in the nineteenth register to the second subtractor and subtracts the Q-path operation result, the operation result of the third subtractor is stored in the twenty-second register through the third decoder, and the operation result of the second subtractor is stored in the nineteenth register through the second decoder;

then, data in the tenth register is shifted into the eleventh register, data in the ninth register is shifted into the tenth register, data in the eighth register is stored in the ninth register, and the data in the eighth register is I4 data output by the adaptive filtering calculation module; shifting the data in the thirteenth register to the fourteenth register, shifting the data in the twelfth register to the thirteenth register, saving the data in the seventh register in the twelfth register, and outputting the data in the seventh register as Q4 data by the adaptive filtering calculation module; shifting the data in the second register into a third register, shifting the data in the first register into the second register, reading in new I2 data by the first register, shifting the data in the fifth register into a sixth register, shifting the data in the fourth register into the fifth register, and reading in new Q2 data by the fourth register; the data in the twenty-third register is saved into the fifteenth register, and the data in the twenty-fourth register is saved into the sixteenth register.

Preferably, the step coefficient module receives the IQ _ POW data, and performs fixed scaling on the IQ _ POW data to obtain a step coefficient meeting the convergence rate and the filtering performance.

Preferably, the dc calculating module includes a thirteenth multiplexer, a first multiplier, a third adder, a second multiplier, a fourteenth multiplexer, a twenty-fifth register, a twenty-sixth register, and a fifth decoder;

the operation steps executed by the direct current calculation module are as follows:

firstly, a thirteenth multiplexer selects total input I-path data to input into a first multiplier, the result obtained by multiplying the data input by the thirteenth multiplexer by the fixed coefficient dc _ a1 read by the first multiplier is input into a third adder, the I0 data obtained by the last direct current calculation is currently stored in a twenty-fifth register, the data in the twenty-fifth register is input into a second multiplier by a fourteenth multiplexer, the result obtained by multiplying the data input by the fourteenth multiplexer by the fixed coefficient dc _ b1 read by the second multiplier is input into the third adder, and the result obtained by adding by the third adder is input into the twenty-fifth register through a fifth decoder and is used as the I0 data output by a direct current calculation module;

then, the thirteenth multiplexer selects Q paths of data of the total input to input the Q paths of data into the first multiplier, the result obtained by multiplying the data input by the thirteenth multiplexer by the fixed coefficient dc _ a1 read by the first multiplier is input into the third adder, the Q0 data obtained by the last direct current calculation is currently stored in the twenty-sixth register, the fourteenth multiplexer inputs the data in the twenty-sixth register into the second multiplier, the result obtained by multiplying the data input by the fourteenth multiplexer by the fixed coefficient dc _ b1 read by the second multiplier is input into the third adder, and the result obtained by adding by the third adder is input into the twenty-sixth register through the fifth decoder and is used as the Q0 data output by the direct current calculation module.

Preferably, the power calculation module comprises a third multiplier, a fourth adder, a fifth multiplier, a sixth multiplier, a fifth adder and a twenty-seventh register;

the calculation steps executed by the power calculation module are as follows:

the third multiplier reads the I1 data and performs the square operation of the I1 data and inputs it to the fourth adder, the fourth multiplier reads the Q1 data and performs the square operation of the Q1 data and inputs it to the fourth adder, the fourth adder adds the data output from the third multiplier and the fourth multiplier and inputs the result to the fifth multiplier, the fifth multiplier reads the fixed coefficient pow _ a1 to multiply the data output from the fourth adder and inputs the result to the fifth adder, the IQ _ POW data obtained by last power calculation is currently stored in the twenty-seventh register, the IQ _ POW data currently stored in the twenty-seventh register is read by the sixth multiplier, multiplied by the read fixed coefficient POW _ b1 and input into the fifth adder, the data output by the fifth multiplier and the data output by the sixth multiplier are added by the fifth adder, the obtained result is stored in a twenty-seventh register and is used as IQ _ POW data output by the power calculation module.

Compared with the prior art, the invention has the beneficial effects that: the digital system has a relatively simple structure, can obviously and stably improve IQ mismatch, and improves the image rejection ratio by 15-25 dB. In addition, the time-sharing multiplexing is adopted for most of the operation units in the system, so that the expenditure of hardware units is further saved, namely the cost is saved.

Drawings

Fig. 1 is a schematic diagram of a low intermediate frequency receiver;

FIG. 2 is a diagram of an ideal low IF signal;

FIG. 3 is a schematic diagram of a mismatched low IF signal;

FIG. 4 is a schematic diagram of the overall architecture of the digital system of the present invention;

FIG. 5 is a schematic structural diagram of a DC calculating module according to the present invention;

FIG. 6 is a schematic diagram of a conjugate computing module according to the present invention;

FIG. 7 is a schematic diagram of a power calculation module according to the present invention;

FIG. 8 is a schematic structural diagram of an adaptive filter calculation module according to the present invention;

fig. 9 is a schematic structural diagram of a complex band-pass filtering module according to the present invention.

Detailed Description

The invention will be further described with reference to the accompanying drawings and the detailed description below:

the IQ mismatch introduced by the mixer can be generally represented using the following model:

x_LO(t)＝cos(ω_LOt)-g*sin(ω_LOt+θ)＝K₁*exp(-jω_LOt)+K₂*exp(jω_LOt)

wherein,

assuming that the ideal baseband signal is d (t), after the rf signal r (t) passes through the mismatched mixer, the resulting mismatched signal can be expressed as:

x(t)＝K₁*d(t)+K₂*d^*(t)

wherein d is^*And (t) is a conjugate signal of d (t). Conversion to the frequency domain, resulting in signal d due to mixer mismatch^*(t) produces a mirror frequency that is symmetrical to the baseband signal. The mirror frequency is the result of IQ mismatch, which is compensated if the mirror frequency is suppressed.

For low IF receivers, at-f_IFAnd f_IFThere are two different signals u (t) and d (t), respectively, assuming d (t) is the signal we need and u (t) is not the signal we need. After the IQ mismatch mixer, two image signals u '(t) and d' (t) are introduced and mixed together with d (t) and u (t), respectively, as shown in fig. 3. If u' (t) is not eliminated, we cannot obtain the ideal baseband signal d (t), which has a certain effect on the communication quality.

The scheme of the invention relates to a QPSK modulation signal, and the compensation scheme is based on the following frequency spectrum characteristics of some QPSK signals.

First, if the autocorrelation function E { d (t) × d of a complex random signal^*(t- τ) } is constant, then we refer to the signal as a generalized stationary signal. Meanwhile, we define E { d (t) × d (t- τ) } as the complementary autocorrelation function of the complex random signal. A complex signal is said to be second order stationary if it is both broadly stationary and its complementary autocorrelation function depends only on the delay τ. If the complex signal satisfies E { d }²(t) } 0, we call the signal cyclic. For a complex signal, if its complementary autocorrelation function is satisfied for an arbitrary delay τWe then say that the signal has a property. It can be seen that the complex random signal with properness is certainly cyclic.

The ideal IQ signal using QPSK modulation in the present invention generally satisfies the requirement of performance. But when there is mismatch, the properness disappears. Therefore, the objective of the algorithm is to recover the proerness characteristic of the received IQ signal in an adaptive manner, thereby suppressing the image rejection.

Looking again at the expression for mismatched IQ signals: x (t) ═ K₁*d(t)+K₂*d^*(t), which in fact satisfies the form of a wide linear (wide linear) signal model. Therefore, the present invention contemplates the use of a wide linear model compensator structure to solve the mismatch problem.

The general structure of the wide linear compensator is shown in the following expression:

where x (N) ═ x (N) x (N-1) x (N-2.. x (N-N +1)]^TFor mismatched IQ signals, N is the order of the compensator filter, w ═ w (0) w (1) w (2.. w (N-1)]^TAre compensator filter coefficients.

For the purposes of the present invention, we intend to convert d^*(n) removed, thereby making it possible to remove w₁Simplified as w₁This does not have a significant effect on the design effect, 1. The compensator is simplified into y (n) ═ x (n) + w^T*x^*(n)。

In order to restore the performance characteristic to the output y (n), i.e. E { y (n) y (n) } is required to be 0, w can be directly obtained by the following recursion relation:

w (N) ═ w (N-1) - λ y (N) y (N), where y (N) ═ y (N) y (N-1.. y (N-N +1)]^T。

Through tests, when the order of the filter is 3, the obtained effect meets the specification requirement of a receiver, so that the invention adopts the structure of the 3-order filter.

The foregoing is the fundamental basis for the design of the digital system of the present invention, and the following is a detailed description of the architecture and implementation of the digital system of the present invention.

Referring to fig. 1, the architecture of the digital system for image rejection of a low if receiver of the present invention comprises: the device comprises a direct current calculation module, a first subtracter, a conjugate calculation module, a power calculation module, an adaptive filtering calculation module and a complex band-pass filtering module. The total input of the system is I-path data and Q-path data, the direct current calculation module receives I, Q-path data to perform direct current calculation and outputs I0 data and Q0 data to the first subtracter. The first subtracter receives I-path data and subtracts I0 data output by the direct current calculation module to obtain I1 data, the first subtracter receives Q-path data and subtracts Q0 data output by the direct current calculation module to obtain Q1 data, and the I1 data and the Q1 data output by the first subtracter are actually direct current-removed I-path data and direct current-removed Q-path data. And the conjugate calculation module receives the I1 data and the Q1 data to carry out conjugate calculation to obtain I2 data and Q2 data. The power calculation module receives the I1 data and the Q1 data to calculate average power to obtain IQ _ POW data. The adaptive filter calculation module receives the I1 data, the Q1 data, the I2 data, the Q2 data and the IQ _ POW data, and performs filtering calculation to obtain image rejection filtered I4 and Q4 data. The complex filtering module receives the I4 and Q4 data and carries out complex band-pass filtering to obtain I5 and Q5 data, and the I5 and Q5 data are the total output of the system. The above description is the basic data processing circuit in the system, and the specific data processing mode in each processing module is further described below.

Fig. 2 is a block diagram of a dc computing module. The direct current calculation module comprises: the circuit comprises a thirteenth multiplexer, a first multiplier, a third adder, a second multiplier, a fourteenth multiplexer, a twenty-fifth register, a twenty-sixth register and a fifth decoder. The operation process of the direct current calculation module is as follows:

firstly, the thirteenth multiplexer selects total input I-path data and inputs the total input I-path data into the first multiplier, the result obtained by multiplying the data input by the thirteenth multiplexer by the fixed coefficient dc _ a1 read by the first multiplier is input into the third adder, the I0 data obtained by the last direct current calculation is currently stored in the twenty-fifth register, the fourteenth multiplexer inputs the data in the twenty-fifth register into the second multiplier, the result obtained by multiplying the data input by the fourteenth multiplexer by the fixed coefficient dc _ b1 read by the second multiplier is input into the third adder, and the result obtained by adding by the third adder is input into the twenty-fifth register through the fifth decoder and is used as the I0 data output by the direct current calculation module.

Then, the thirteenth multiplexer selects Q paths of data of the total input to input the Q paths of data into the first multiplier, the result obtained by multiplying the data input by the thirteenth multiplexer by the fixed coefficient dc _ a1 read by the first multiplier is input into the third adder, the Q0 data obtained by the last direct current calculation is currently stored in the twenty-sixth register, the fourteenth multiplexer inputs the data in the twenty-sixth register into the second multiplier, the result obtained by multiplying the data input by the fourteenth multiplexer by the fixed coefficient dc _ b1 read by the second multiplier is input into the third adder, and the result obtained by adding by the third adder is input into the twenty-sixth register through the fifth decoder and is used as the Q0 data output by the direct current calculation module. Among them, the fixed coefficient dc _ a1 and the fixed coefficient dc _ b1 are configured empirically by a skilled person.

Referring to fig. 3, a block diagram of a power calculation module for outputting IQ _ POW data approximate to an average power is shown. The module includes: a third multiplier, a fourth adder, a fifth multiplier, a sixth multiplier, a fifth adder and a twenty-seventh register.

The operation process of the power calculation module is as follows:

the third multiplier reads the I1 data and performs the square operation of the I1 data and inputs it to the fourth adder, the fourth multiplier reads the Q1 data and performs the square operation of the Q1 data and inputs it to the fourth adder, the fourth adder adds the data output from the third multiplier and the fourth multiplier and inputs the result to the fifth multiplier, the fifth multiplier reads the fixed coefficient pow _ a1 to multiply the data output from the fourth adder and inputs the result to the fifth adder, the IQ _ POW data obtained by last power calculation is currently stored in the twenty-seventh register, the IQ _ POW data currently stored in the twenty-seventh register is read by the sixth multiplier, multiplied by the read fixed coefficient POW _ b1 and input into the fifth adder, the data output by the fifth multiplier and the data output by the sixth multiplier are added by the fifth adder, the obtained result is stored in a twenty-seventh register and is used as IQ _ POW data output by the power calculation module. Among them, the fixed coefficient pow _ a1 and the fixed coefficient pow _ b1 are configured empirically by a skilled person.

Referring to fig. 4, a block diagram of a conjugate calculation module is shown, which is used to perform an inversion operation on input Q1 data, I1 data is unchanged, and actually, I2 data output by the module is I1 data, and Q2 data is-Q1 data.

Referring to fig. 5, a structure diagram of an adaptive filtering computation module is shown, where the structure in the module adopts third-order filtering and has four clock cycles, which are respectively denoted as cyc1, cyc2, cyc3, and cyc4, and the four clock cycles constitute one computation cycle, so that the internal clock of the module is 4 times the external I, Q data sampling rate, that is, I, Q data is input once from the outside, and the inside of the module needs to complete four clock cycles of computation, and then outputs processed I, Q data. The adaptive filtering calculation module specifically includes: a first register, a second register, a third register, a fourth register, a fifth register, a sixth register, a seventh register, an eighth register, a ninth register, a tenth register, an eleventh register, a twelfth register, a thirteenth register, a fourteenth register, a fifteenth register, a sixteenth register, a seventeenth register, an eighteenth register, a nineteenth register, a twentieth register, a twenty-first register, a twenty-second register, a twenty-third register, a twenty-fourth register, a first multiplexer, a second multiplexer, a third multiplexer, a fourth multiplexer, a fifth multiplexer, a sixth multiplexer, a seventh multiplexer, an eighth multiplexer, a ninth multiplexer, a tenth multiplexer, an eleventh multiplexer, a fifteenth multiplexer, The system comprises a sixteenth multiplexer, a first complex multiplier, a second complex multiplier, a first adder, a second subtractor, a third subtractor, a first divider, a second decoder, a third decoder, a fourth decoder and a stepping coefficient module.

The first register, the second register and the third register form a shift register chain and are respectively used for storing currently received I2 data, last received I2 data and last received I2 data, and the fourth register, the fifth register and the sixth register also form a shift register chain and are respectively used for storing currently received Q2 data, last received Q2 data and last received Q2 data. The ninth, tenth and eleventh registers also form a shift register chain, and the twelfth, thirteenth and fourteenth registers also form a shift register chain.

The four clock cycles in a computation cycle work as follows:

in cyc 1:

the data in the first register and the data in the fourth register are respectively input into a first complex multiplier through a first multiplexer and a second multiplexer, the data in the twentieth register and the seventeenth register are respectively input into the first complex multiplier through a seventh multiplexer and a sixth multiplexer, the first complex multiplier obtains a Q-path operation result through operation and inputs the Q-path operation result into a first adder, the first complex multiplier obtains an I-path operation result through operation and inputs the I-path operation result into a second adder, the tenth multiplexer inputs Q1 data into the first adder, the eleventh multiplexer inputs I1 data into the second adder, the operation result of the first adder is stored in the seventh register, and the operation result of the second adder is stored in an eighth register.

In order to simplify the calculation, when calculating the recursion w (n) ═ w (n-1) - λ y (n) y (n), the recursion may be adjusted so that w (n) ═ w (n-1) - λ y (n) y (n) is obtained, and in the actual calculation, λ y (n) is calculatedIs the coefficient related to the average power: lambda is lambda'/P_avg. The recursive calculation is performed in the second complex multiplier, and the fifteenth register stores λ y (n) related to the I-path data obtained in the previous calculation cycle, and the sixteenth register stores λ y (n) related to the Q-path data obtained in the previous calculation cycle. The third multiplexer and the fourth multiplexer input data in the ninth register and the twelfth register into the second complex multiplier respectively, data in the fifteenth register and the sixteenth register are input into the second complex multiplier, the second complex multiplier operates to obtain an I-path operation result and stores the I-path operation result in the twenty-third register, and the second complex multiplier operates to obtain a Q-path operation result and stores the Q-path operation result in the twenty-fourth register.

In cyc 2:

the data in the second register and the data in the fifth register are respectively input into a first complex multiplier through a first multiplexer and a second multiplexer, the data in the twenty-first register and the data in the eighteenth register are respectively input into a first complex multiplier through a seventh multiplexer and a sixth multiplexer, the first complex multiplier obtains a Q-path operation result through operation and inputs the Q-path operation result into a first adder, the first complex multiplier obtains an I-path operation result through operation and inputs the I-path operation result into a second adder, the tenth multiplexer inputs the data in the seventh register into the first adder, the eleventh multiplexer inputs the data in the eighth register into the second adder, the operation result of the first adder is stored in the seventh register, and the operation result stored in the eighth register is stored in the second adder.

The third multiplexer and the fourth multiplexer input the data in the ninth register and the twelfth register into the second complex multiplier respectively, the data in the fifteenth register and the sixteenth register are input into a second complex multiplier, the I-path operation result obtained by the operation of the second complex multiplier is input into a third subtracter, the Q-path operation result obtained by the operation of the second complex multiplier is input into the second subtracter, the data in the twentieth register is input into the third subtracter by a sixteenth multiplexer to subtract the I-path operation result, the data in the seventeenth register is input into the second subtracter by the fifteenth multiplexer to subtract the Q-path operation result, the operation result of the third subtracter is stored in a twentieth register through a third decoder, and the operation result of the second subtracter is stored in a seventeenth register through the second decoder.

The fifth multiplexer inputs the data obtained by the operation in cyc1 and stored in the twenty-third register as a dividend into the first divider, the step coefficient in the step coefficient module is input into the first divider as a divisor, and the operation result of the first divider is stored in the twenty-third register through the fourth decoder and the eighth multiplexer. The step coefficient module receives the IQ _ POW data and performs fixed scaling on the IQ _ POW data to obtain a step coefficient meeting the convergence rate and the filtering performance, wherein the fixed scaling is specifically set according to an empirical value.

In cyc 3:

the data in the third register and the sixth register are respectively input into a first complex multiplier through a first multiplexer and a second multiplexer, the data in the twenty-second register and the nineteenth register are respectively input into the first complex multiplier through a seventh multiplexer and a sixth multiplexer, the first complex multiplier obtains a Q-path operation result through operation and inputs the Q-path operation result into a first adder, the first complex multiplier obtains an I-path operation result through operation and inputs the I-path operation result into a second adder, the tenth multiplexer inputs the data in the seventh register into the first adder, the eleventh multiplexer inputs the data in the eighth register into the second adder, the operation result of the first adder is stored in the seventh register, and the operation result of the second adder is stored in the eighth register.

The third multiplexer and the fourth multiplexer input the data in the tenth register and the thirteenth register to the second complex multiplier, the data in the fifteenth register and the sixteenth register are input into a second complex multiplier, the I-path operation result obtained by the operation of the second complex multiplier is input into a third subtracter, the Q-path operation result obtained by the operation of the second complex multiplier is input into the second subtracter, the data in the twenty-first register is input into the third subtracter to be subtracted from the I-path operation result by a sixteenth multiplexer, the data in the eighteenth register is input into the second subtracter to be subtracted from the Q-path operation result by a fifteenth multiplexer, the operation result of the third subtracter is stored in the twenty-first register through a third decoder, and the operation result of the second subtracter is stored in the eighteenth register through the second decoder.

The fifth multiplexer inputs the data obtained by the operation in cyc1 and stored in the twenty-fourth register as dividend into the first divider, the step coefficient in the step coefficient module is input into the first divider as divisor, and the operation result of the first divider is stored in the twenty-fourth register through the fourth decoder and the ninth multiplexer.

In cyc 4:

the third multiplexer and the fourth multiplexer input the data in the eleventh register and the fourteenth register to the second complex multiplier respectively, the data in the fifteenth register and the sixteenth register are input into a second complex multiplier, the I-path operation result obtained by the operation of the second complex multiplier is input into a third subtracter, the Q-path operation result obtained by the operation of the second complex multiplier is input into the second subtracter, the data in the twenty-second register is input into the third subtracter to be subtracted from the I-path operation result by a sixteenth multiplexer, the data in the nineteenth register is input into the second subtracter to be subtracted from the Q-path operation result by a fifteenth multiplexer, the operation result of the third subtracter is stored in a twenty-second register through a third decoder, and the operation result of the second subtracter is stored in a nineteenth register through the second decoder.

Then the data in the tenth register is shifted into the eleventh register, the data in the ninth register is shifted into the tenth register, the data in the eighth register is saved in the ninth register, and the data in the eighth register is the I4 data output by the adaptive filtering computation module. The data in the thirteenth register is shifted into the fourteenth register, the data in the twelfth register is shifted into the thirteenth register, the data in the seventh register is saved in the twelfth register, and the data in the seventh register is the Q4 data output by the adaptive filtering calculation module.

The data in the twenty-third register is saved into the fifteenth register, and the data in the twenty-fourth register is saved into the sixteenth register.

The data in the second register is shifted into the third register, the data in the first register is shifted into the second register, the first register reads in new I2 data, the data in the fifth register is shifted into the sixth register, the data in the fourth register is shifted into the fifth register, and the fourth register reads in new Q2 data.

It can be seen from the above operation process of the clock cycle that the first register and the fourth register read new data once after the end of a calculation cycle, that is, after cyc4 ends, and the ninth register and the twelfth register read new data once from the eighth register and the ninth register respectively after the end of a calculation cycle. And after the data in the twentieth register is read in the current clock cycle, the data can be updated by new data in the next clock cycle, and the data updating principle of the twenty-first register, the twenty-second register, the seventeenth register, the eighteenth register and the nineteenth register is the same as that of the twentieth register.

After a calculation period is finished, the adaptive filtering calculation module outputs I4 data and Q4 data once, then reads new I1 data, Q1 data, I2 data, Q2 data and IQ _ POW data again, starts a new calculation period, and the steps are repeated in a circulating mode.

Fig. 9 is a structural diagram of a complex band-pass filter module. TheThe complex number band-pass filtering module is a conventional complex number band-pass filter, and specifically comprises: a shift register chain of K +1 registers 78, a shift register chain of K +1 registers 79, K +1 complex multipliers 89, K adders 90, and K adders 91. The structure of the negative number band-pass filtering module adopts a direct FIR to complete the following calculation formula:where K denotes the filter order, and x (n-K) ═ x_i(n-k)+jx_qAnd (n-k), h (k) are filter coefficients.

The working process of the complex band-pass filtering module is as follows:

the shift register chain of K +1 registers 78 holds data for way I, x respectively_i(n)，x_i(n-1)，...，x_i(n-(K-1))，x_i(n-K); the shift register chain consisting of K +1 registers 79 stores data related to Q paths, respectively

x_q(n)，x_q(n-1)，...，x_q(n-(K-1))，x_q(n-K)。

When the data for the I-way is updated,

x_i(n-K)＝x_i(n-(K-1))，

x_i(n-(K-1))＝x_i(n-(K-2))，

…

x_i(n-1)＝x_i(n)，

x_i(n)＝new I data。

when the data for the Q-way is updated,

x_q(n-K)＝x_q(n-(K-1))，

x_q(n-(K-1))＝x_q(n-(K-2))，

…

x_q(n-1)＝x_q(n)，

x_q(n)new Q data。

after the data shift is completed, the data in the corresponding register 78 and the register 79 are sent to the corresponding complex multiplier 89, the corresponding filter coefficient is also sent to the corresponding complex multiplier 89, the complex multiplier 89 calculates the data result about the path I and the data result about the path Q, the data result about the path I is sent to the adder 90, and the data result about the path Q is sent to the adder 91. The adder 90 receives and adds the I-path data sent from the corresponding complex multiplier 89 and the I-path data sent from the previous adder 90, and outputs the result to the next adder 90 after addition. Adder 91 operates on the same principle as adder 90, except that adder 91 processes Q-way data. It should be noted that the first adder 90, i.e. the adder (n)90 receives I-path data output by the complex multiplier (n) and the complex multiplier (n-1), respectively, and the first adder 91, i.e. the adder (n)91 receives Q-path data output by the complex multiplier (n) and the complex multiplier (n-1), respectively; the data output by the last adder 90, i.e. the adder (n- (K-1))90, is the I-path data output by the complex band-pass filter module, and the data output by the last adder 91, i.e. the adder (n- (K-1))91, is the Q-path data output by the complex band-pass filter module. The function of the plurality of band-pass filtering modules is shown as-f in FIG. 3_IFThe u (t), d' (t) signal at (d) is suppressed.

The digital system for image rejection of the low intermediate frequency receiver has a relatively simple structure, can obviously and stably improve IQ mismatch, and improves the image rejection ratio by 15-25 dB. In addition, the time-sharing multiplexing is adopted for most of the operation units in the system, so that the expenditure of hardware units is further saved, namely the cost is saved.

The invention also discloses a method for realizing the digital system for image rejection of the low intermediate frequency receiver. The digital system comprises a direct current computing module, a first subtracter, a conjugate computing module, a power computing module, a self-adaptive filtering computing module and a complex band-pass filtering module; the method comprises the following steps:

the direct current calculation module receives I, Q paths of data to perform direct current calculation and outputs I0 data and Q0 data to the first subtracter, wherein I, Q paths of data are the total input of the system;

the first subtracter receives I-path data and subtracts I0 data output by the direct current calculation module to obtain I1 data, and the first subtracter receives Q-path data and subtracts Q0 data output by the direct current calculation module to obtain Q1 data;

the conjugate calculation module receives the I1 data and the Q1 data to carry out conjugate calculation to obtain I2 data and Q2 data;

the power calculation module receives the I1 data and the Q1 data to carry out power calculation to obtain IQ _ POW data;

the adaptive filter calculation module receives I1 data, Q1 data, I2 data, Q2 data and IQ _ POW data, and performs filtering calculation to obtain I4 and Q4 data after image rejection filtering;

the complex filtering module receives the I4 and Q4 data and carries out complex band-pass filtering to obtain I5 and Q5 data, and the I5 and Q5 data are the total output of the system.

Preferably, the adaptive filtering calculation module includes: a first register, a second register, a third register, a fourth register, a fifth register, a sixth register, a seventh register, an eighth register, a ninth register, a tenth register, an eleventh register, a twelfth register, a thirteenth register, a fourteenth register, a fifteenth register, a sixteenth register, a seventeenth register, an eighteenth register, a nineteenth register, a twentieth register, a twenty-first register, a twenty-second register, a twenty-third register, a twenty-fourth register, a first multiplexer, a second multiplexer, a third multiplexer, a fourth multiplexer, a fifth multiplexer, a sixth multiplexer, a seventh multiplexer, an eighth multiplexer, a ninth multiplexer, a tenth multiplexer, an eleventh multiplexer, a fifteenth multiplexer, A sixteenth multiplexer, a first complex multiplier, a second complex multiplier, a first adder, a second subtractor, a third subtractor, a first divider, a second decoder, a third decoder, a fourth decoder and a step coefficient module; the first register, the second register and the third register form a shift register chain and are respectively used for storing currently received I2 data, last received I2 data and last received I2 data, and the fourth register, the fifth register and the sixth register also form a shift register chain and are respectively used for storing currently received Q2 data, last received Q2 data and last received Q2 data;

the calculation process of the adaptive filtering calculation module includes 4 clock cycles, which are respectively marked as cyc1, cyc2, cyc3 and cyc4, and a calculation cycle is composed of 4 clock cycles, and the step of executing one calculation cycle is as follows:

in cyc1, data in a first register and a fourth register are respectively input into a first complex multiplier through a first multiplexer and a second multiplexer, data in a twentieth register and a seventeenth register are respectively input into the first complex multiplier through a seventh multiplexer and a sixth multiplexer, the first complex multiplier obtains a Q-path operation result through operation and inputs the Q-path operation result into a first adder, the first complex multiplier obtains an I-path operation result through operation and inputs the I-path operation result into a second adder, the tenth multiplexer inputs Q1 data into the first adder, the eleventh multiplexer inputs I1 data into the second adder, the operation result of the first adder is stored in the seventh register, and the operation result of the second adder is stored in an eighth register; the third multiplexer and the fourth multiplexer respectively input data in the ninth register and the twelfth register into a second complex multiplier, data in the fifteenth register and the sixteenth register are input into a second complex multiplier, the second complex multiplier operates to obtain an I-path operation result and stores the I-path operation result in a twenty-third register, and the second complex multiplier operates to obtain a Q-path operation result and stores the Q-path operation result in a twenty-fourth register;

in cyc2, the data in the second register and the fifth register are input to the first complex multiplier through the first multiplexer and the second multiplexer, respectively, the data in the twenty-first register and the eighteenth register are respectively input into the first complex multiplier through the seventh multiplexer and the sixth multiplexer, the first complex multiplier obtains Q-path operation results through operation and inputs the Q-path operation results into the first adder, the first complex multiplier obtains I-path operation results through operation and inputs the I-path operation results into the second adder, the tenth multiplexer inputs data in the seventh register into the first adder, the eleventh multiplexer inputs data in the eighth register into the second adder, the operation results of the first adder are stored in the seventh register, and the operation results of the second adder are stored in the eighth register; the third multiplexer and the fourth multiplexer input the data in the ninth register and the twelfth register into the second complex multiplier respectively, the data in the fifteenth register and the sixteenth register are input into a second complex multiplier, the second complex multiplier obtains an I-path operation result through operation and inputs the I-path operation result into a third subtracter, the second complex multiplier obtains a Q-path operation result through operation and inputs the Q-path operation result into the second subtracter, a sixteenth multiplexer inputs the data in the twentieth register into the third subtracter to subtract the I-path operation result, a fifteenth multiplexer inputs the data in the seventeenth register into the second subtracter to subtract the Q-path operation result, the operation result of the third subtracter is stored in a twentieth register through a third decoder, and the operation result of the second subtracter is stored in a seventeenth register through the second decoder; the fifth multiplexer inputs the data obtained by operation in cyc1 and stored in the twenty-third register into the first divider as dividend, the step coefficient in the step coefficient module is input into the first divider as divisor, and the operation result of the first divider is stored in the twenty-third register through the fourth decoder and the eighth multiplexer;

in cyc3, the data in the third register and the sixth register are input to the first complex multiplier through the first multiplexer and the second multiplexer, respectively, the data in the twenty-second register and the nineteenth register are input into the first complex multiplier through the seventh multiplexer and the sixth multiplexer respectively, the first complex multiplier obtains Q-path operation results through operation and inputs the Q-path operation results into the first adder, the first complex multiplier obtains I-path operation results through operation and inputs the I-path operation results into the second adder, the tenth multiplexer inputs data in the seventh register into the first adder, the eleventh multiplexer inputs data in the eighth register into the second adder, the operation results of the first adder are stored in the seventh register, and the operation results of the second adder are stored in the eighth register; the third multiplexer and the fourth multiplexer input the data in the tenth register and the thirteenth register to the second complex multiplier, the data in the fifteenth register and the sixteenth register are input into a second complex multiplier, the I-path operation result obtained by the operation of the second complex multiplier is input into a third subtracter, the Q-path operation result obtained by the operation of the second complex multiplier is input into the second subtracter, the data in the twenty-first register is input into the third subtracter to be subtracted from the I-path operation result by a sixteenth multiplexer, the data in the eighteenth register is input into the second subtracter to be subtracted from the Q-path operation result by a fifteenth multiplexer, the operation result of the third subtracter is stored in the twenty-first register through a third decoder, and the operation result of the second subtracter is stored in the eighteenth register through the second decoder; the fifth multiplexer inputs the data obtained by operation in cyc1 and stored in the twenty-fourth register into the first divider as dividend, the step coefficient in the step coefficient module is input into the first divider as divisor, and the operation result of the first divider is stored in the twenty-fourth register through the fourth decoder and the ninth multiplexer;

in cyc4, the third multiplexer and the fourth multiplexer input data in the eleventh register and the fourteenth register to the second complex multiplier, data in the fifteenth register and the sixteenth register to the second complex multiplier, the second complex multiplier operates to obtain an I-path operation result and inputs the I-path operation result to the third subtractor, the second complex multiplier operates to obtain a Q-path operation result and inputs the Q-path operation result to the second subtractor, the sixteenth multiplexer inputs data in the twenty-second register to the third subtractor and subtracts the I-path operation result, the fifteenth multiplexer inputs data in the nineteenth register to the second subtractor and subtracts the Q-path operation result, the operation result of the third subtractor is stored in the twenty-second register through the third decoder, and the operation result of the second subtractor is stored in the nineteenth register through the second decoder;

then, data in the tenth register is shifted into the eleventh register, data in the ninth register is shifted into the tenth register, data in the eighth register is stored in the ninth register, and the data in the eighth register is I4 data output by the adaptive filtering calculation module; shifting the data in the thirteenth register to the fourteenth register, shifting the data in the twelfth register to the thirteenth register, saving the data in the seventh register in the twelfth register, and outputting the data in the seventh register as Q4 data by the adaptive filtering calculation module; shifting the data in the second register into a third register, shifting the data in the first register into the second register, reading in new I2 data by the first register, shifting the data in the fifth register into a sixth register, shifting the data in the fourth register into the fifth register, and reading in new Q2 data by the fourth register; the data in the twenty-third register is saved into the fifteenth register, and the data in the twenty-fourth register is saved into the sixteenth register.

Preferably, the step coefficient module receives the IQ _ POW data, and performs fixed scaling on the IQ _ POW data to obtain a step coefficient meeting the convergence rate and the filtering performance.

Preferably, the dc calculating module includes a thirteenth multiplexer, a first multiplier, a third adder, a second multiplier, a fourteenth multiplexer, a twenty-fifth register, a twenty-sixth register, and a fifth decoder;

the operation steps executed by the direct current calculation module are as follows:

firstly, a thirteenth multiplexer selects total input I-path data to input into a first multiplier, the result obtained by multiplying the data input by the thirteenth multiplexer by the fixed coefficient dc _ a1 read by the first multiplier is input into a third adder, the I0 data obtained by the last direct current calculation is currently stored in a twenty-fifth register, the data in the twenty-fifth register is input into a second multiplier by a fourteenth multiplexer, the result obtained by multiplying the data input by the fourteenth multiplexer by the fixed coefficient dc _ b1 read by the second multiplier is input into the third adder, and the result obtained by adding by the third adder is input into the twenty-fifth register through a fifth decoder and is used as the I0 data output by a direct current calculation module;

then, the thirteenth multiplexer selects Q paths of data of the total input to input the Q paths of data into the first multiplier, the result obtained by multiplying the data input by the thirteenth multiplexer by the fixed coefficient dc _ a1 read by the first multiplier is input into the third adder, the Q0 data obtained by the last direct current calculation is currently stored in the twenty-sixth register, the fourteenth multiplexer inputs the data in the twenty-sixth register into the second multiplier, the result obtained by multiplying the data input by the fourteenth multiplexer by the fixed coefficient dc _ b1 read by the second multiplier is input into the third adder, and the result obtained by adding by the third adder is input into the twenty-sixth register through the fifth decoder and is used as the Q0 data output by the direct current calculation module.

Preferably, the power calculation module comprises a third multiplier, a fourth adder, a fifth multiplier, a sixth multiplier, a fifth adder and a twenty-seventh register;

the calculation steps executed by the power calculation module are as follows:

the third multiplier reads the I1 data and performs the square operation of the I1 data and inputs it to the fourth adder, the fourth multiplier reads the Q1 data and performs the square operation of the Q1 data and inputs it to the fourth adder, the fourth adder adds the data output from the third multiplier and the fourth multiplier and inputs the result to the fifth multiplier, the fifth multiplier reads the fixed coefficient pow _ a1 to multiply the data output from the fourth adder and inputs the result to the fifth adder, the IQ _ POW data obtained by last power calculation is currently stored in the twenty-seventh register, the IQ _ POW data currently stored in the twenty-seventh register is read by the sixth multiplier, multiplied by the read fixed coefficient POW _ b1 and input into the fifth adder, the data output by the fifth multiplier and the data output by the sixth multiplier are added by the fifth adder, the obtained result is stored in a twenty-seventh register and is used as IQ _ POW data output by the power calculation module.

Various other modifications and changes may be made by those skilled in the art based on the above-described technical solutions and concepts, and all such modifications and changes should fall within the scope of the claims of the present invention.

Claims (10)

1. A digital system for image rejection in a low intermediate frequency receiver, comprising: the device comprises a direct current calculation module, a first subtracter, a conjugate calculation module, a power calculation module, an adaptive filtering calculation module and a complex band-pass filtering module; the direct current calculation module receives I, Q data, performs direct current calculation and outputs I0 data and Q0 data to a first subtracter, I, Q data is total input of a system, the first subtracter receives I data and subtracts I0 data output by the direct current calculation module to obtain I1 data, the first subtracter receives Q data and subtracts Q0 data output by the direct current calculation module to obtain Q1 data, the conjugate calculation module receives I1 data and Q1 data, performs conjugate calculation to obtain I2 data and Q2 data, the power calculation module receives I1 data and Q1 data, performs power calculation to obtain IQ _ POW data, the adaptive filter calculation module receives I1 data, Q1 data, I2 data, Q2 data and IQ _ POW data, performs filtering calculation to obtain I4 data and Q4 data after image rejection filtering, the complex filter module receives I4 data and Q4 data, performs complex band-pass filtering to obtain I5 data and Q5 data, the I5 data and the Q5 data are the total output of the system, and the adaptive filtering computation module comprises: a first register, a second register, a third register, a fourth register, a fifth register, a sixth register, a seventh register, an eighth register, a ninth register, a tenth register, an eleventh register, a twelfth register, a thirteenth register, a fourteenth register, a fifteenth register, a sixteenth register, a seventeenth register, an eighteenth register, a nineteenth register, a twentieth register, a twenty-first register, a twenty-second register, a twenty-third register, a twenty-fourth register, a first multiplexer, a second multiplexer, a third multiplexer, a fourth multiplexer, a fifth multiplexer, a sixth multiplexer, a seventh multiplexer, an eighth multiplexer, a ninth multiplexer, a tenth multiplexer, an eleventh multiplexer, a fifteenth multiplexer, A sixteenth multiplexer, a first complex multiplier, a second complex multiplier, a first adder, a second subtractor, a third subtractor, a first divider, a second decoder, a third decoder, a fourth decoder and a step coefficient module; the first register, the second register and the third register form a shift register chain and are respectively used for storing currently received I2 data, last received I2 data and last received I2 data, and the fourth register, the fifth register and the sixth register also form a shift register chain and are respectively used for storing currently received Q2 data, last received Q2 data and last received Q2 data.

2. The digital system for image rejection of a low intermediate frequency receiver of claim 1, wherein the filtering calculation comprises 4 clock cycles, denoted cyc1, cyc2, cyc3 and cyc4, and the calculation cycle is composed of 4 clock cycles, and the specific calculation cycle is performed as follows:

in cyc1, data in a first register and a fourth register are respectively input into a first complex multiplier through a first multiplexer and a second multiplexer, data in a twentieth register and a seventeenth register are respectively input into the first complex multiplier through a seventh multiplexer and a sixth multiplexer, the first complex multiplier obtains a Q-path operation result through operation and inputs the Q-path operation result into a first adder, the first complex multiplier obtains an I-path operation result through operation and inputs the I-path operation result into a second adder, the tenth multiplexer inputs Q1 data into the first adder, the eleventh multiplexer inputs I1 data into the second adder, the operation result of the first adder is stored in the seventh register, and the operation result of the second adder is stored in an eighth register; the third multiplexer and the fourth multiplexer respectively input data in the ninth register and the twelfth register into a second complex multiplier, data in the fifteenth register and the sixteenth register are input into a second complex multiplier, the second complex multiplier operates to obtain an I-path operation result and stores the I-path operation result in a twenty-third register, and the second complex multiplier operates to obtain a Q-path operation result and stores the Q-path operation result in a twenty-fourth register;

in cyc2, the data in the second register and the fifth register are input to the first complex multiplier through the first multiplexer and the second multiplexer, respectively, the data in the twenty-first register and the eighteenth register are respectively input into the first complex multiplier through the seventh multiplexer and the sixth multiplexer, the first complex multiplier obtains Q-path operation results through operation and inputs the Q-path operation results into the first adder, the first complex multiplier obtains I-path operation results through operation and inputs the I-path operation results into the second adder, the tenth multiplexer inputs data in the seventh register into the first adder, the eleventh multiplexer inputs data in the eighth register into the second adder, the operation results of the first adder are stored in the seventh register, and the operation results of the second adder are stored in the eighth register; the third multiplexer and the fourth multiplexer input the data in the ninth register and the twelfth register into the second complex multiplier respectively, the data in the fifteenth register and the sixteenth register are input into a second complex multiplier, the second complex multiplier obtains an I-path operation result through operation and inputs the I-path operation result into a third subtracter, the second complex multiplier obtains a Q-path operation result through operation and inputs the Q-path operation result into the second subtracter, a sixteenth multiplexer inputs the data in the twentieth register into the third subtracter to subtract the I-path operation result, a fifteenth multiplexer inputs the data in the seventeenth register into the second subtracter to subtract the Q-path operation result, the operation result of the third subtracter is stored in a twentieth register through a third decoder, and the operation result of the second subtracter is stored in a seventeenth register through the second decoder; the fifth multiplexer inputs the data obtained by operation in cyc1 and stored in the twenty-third register into the first divider as dividend, the step coefficient in the step coefficient module is input into the first divider as divisor, and the operation result of the first divider is stored in the twenty-third register through the fourth decoder and the eighth multiplexer;

in cyc3, the data in the third register and the sixth register are input to the first complex multiplier through the first multiplexer and the second multiplexer, respectively, the data in the twenty-second register and the nineteenth register are input into the first complex multiplier through the seventh multiplexer and the sixth multiplexer respectively, the first complex multiplier obtains Q-path operation results through operation and inputs the Q-path operation results into the first adder, the first complex multiplier obtains I-path operation results through operation and inputs the I-path operation results into the second adder, the tenth multiplexer inputs data in the seventh register into the first adder, the eleventh multiplexer inputs data in the eighth register into the second adder, the operation results of the first adder are stored in the seventh register, and the operation results of the second adder are stored in the eighth register; the third multiplexer and the fourth multiplexer input the data in the tenth register and the thirteenth register to the second complex multiplier, the data in the fifteenth register and the sixteenth register are input into a second complex multiplier, the I-path operation result obtained by the operation of the second complex multiplier is input into a third subtracter, the Q-path operation result obtained by the operation of the second complex multiplier is input into the second subtracter, the data in the twenty-first register is input into the third subtracter to be subtracted from the I-path operation result by a sixteenth multiplexer, the data in the eighteenth register is input into the second subtracter to be subtracted from the Q-path operation result by a fifteenth multiplexer, the operation result of the third subtracter is stored in the twenty-first register through a third decoder, and the operation result of the second subtracter is stored in the eighteenth register through the second decoder; the fifth multiplexer inputs the data obtained by operation in cyc1 and stored in the twenty-fourth register into the first divider as dividend, the step coefficient in the step coefficient module is input into the first divider as divisor, and the operation result of the first divider is stored in the twenty-fourth register through the fourth decoder and the ninth multiplexer;

in cyc4, the third multiplexer and the fourth multiplexer input data in the eleventh register and the fourteenth register to the second complex multiplier, data in the fifteenth register and the sixteenth register to the second complex multiplier, the second complex multiplier operates to obtain an I-path operation result and inputs the I-path operation result to the third subtractor, the second complex multiplier operates to obtain a Q-path operation result and inputs the Q-path operation result to the second subtractor, the sixteenth multiplexer inputs data in the twenty-second register to the third subtractor and subtracts the I-path operation result, the fifteenth multiplexer inputs data in the nineteenth register to the second subtractor and subtracts the Q-path operation result, the operation result of the third subtractor is stored in the twenty-second register through the third decoder, and the operation result of the second subtractor is stored in the nineteenth register through the second decoder;

then, data in the tenth register is shifted into the eleventh register, data in the ninth register is shifted into the tenth register, data in the eighth register is stored in the ninth register, and the data in the eighth register is I4 data output by the adaptive filtering calculation module; shifting the data in the thirteenth register to the fourteenth register, shifting the data in the twelfth register to the thirteenth register, saving the data in the seventh register in the twelfth register, and outputting the data in the seventh register as Q4 data by the adaptive filtering calculation module; shifting the data in the second register into a third register, shifting the data in the first register into the second register, reading in new I2 data by the first register, shifting the data in the fifth register into a sixth register, shifting the data in the fourth register into the fifth register, and reading in new Q2 data by the fourth register; the data in the twenty-third register is saved into the fifteenth register, and the data in the twenty-fourth register is saved into the sixteenth register.

3. The digital system for image rejection of a low if receiver of claim 2, wherein the step factor module receives IQ _ POW data and scales the IQ _ POW data to obtain the step factor satisfying the convergence rate and the filtering performance.

4. The digital system for image rejection of a low intermediate frequency receiver according to claim 1, wherein said dc calculation block comprises a thirteenth multiplexer, a first multiplier, a third adder, a second multiplier, a fourteenth multiplexer, a twenty-fifth register, a twenty-sixth register, and a fifth decoder; the operation process of the direct current calculation module is as follows:

firstly, a thirteenth multiplexer selects total input I-path data to input into a first multiplier, the result obtained by multiplying the data input by the thirteenth multiplexer by the fixed coefficient dc _ a1 read by the first multiplier is input into a third adder, the I0 data obtained by the last direct current calculation is currently stored in a twenty-fifth register, the data in the twenty-fifth register is input into a second multiplier by a fourteenth multiplexer, the result obtained by multiplying the data input by the fourteenth multiplexer by the fixed coefficient dc _ b1 read by the second multiplier is input into the third adder, and the result obtained by adding by the third adder is input into the twenty-fifth register through a fifth decoder and is used as the I0 data output by a direct current calculation module; then, the thirteenth multiplexer selects Q paths of data of the total input to input the Q paths of data into the first multiplier, the result obtained by multiplying the data input by the thirteenth multiplexer by the fixed coefficient dc _ a1 read by the first multiplier is input into the third adder, the Q0 data obtained by the last direct current calculation is currently stored in the twenty-sixth register, the fourteenth multiplexer inputs the data in the twenty-sixth register into the second multiplier, the result obtained by multiplying the data input by the fourteenth multiplexer by the fixed coefficient dc _ b1 read by the second multiplier is input into the third adder, and the result obtained by adding by the third adder is input into the twenty-sixth register through the fifth decoder and is used as the Q0 data output by the direct current calculation module.

5. The digital system for image rejection of a low intermediate frequency receiver of claim 1, wherein the power calculation module comprises a third multiplier, a fourth adder, a fifth multiplier, a sixth multiplier, a fifth adder, and a twenty-seventh register; the operation process of the power calculation module is as follows:

the third multiplier reads the I1 data and performs the square operation of the I1 data and inputs it to the fourth adder, the fourth multiplier reads the Q1 data and performs the square operation of the Q1 data and inputs it to the fourth adder, the fourth adder adds the data output from the third multiplier and the fourth multiplier and inputs the result to the fifth multiplier, the fifth multiplier reads the fixed coefficient pow _ a1 to multiply the data output from the fourth adder and inputs the result to the fifth adder, the IQ _ POW data obtained by last power calculation is currently stored in the twenty-seventh register, the IQ _ POW data currently stored in the twenty-seventh register is read by the sixth multiplier, multiplied by the read fixed coefficient POW _ b1 and input into the fifth adder, the data output by the fifth multiplier and the data output by the sixth multiplier are added by the fifth adder, the obtained result is stored in a twenty-seventh register and is used as IQ _ POW data output by the power calculation module.

6. A method for realizing a digital system of image rejection of a low-intermediate frequency receiver is characterized in that the digital system comprises a direct current calculation module, a first subtracter, a conjugate calculation module, a power calculation module, a self-adaptive filtering calculation module and a complex band-pass filtering module; the method comprises the following steps:

the direct current calculation module receives I, Q paths of data to perform direct current calculation and outputs I0 data and Q0 data to the first subtracter, wherein I, Q paths of data are the total input of the system;

the first subtracter receives I-path data and subtracts I0 data output by the direct current calculation module to obtain I1 data, and the first subtracter receives Q-path data and subtracts Q0 data output by the direct current calculation module to obtain Q1 data;

the conjugate calculation module receives the I1 data and the Q1 data to carry out conjugate calculation to obtain I2 data and Q2 data;

the power calculation module receives the I1 data and the Q1 data to carry out power calculation to obtain IQ _ POW data;

the adaptive filter calculation module receives I1 data, Q1 data, I2 data, Q2 data and IQ _ POW data, and performs filtering calculation to obtain I4 and Q4 data after image rejection filtering;

the complex filtering module receives the I4 and Q4 data and carries out complex band-pass filtering to obtain I5 and Q5 data, the I5 and Q5 data are the total output of the system, and the self-adaptive filtering calculation module comprises: a first register, a second register, a third register, a fourth register, a fifth register, a sixth register, a seventh register, an eighth register, a ninth register, a tenth register, an eleventh register, a twelfth register, a thirteenth register, a fourteenth register, a fifteenth register, a sixteenth register, a seventeenth register, an eighteenth register, a nineteenth register, a twentieth register, a twenty-first register, a twenty-second register, a twenty-third register, a twenty-fourth register, a first multiplexer, a second multiplexer, a third multiplexer, a fourth multiplexer, a fifth multiplexer, a sixth multiplexer, a seventh multiplexer, an eighth multiplexer, a ninth multiplexer, a tenth multiplexer, an eleventh multiplexer, a fifteenth multiplexer, A sixteenth multiplexer, a first complex multiplier, a second complex multiplier, a first adder, a second subtractor, a third subtractor, a first divider, a second decoder, a third decoder, a fourth decoder and a step coefficient module; the first register, the second register and the third register form a shift register chain and are respectively used for storing currently received I2 data, last received I2 data and last received I2 data, and the fourth register, the fifth register and the sixth register also form a shift register chain and are respectively used for storing currently received Q2 data, last received Q2 data and last received Q2 data.

7. The method as claimed in claim 6, wherein the calculation process of the adaptive filtering calculation module includes 4 clock cycles, respectively denoted as cyc1, cyc2, cyc3 and cyc4, and the calculation cycle is composed of 4 clock cycles, and the step of executing one calculation cycle is as follows:

in cyc1, data in a first register and a fourth register are respectively input into a first complex multiplier through a first multiplexer and a second multiplexer, data in a twentieth register and a seventeenth register are respectively input into the first complex multiplier through a seventh multiplexer and a sixth multiplexer, the first complex multiplier obtains a Q-path operation result through operation and inputs the Q-path operation result into a first adder, the first complex multiplier obtains an I-path operation result through operation and inputs the I-path operation result into a second adder, the tenth multiplexer inputs Q1 data into the first adder, the eleventh multiplexer inputs I1 data into the second adder, the operation result of the first adder is stored in the seventh register, and the operation result of the second adder is stored in an eighth register; the third multiplexer and the fourth multiplexer respectively input data in the ninth register and the twelfth register into a second complex multiplier, data in the fifteenth register and the sixteenth register are input into a second complex multiplier, the second complex multiplier operates to obtain an I-path operation result and stores the I-path operation result in a twenty-third register, and the second complex multiplier operates to obtain a Q-path operation result and stores the Q-path operation result in a twenty-fourth register;

in cyc2, the data in the second register and the fifth register are input to the first complex multiplier through the first multiplexer and the second multiplexer, respectively, the data in the twenty-first register and the eighteenth register are respectively input into the first complex multiplier through the seventh multiplexer and the sixth multiplexer, the first complex multiplier obtains Q-path operation results through operation and inputs the Q-path operation results into the first adder, the first complex multiplier obtains I-path operation results through operation and inputs the I-path operation results into the second adder, the tenth multiplexer inputs data in the seventh register into the first adder, the eleventh multiplexer inputs data in the eighth register into the second adder, the operation results of the first adder are stored in the seventh register, and the operation results of the second adder are stored in the eighth register; the third multiplexer and the fourth multiplexer input the data in the ninth register and the twelfth register into the second complex multiplier respectively, the data in the fifteenth register and the sixteenth register are input into a second complex multiplier, the second complex multiplier obtains an I-path operation result through operation and inputs the I-path operation result into a third subtracter, the second complex multiplier obtains a Q-path operation result through operation and inputs the Q-path operation result into the second subtracter, a sixteenth multiplexer inputs the data in the twentieth register into the third subtracter to subtract the I-path operation result, a fifteenth multiplexer inputs the data in the seventeenth register into the second subtracter to subtract the Q-path operation result, the operation result of the third subtracter is stored in a twentieth register through a third decoder, and the operation result of the second subtracter is stored in a seventeenth register through the second decoder; the fifth multiplexer inputs the data obtained by operation in cyc1 and stored in the twenty-third register into the first divider as dividend, the step coefficient in the step coefficient module is input into the first divider as divisor, and the operation result of the first divider is stored in the twenty-third register through the fourth decoder and the eighth multiplexer;

in cyc3, the data in the third register and the sixth register are input to the first complex multiplier through the first multiplexer and the second multiplexer, respectively, the data in the twenty-second register and the nineteenth register are input into the first complex multiplier through the seventh multiplexer and the sixth multiplexer respectively, the first complex multiplier obtains Q-path operation results through operation and inputs the Q-path operation results into the first adder, the first complex multiplier obtains I-path operation results through operation and inputs the I-path operation results into the second adder, the tenth multiplexer inputs data in the seventh register into the first adder, the eleventh multiplexer inputs data in the eighth register into the second adder, the operation results of the first adder are stored in the seventh register, and the operation results of the second adder are stored in the eighth register; the third multiplexer and the fourth multiplexer input the data in the tenth register and the thirteenth register to the second complex multiplier, the data in the fifteenth register and the sixteenth register are input into a second complex multiplier, the I-path operation result obtained by the operation of the second complex multiplier is input into a third subtracter, the Q-path operation result obtained by the operation of the second complex multiplier is input into the second subtracter, the data in the twenty-first register is input into the third subtracter to be subtracted from the I-path operation result by a sixteenth multiplexer, the data in the eighteenth register is input into the second subtracter to be subtracted from the Q-path operation result by a fifteenth multiplexer, the operation result of the third subtracter is stored in the twenty-first register through a third decoder, and the operation result of the second subtracter is stored in the eighteenth register through the second decoder; the fifth multiplexer inputs the data obtained by operation in cyc1 and stored in the twenty-fourth register into the first divider as dividend, the step coefficient in the step coefficient module is input into the first divider as divisor, and the operation result of the first divider is stored in the twenty-fourth register through the fourth decoder and the ninth multiplexer;

in cyc4, the third multiplexer and the fourth multiplexer input data in the eleventh register and the fourteenth register to the second complex multiplier, data in the fifteenth register and the sixteenth register to the second complex multiplier, the second complex multiplier operates to obtain an I-path operation result and inputs the I-path operation result to the third subtractor, the second complex multiplier operates to obtain a Q-path operation result and inputs the Q-path operation result to the second subtractor, the sixteenth multiplexer inputs data in the twenty-second register to the third subtractor and subtracts the I-path operation result, the fifteenth multiplexer inputs data in the nineteenth register to the second subtractor and subtracts the Q-path operation result, the operation result of the third subtractor is stored in the twenty-second register through the third decoder, and the operation result of the second subtractor is stored in the nineteenth register through the second decoder;

then, data in the tenth register is shifted into the eleventh register, data in the ninth register is shifted into the tenth register, data in the eighth register is stored in the ninth register, and the data in the eighth register is I4 data output by the adaptive filtering calculation module; shifting the data in the thirteenth register to the fourteenth register, shifting the data in the twelfth register to the thirteenth register, saving the data in the seventh register in the twelfth register, and outputting the data in the seventh register as Q4 data by the adaptive filtering calculation module; shifting the data in the second register into a third register, shifting the data in the first register into the second register, reading in new I2 data by the first register, shifting the data in the fifth register into a sixth register, shifting the data in the fourth register into the fifth register, and reading in new Q2 data by the fourth register; the data in the twenty-third register is saved into the fifteenth register, and the data in the twenty-fourth register is saved into the sixteenth register.

8. The method as claimed in claim 7, wherein the step factor module receives IQ _ POW data and scales the IQ _ POW data to obtain the step factor satisfying convergence speed and filtering performance.

9. The method of claim 6, wherein the DC calculation module comprises a thirteenth multiplexer, a first multiplier, a third adder, a second multiplier, a fourteenth multiplexer, a twenty-fifth register, a twenty-sixth register, and a fifth decoder;

the operation steps executed by the direct current calculation module are as follows:

firstly, a thirteenth multiplexer selects total input I-path data to input into a first multiplier, the result obtained by multiplying the data input by the thirteenth multiplexer by the fixed coefficient dc _ a1 read by the first multiplier is input into a third adder, the I0 data obtained by the last direct current calculation is currently stored in a twenty-fifth register, the data in the twenty-fifth register is input into a second multiplier by a fourteenth multiplexer, the result obtained by multiplying the data input by the fourteenth multiplexer by the fixed coefficient dc _ b1 read by the second multiplier is input into the third adder, and the result obtained by adding by the third adder is input into the twenty-fifth register through a fifth decoder and is used as the I0 data output by a direct current calculation module;

then, the thirteenth multiplexer selects Q paths of data of the total input to input the Q paths of data into the first multiplier, the result obtained by multiplying the data input by the thirteenth multiplexer by the fixed coefficient dc _ a1 read by the first multiplier is input into the third adder, the Q0 data obtained by the last direct current calculation is currently stored in the twenty-sixth register, the fourteenth multiplexer inputs the data in the twenty-sixth register into the second multiplier, the result obtained by multiplying the data input by the fourteenth multiplexer by the fixed coefficient dc _ b1 read by the second multiplier is input into the third adder, and the result obtained by adding by the third adder is input into the twenty-sixth register through the fifth decoder and is used as the Q0 data output by the direct current calculation module.

10. The method of claim 6, wherein the power calculating module comprises a third multiplier, a fourth adder, a fifth multiplier, a sixth multiplier, a fifth adder, and a twenty-seventh register;

the calculation steps executed by the power calculation module are as follows:

the third multiplier reads the I1 data and performs the square operation of the I1 data and inputs it to the fourth adder, the fourth multiplier reads the Q1 data and performs the square operation of the Q1 data and inputs it to the fourth adder, the fourth adder adds the data output from the third multiplier and the fourth multiplier and inputs the result to the fifth multiplier, the fifth multiplier reads the fixed coefficient pow _ a1 to multiply the data output from the fourth adder and inputs the result to the fifth adder, the IQ _ POW data obtained by last power calculation is currently stored in the twenty-seventh register, the IQ _ POW data currently stored in the twenty-seventh register is read by the sixth multiplier, multiplied by the read fixed coefficient POW _ b1 and input into the fifth adder, the data output by the fifth multiplier and the data output by the sixth multiplier are added by the fifth adder, the obtained result is stored in a twenty-seventh register and is used as IQ _ POW data output by the power calculation module.