CN105187065A - Successive approximation ADC ultra-low power consumption capacitor array and logic control method thereof - Google Patents

Abstract

The invention discloses a successive approximation ADC ultra-low power consumption capacitor array and a logic control method thereof, belonging to the technical field of successive approximation ADC ultra-low power consumption design, including a binary capacitor array and a switch array, a reference (V _ref , V _cm = V _ref /2 and Gnd=0) and the new logic control mode combined with the upper plate sampling of the capacitor, the sequence initialization of the switch control, the reduction of the power consumption of the parasitic capacitor and the monotonous switching of the capacitor, the average energy consumption of the capacitor array disclosed in the present invention is only 1.2% of the charge redistribution structure has the advantages of simple structure, low power consumption, and small area. Applying the present invention to successive approximation ADC can significantly reduce power consumption, and under the same conversion precision, the scale reduction of the capacitance array of the present invention is also conducive to improving the A/D conversion rate.

Description

Successive approximation ADC ultra-low power consumption capacitor array and its logic control method

technical field

The invention belongs to the technical field of integrated circuits, and in particular relates to an ultra-low power consumption capacitor array for successive approximation ADCs and a logic control method thereof.

Background technique

The charge redistribution successive approximation (SAR) ADC with capacitor array as the main structure has been widely used due to its low power consumption advantage. With the advancement of CMOS integrated circuit design technology and the reduction of process feature size, the scale of SoC is becoming more and more Especially in implanted bioelectronic systems for neural signal recording (EEG, ECOG, etc.), the ADC embedded in it needs to have the characteristics of ultra-low power consumption and miniaturization. The scale of the traditional charge redistribution SARADC capacitor array varies with the The number of ADC digits increases exponentially, which is not conducive to the optimization of area, power consumption and speed. Figure 1 shows the traditional N-bit fully differential charge redistribution SARADC structure, and its capacitor array includes 2 ^N+1 unit capacitors. On the one hand, due to the constraints of matching accuracy and noise performance, not only the circuit area is large, the process cost is high, but also the dynamic power consumption of the capacitor array is relatively large; on the other hand, the large-scale capacitor array leads to large input capacitance of SARADC, It not only affects the improvement of the ADC sampling rate, but also requires the analog front-end (AFE) circuit to have a strong driving capability, which affects the low power consumption optimization of the AFE circuit and the entire SoC.

Contents of the invention

The object of the present invention is to overcome the shortcoming of above-mentioned prior art, provide a kind of capacitor array of successive approximation ADC ultra-low power consumption and logic control method thereof, it has ultra-low power consumption, miniaturized capacitor array and logic control mode, can significantly reduce The power consumption of the SARADC reduces the chip area, saves the cost, and at the same time improves the flexibility of the matching design of the capacitor array.

The purpose of the present invention is achieved through the following technical solutions:

The successive approximation ADC ultra-low power consumption capacitor array of the present invention comprises two groups of (N-2)-bit binary capacitor arrays respectively connected to the two input terminals of the comparator, and each group of (N-2)-bit binary capacitor arrays is passed through a switch The array is connected to voltage references V _ref , V _cm , Gnd; each (N-2)-bit binary capacitor array is composed of capacitors C ₀ , C ₁ , C ₂ , ... C _N-2 connections, where N is a natural number; One end of the capacitors C ₀ , C ₁ , C ₂ , ... C _N-2 of a group of (N-2)-bit binary capacitor arrays are respectively connected to the differential input signal V _ip , and the other ends of each capacitor are respectively passed through the switches in the switch array. The switches are connected to the voltage references V _ref , V _cm , Gnd; one end of the capacitors C ₀ , C ₁ , C ₂ , ... C _N-2 of the second (N-2)-bit binary capacitor array is respectively connected to the differential input signal V _in , the other end is respectively connected to voltage references V _ref , V _cm , Gnd through switches in the switch array; the output end of the comparator is connected to the successive approximation logic control unit SARLogic, and according to the output of the comparator, the successive approximation logic control unit Under the action of clock signals clk and soc, SARLogic realizes the logic control of the capacitor array switch, and generates the digital output B ₀ -B _N-1 of ADC.

Further, the above C ₀ =C ₁ , C _i =2C _i-1 , i=1˜N-2.

Further, the switch array connected to the first (N-2)-bit binary capacitor array is the first switch array, and the first switch array is composed of switches S _0p , S _1p , S _2p , ... S _(N-2)p composition.

Further, the switch array connected to the second (N-2)-bit binary capacitor array is the second switch array, and the second switch array is composed of switches S _0n , S _1n , S _2n , ... S _(N-2)n composition.

The present invention also proposes a logic control method for the above-mentioned successive approximation ADC ultra-low power consumption capacitor array:

(1) In the sampling stage, the switch array timing initialization technology is adopted, S _(N-2)n = S _(N-2)p = "1", S _(N-3)n = S _(N-4)n = ... S _1n = S _0n = "0", S _(N-3)p = S (N _{- 4)p} = ... S _1p = S _0p = "0", change S _{( N-2)} (S _(N-2)n or S _(N-2)p ), output the control signal S _(N-2) of the highest switch corresponding to the larger capacitor array connected by "1" to "0", and then compare the size of the capacitor array output again to generate the second digital output B _N-2 ; "1" and "0" respectively represent that the corresponding switch connects its corresponding capacitor to V _ref and Gnd;

(2) By adopting upper plate sampling and switch array logic timing initialization technology, no reference is needed to provide energy consumption in the process of generating the highest and second digital outputs; when generating the third digital output B _N-3 , If it is an up jump, the switch control signal of the capacitor array changes from "100...0" to "11/21/2...1/2", and the energy consumption is -C _N-2 V _ref ² /2; if it is a down jump, the capacitor array switch control signal changes from "100...0" to "1/200...0", and the energy consumption is also -C _N-2 V _ref ² /2; "1/2" means that the corresponding switch will The corresponding capacitor is connected to V _cm , V _cm =V _ref /2.

Further, in the above method, after the first three digits of digital output B _N-1 -B _N-3 are generated, the capacitor array adopts a monotonic switching logic control mode in the subsequent conversion process, and only one capacitor is generated in each clock cycle. Changes in connection relationships.

Further, according to the difference of the second digital output B _N-2 above, the change of the common mode output level of the capacitor array presents two trends:

1) If B _N-2 outputs logic 1, the capacitor array needs to jump up to generate the third output B _N-3 , and the common-mode output level of the capacitor array gradually approaches V _ref /2 during the successive approximation process;

2) If B _N-2 outputs logic 0, the capacitor array needs to undergo a down transition to generate the third bit output B _N-3 , and the common-mode output level of the capacitor array gradually approaches V _ref /4 during the successive approximation process.

The present invention has the following beneficial effects:

The capacitor array structure provided by the present invention has obvious advantages. The capacitor array scale and the number of switches are only 25% and 38.5% of the traditional charge redistribution structure. 1.2% of the structure, in the case of considering the energy consumption of parasitic capacitance, taking C _pt =0.1C _tot , C _pb =0.15C as an example, the energy consumption of the capacitor array provided by the present invention is only 1.4% of the traditional charge redistribution structure .

Description of drawings

Figure 1 shows the structure of a traditional charge redistribution SARADC;

Fig. 2 is the novel SARADC structure of the present invention;

Fig. 3 is 4-bitA/D conversion embodiment of the present invention;

a, the generation of the highest two digit output,

b, Generation of the lowest two digits output;

Fig. 4 is the improvement of the conversion waveform by the logic control mode in the embodiment of the present invention;

Fig. 5 is the improvement of parasitic capacitance power consumption by logic control mode in the embodiment of the present invention;

Fig. 6 is the energy consumption curve of 10-bit embodiment of the present invention and traditional charge redistribution structure;

Detailed ways

The present invention firstly proposes successive approximation ADC ultra-low power consumption capacitor arrays: comprising two groups of (N-2)-bit binary capacitor arrays respectively connected to the two input terminals of the comparator, each group of (N-2)-bit binary capacitor arrays passes The switch array is connected to the voltage references V _ref , V _cm , Gnd; each (N-2)-bit binary capacitor array is composed of capacitors C ₀ , C ₁ , C ₂ , ... C _N-2 , where N is a natural number; One end of the capacitors C ₀ , C ₁ , C ₂ , ... C _N-2 of the first group (N-2)-bit binary capacitor array is respectively connected to the differential input signal V _ip , and the other end of each capacitor is passed through the switch array respectively. The switch of the switch is connected to the voltage reference V _ref , V _cm , Gnd; one end of the capacitors C ₀ , C ₁ , C ₂ , ... C _N-2 of the second (N-2)-bit binary capacitor array is respectively connected to the differential input The other end of the signal V _in is respectively connected to the voltage references V _ref , V _cm , Gnd through the switches in the switch array; the output end of the comparator is connected to the successive approximation logic control unit SARLogic, and according to the output of the comparator, the successive approximation logic control The unit SARLogic implements the logic control of the switch of the capacitor array under the action of the clock signal clk and soc, and generates the digital output B ₀ -B _N-1 of the ADC.

Wherein the above C ₀ =C ₁ , C _i =2C _i-1 , i=1˜N-2. The switch array connected to the first (N-2)-bit binary capacitor array is the first switch array, and the first switch array is composed of switches S _0p , S _1p , S _2p , ... S _(N-2)p . The switch array connected to the second (N-2)-bit binary capacitor array is the second switch array, and the second switch array is composed of switches S _0n , S _1n , S _2n , ... S _(N-2)n .

The logic control method based on the above successive approximation to the ADC ultra-low power consumption capacitor array is as follows:

(1) In the sampling stage, the switch array timing initialization technology is adopted, S _(N-2)n = S _(N-2)p = "1", S _(N-3)n = S _(N-4)n = ... S _1n = S _0n = "0", S _(N-3)p = S (N _{- 4)p} = ... S _1p = S _0p = "0", change S _{( N-2)} (S _(N-2)n or S _(N-2)p ), output the control signal S _(N-2) of the highest switch corresponding to the larger capacitor array connected by "1" to "0", and then compare the size of the capacitor array output again to generate the second digital output B _N-2 ; "1" and "0" respectively represent that the corresponding switch connects its corresponding capacitor to V _ref and Gnd;

(2) By adopting upper plate sampling and switch array logic timing initialization technology, no reference is needed to provide energy consumption in the process of generating the highest and second digital outputs; when generating the third digital output B _N-3 , If it is an up jump, the switch control signal of the capacitor array changes from "100...0" to "11/21/2...1/2", and the energy consumption is -C _N-2 V _ref ² /2; if it is a down jump, the capacitor array switch control signal changes from "100...0" to "1/200...0", and the energy consumption is also -C _N-2 V _ref ² /2; "1/2" means that the corresponding switch will The corresponding capacitor is connected to V _cm , V _cm =V _ref /2.

In the above method: after the first three digits of digital output B _N-1 -B _N-3 are generated, the capacitor array adopts a monotonic switching logic control mode in the subsequent conversion process, and only one capacitor is connected in each clock cycle The change. According to the difference of the second digital output B _N-2 , the change of the common mode output level of the capacitor array presents two trends:

1) If B _N-2 outputs logic 1, the capacitor array needs to jump up to generate the third output B _N-3 , and the common-mode output level of the capacitor array gradually approaches V _ref /2 during the successive approximation process;

2) If B _N-2 outputs logic 0, the capacitor array needs to undergo a down transition to generate the third bit output B _N-3 , and the common-mode output level of the capacitor array gradually approaches V _ref /4 during the successive approximation process.

Below in conjunction with accompanying drawing and embodiment the present invention is described in further detail:

Example

The successive approximation ADC ultra-low power consumption capacitor array of the present embodiment is as shown in Figure 2: comprises two groups of (N-2)-bit binary capacitor arrays that are respectively connected to the two input terminals of the comparator, each group (N-2)- The bit binary capacitor array is connected to the voltage reference V _ref , V _cm , Gnd through the switch array; each (N-2)-bit binary capacitor array is composed of capacitors C ₀ , C ₁ , C ₂ , ... C _N-2 connections, Among them, N is a natural number; one end of the capacitors C ₀ , C ₁ , C ₂ , ... C _N-2 of the first (N-2)-bit binary capacitor array is respectively connected to the differential input signal V _ip , and the other end of each capacitor Connect to the voltage references V _ref , V _cm , Gnd through the switches in the switch array respectively; the capacitors C ₀ , C ₁ , C ₂ , ... C _N-2 of the second (N-2)-bit binary capacitor array One end is respectively connected to the differential input signal V _in , and the other end is respectively connected to voltage references V _ref , V _cm , Gnd through the switches in the switch array; the output end of the comparator is connected to the successive approximation logic control unit SARLogic, and according to the output of the comparator, the The SARLogic realizes the logic control of the switch of the capacitor array under the action of the clock signal clk and soc, and generates the digital output B ₀ -B _N-1 of the ADC. .

Where C ₀ =C ₁ , C _i =2C _i-1 , i=1˜N-2; reference voltage V _cm =V _ref /2. The switch array connected to the first (N-2)-bit binary capacitor array is the first switch array, and the first switch array is composed of switches S _0p , S _1p , S _2p , ... S _(N-2)p . The switch array connected to the second (N-2)-bit binary capacitor array is the second switch array, and the second switch array is composed of switches S _0n , S _1n , S _2n , ... S _(N-2)n .

In the above-mentioned differential capacitor array structure, the upper plate of the capacitor is used for sampling. After the sampling, the comparator compares V _ip and V _in to directly generate the highest output B _N-1 . This process does not consume energy, and because The highest bit is generated directly after sampling, which reduces the scale of the capacitor array, thereby reducing power consumption, chip area and cost.

In the above differential capacitor array structure, in the sampling stage, the switch array timing initialization technology is adopted, S _(N-2)n = S _(N-2)p = "1", S _(N-3)n = S _{(N -4)n} =... S _1n = S _0n = "0", S _(N-3)p = S _(N-4)p = ... S _1p = S _0p = "0", according to B _N-1 The result changes the value of S _(N-2) (S _(N-2)n or S _(N-2)p ), and outputs the control signal of the highest bit switch corresponding to the larger capacitor array (S _{(N-2 )n} or S _(N-2)p ) from "1" to "0", as shown in Figure 3a, and then compare the size of the output of the capacitor array again to generate the second digital output B _N-2 , the process is also No energy consumption.

In the capacitor array structure above, by adopting upper plate sampling and switch array logic timing initialization technology, no reference is needed to provide energy consumption during the process of generating the highest bit and the second bit digital output. In addition, when generating the third digital output B _N-3 , if it is an up-transition, the switch control signal of the capacitor array changes from "100...0" to "11/21/2...1/ 2", the energy consumption is -C _N-2 V _ref ² /2; if it is a down-transition, the switch control signal of the capacitor array changes from "100...0" to "1/200...0" , the energy consumption is also -C _N-2 V _ref ² /2. By adopting this new logic control method, the generation of the third digital output B _N-3 does not require the reference to provide energy consumption. FIG. 3 shows the specific conversion process and corresponding energy consumption of the 4-bit embodiment of the present invention.

In the capacitor array structure above, after the first three digital outputs (B _N-1 -B _N-3 ) are generated, the capacitor array adopts a monotonic switching logic control mode in the subsequent conversion process, and only The connection relationship of a capacitor changes, which not only simplifies the logic control sequence, but also reduces power consumption.

In the above capacitor array structure, according to the difference of the second digital output B _N-2 , the change of the common mode output level of the capacitor array presents two trends: 1) If B _N-2 is logic 1, the capacitor array needs to generate Jump up (shown as A and D in Figure 3) to generate the third bit output B _N-3 , and the common-mode output level of the capacitor array gradually approaches V _ref /2 during the successive approximation process; 2) If B _{N- 2} is logic 0, and the capacitor array needs to undergo a downward transition (as shown by B and C in Figure 3) to generate the third bit output B _N-3 , and the common-mode output level of the capacitor array gradually approaches V _ref during the successive approximation process /4. Fig. 4 compares the capacitor array output waveform of the 4-bit embodiment of the present invention and the traditional monotone switching mode, compared with the traditional monotone switching mode, the common mode output of the capacitor array provided by the present invention (that is: the common mode input of the comparator) The level change range is significantly reduced, which can effectively reduce the input offset error caused by the common mode level change of the comparator, which is beneficial to the low power consumption optimization design of the comparator.

In the capacitor array structure above, the new logic control method adopted can effectively reduce the extra power consumption caused by parasitic capacitors. FIG. 5 shows a schematic diagram of an embodiment of the 4-bit invention. There are parasitic capacitances between the upper and lower plates of the capacitor and the substrate ("0"). The parasitic capacitance between the lower plate and the substrate is directly connected to the reference through the switch. During the capacitor switching process, the charge of the parasitic capacitance Discharging consumes additional energy. Among them, the highest capacitor C _N-2 has the largest weight, and its parasitic capacitance consumes the most energy. By optimizing the logic timing of the capacitor array switch, it is guaranteed that the entire A During the /D conversion process, the highest bit capacitor C _N-2 only undergoes a monotonous downward jump ("1"→"0" or "1"→"1/2"), avoiding the impact on its parasitic capacitance (2C _pb ) Repeated charging, thus effectively reducing the power consumption of parasitic capacitors.

In the traditional charge redistribution SARADC structure shown in Fig. 1, the lower plate sampling of the capacitor and the traditional successive approximation method are adopted, C ₀ , C ₁ , C ₂ , ... C _N-1 form a binary capacitor array, C ₀ =C ₁ , C _i =2C _i-1 , i=1~N-1; S _ip , S _in (i=0~N-1) are capacitor array switches; V _ip and V _in are differential input signals; V _ref is the voltage reference. The entire capacitor array is not only large in scale, but also has high area, power consumption and process costs, and the large-scale capacitor array leads to a large input capacitance of the SARADC, which limits the overall working speed.

Table 1 Comparison (10-bitADC) between the present invention and traditional charge redistribution structure

Taking 10-bitADC as an example in the above table, the present invention is compared with the traditional charge redistribution structure in terms of capacitor array scale, number of switches, and capacitor array energy consumption, wherein C _pt represents the upper plate-to-substrate of the entire capacitor array The sum of the parasitic capacitances, C _pb represents the parasitic capacitance of the lower plate of the unit capacitance to the substrate, and C _tot represents the total capacitance value of the entire capacitor array. The capacitor array structure provided by the present invention has obvious advantages. The capacitor array scale and the number of switches are only 25% and 38.5% of the traditional charge redistribution structure. 1.2% of the structure, in the case of considering the energy consumption of parasitic capacitance, taking C _pt =0.1C _tot , C _pb =0.15C as an example, the energy consumption of the capacitor array provided by the present invention is only 1.4% of the traditional charge redistribution structure . See Figure 6 for details.

Claims (7)

1. a successive approximation analog to digital C super low-power consumption capacitor array, it is characterized in that, comprise (N-2)-bit binary capacitor array that two groups are connected to two inputs of comparator, often group (N-2)-bit binary capacitor array connects voltage reference V by switch arrays _ref, V _cm, Gnd; Often group (N-2)-bit binary capacitor array is by electric capacity C ₀, C ₁, C ₂... C _n-2connect to form, wherein N is natural number; The electric capacity C of first group of (N-2)-bit binary capacitor array ₀, C ₁, C ₂... C _n-2one end connect differential input signal V respectively _ip, the other end of each electric capacity is connected to voltage reference V respectively by the switch in switch arrays _ref, V _cm, Gnd; The electric capacity C of second group of (N-2)-bit binary capacitor array ₀, C ₁, C ₂... C _n-2one end connect differential input signal V respectively _in, the other end is connected to voltage reference V respectively by the switch in switch arrays _ref, V _cm, Gnd; The output of comparator connects Approach by inchmeal logic control element SARLogic, according to the output of comparator, described Approach by inchmeal logic control element SARLogic realizes the logic control to capacitor array switch under the effect of clock signal clk and soc, and the numeral producing ADC exports B ₀-B _n-1.

2. successive approximation analog to digital C super low-power consumption capacitor array according to claim 1, is characterized in that, C ₀=C ₁, C _i=2C _i-1, i=1 ~ N-2.

3. successive approximation analog to digital C super low-power consumption capacitor array according to claim 1, is characterized in that, the switch arrays be connected with first group of (N-2)-bit binary capacitor array are the first switch arrays, and the first switch arrays are by switch S _0p, S _1p, S _2p... S _{(N-2) p}composition.

4. successive approximation analog to digital C super low-power consumption capacitor array according to claim 1, is characterized in that, the switch arrays be connected with second group of (N-2)-bit binary capacitor array are second switch array, and second switch array is by switch S _0n, S _1n, S _2n... S _{(N-2) n}composition.

5. a logic control method for successive approximation analog to digital C super low-power consumption capacitor array described in claim 1-4 any one, is characterized in that:

(1) in sample phase, switch arrays sequential initialization technique is taked, S _{(N-2) n}=S _{(N-2) p}=" 1 ", S _{(N-3) n}=S _{(N-4) n}=... S _1n=S _0n=" 0 ", S _{(N-3) p}=S _{(N-4) p}=... S _1p=S _0p=" 0 ", according to B _n-1result change S _(N-2)(S _{(N-2) n}or S _{(N-2) p}) value, export the control signal S of the larger highest order switch corresponding to capacitor array _(N-2)be connected to " 0 " by " 1 ", and then again compare the size of capacitor array output, produce second-order digit and export B _n-2; " 1 " and " 0 " represents respective switch respectively and the electric capacity corresponding to it is connected to V _refand Gnd;

(2) by adopting top crown sampling and switch arrays logical sequence initialization technique, in the process producing highest order and second-order digit output, benchmark is not needed to provide energy consumption; B is exported in generation the 3rd bit digital _n-3time, if upper saltus step, capacitor array switch controlling signal is become " 11/21/2 ... 1/2 " by " 100 ... 0 ", and energy consumption is-C _n-2v _ref ²/ 2; If lower saltus step, capacitor array switch controlling signal is become " 1/200 ... 0 " by " 100 ... 0 ", and energy consumption is also-C _n-2v _ref ²/ 2; " 1/2 " represents respective switch and the electric capacity corresponding to it is connected to V _cm, V _cm=V _ref/ 2.

6. logic control method according to claim 5, is characterized in that, exports B in the numeral producing front three _n-1-B _n-3afterwards, in follow-up transfer process, capacitor array takes dull switch logic control mode, only has the change of an electric capacity generation annexation in each clock cycle.

7. logic control method according to claim 5, is characterized in that, exports B according to second-order digit _n-2difference, the change of the common mode output level of capacitor array presents two kinds of trend:

1) if B _n-2output logic 1, capacitor array needs that upper saltus step occurs and exports B to produce the 3rd _n-3, capacitor array common mode output level approaches V gradually in Approach by inchmeal process _ref/ 2;

2) if B _n-2output logic 0, capacitor array needs that lower saltus step occurs and exports B to produce the 3rd _n-3, capacitor array common mode output level approaches V gradually in Approach by inchmeal process _ref/ 4.