CN105185835A - Thin film transistor and manufacturing method thereof, array substrate, and display device - Google Patents

Abstract

The invention discloses a thin film transistor and a manufacturing method thereof, an array substrate, and a display device, which are used for reducing a mask plate, saving production cost and increasing aperture opening ratio of pixels. The thin film transistor comprises a substrate, a grid, a grid insulating layer, an active layer, a source and a drain which are arranged on the substrate, wherein the source comprises a first source in contact with the active layer and a second source arranged on the first source; the drain comprises a first drain in contact with the active layer and a second drain arranged on the first drain; the first source and the first drain are made of conductive polymers; and the second source and the second drain are made of metal.

Description

A kind of thin film transistor and its manufacturing method, array substrate, display device

technical field

The invention relates to the field of display technology, in particular to a thin film transistor and a manufacturing method thereof, an array substrate, and a display device.

Background technique

With the continuous development of semiconductor display technology, technologies such as high refresh rate, high resolution (PixelPerInch, PPI), array substrate line driver circuit (GateDriverOnArray, GOA) emerge in an endless stream. These technologies have higher and higher requirements on the performance of thin film transistors (ThinFilm Transistor, TFT), especially the mobility of the active layer.

The oxide active layer has a high mobility, and the carrier mobility of the oxide TFT is as high as 10cm ² /Vs, which is about 10 times that of the amorphous silicon TFT. Therefore, the oxide TFT is currently a research hotspot in the field of display technology. However, during the etching process of the source electrode and the drain electrode, the oxide active layer is easily corroded and damaged by the etching solution. In order to solve this problem in the prior art, an etching stop layer structure is usually provided in the oxide TFT.

Specifically, as shown in FIG. 1 , firstly, deposit a layer of metal film on the base substrate 10, fabricate the gate 11 through a patterning process, fabricate a gate insulating layer 12 on the gate 11, and form a gate insulating layer 12 on the gate insulating layer 12. Fabricate the oxide active layer 13 by a patterning process, the material of the oxide active layer 13 is indium gallium zinc oxide (IGZO), on the oxide active layer 13, fabricate an etch barrier layer 14 by a patterning process, during etching On the barrier layer 14, a source electrode 15 and a drain electrode 16 are fabricated by a patterning process, the source electrode 15 is connected to the oxide active layer 13 through a via hole penetrating the etching barrier layer 14, and the drain electrode 16 is connected to the oxide active layer 13 through a via hole penetrating the etching barrier layer 14. The holes are connected to the oxide active layer 13 . Wherein, the patterning process described above includes photoresist coating, exposure, development, etching and part or all of photoresist removal processes.

In summary, although the etching barrier layer in the prior art can prevent the etching solution from eroding the oxide active layer, it needs to add a mask plate, and the process is complicated; at the same time, the setting of via holes penetrating the etching barrier layer increases. The area of the TFT is reduced, making it difficult to make the TFT small. Since the area occupied by the TFT is large, the aperture ratio of the pixel is reduced.

Contents of the invention

Embodiments of the present invention provide a thin film transistor and its manufacturing method, an array substrate, and a display device, which are used to reduce one mask plate, save production capacity, and increase the aperture ratio of pixels.

A thin film transistor provided by an embodiment of the present invention includes a substrate, a gate located on the substrate, a gate insulating layer, an active layer, and a source and a drain;

The source includes a first source in contact with the active layer, and a second source on the first source;

The drain includes a first drain in contact with the active layer, and a second drain on the first drain;

Wherein, the material of the first source and the first drain is conductive polymer; the material of the second source and the second drain is metal.

The thin film transistor of the array substrate provided by the embodiment of the present invention includes a base substrate, a gate located on the base substrate, a gate insulating layer, an active layer, and a source and a drain; the source includes a The first source, the second source on the first source; the drain includes a first drain in contact with the active layer, and the second drain on the first drain; wherein, the first source and The material of the first drain is conductive polymer; the material of the second source and the second drain is metal. Compared with the prior art, the thin film transistor in the embodiment of the present invention does not need to be provided with an etching stopper layer, which can reduce a mask and save production capacity; because the first source and the first drain in the embodiment of the present invention The material is a conductive polymer, and compared with the prior art, no via hole is required, and the aperture ratio of the pixel can be increased.

Preferably, the conductive polymer is polyacetylene, or polythiophene, or polypyrrole, or polyaniline.

Preferably, the metal is a single-layer metal of copper, molybdenum, aluminum, and neodymium, or a composite metal composed of copper, molybdenum, aluminum, and neodymium.

Preferably, it further includes a passivation layer on the second source and the second drain.

Preferably, the material of the passivation layer is a silicon oxide layer, or a silicon nitride layer, or a composite layer of silicon oxide and silicon nitride.

An embodiment of the present invention also provides an array substrate, which includes the above-mentioned thin film transistor.

An embodiment of the present invention also provides a display device, which includes the above-mentioned array substrate.

An embodiment of the present invention also provides a method for manufacturing a thin film transistor, including a method for manufacturing a gate, a gate insulating layer, an active layer, and a source and a drain on a substrate, wherein the source includes a The first source in contact with the active layer is located on the second source on the first source; the drain includes a first drain in contact with the active layer and is located on the first drain the second drain on the pole;

The method for making source and drain includes:

sequentially depositing a conductive polymer layer and a metal layer on the active layer;

The second source and the second drain are formed by patterning the metal layer, and the first source and the first drain are formed by patterning the conductive polymer layer.

Preferably, the metal layer is patterned to form the second source and the second drain, and the conductive polymer layer is patterned to form the first source and the first drain, specifically including:

Coating photoresist on the metal layer, exposing and developing the photoresist, retaining the light at the positions where the first source, the first drain, the second source and the second drain need to be formed Engraving;

Removing the exposed metal layer by first etching;

removing the exposed conductive polymer layer by second etching, the first etching being wet etching, and the second etching being dry etching;

The remaining photoresist is removed to form a first source, a first drain, a second source and a second drain.

Preferably, the method further includes forming a passivation layer on the base substrate formed with the first source, the first drain, the second source and the second drain through a patterning process.

Description of drawings

FIG. 1 is a schematic structural diagram of a thin film transistor in the prior art;

FIG. 2 is a schematic structural diagram of a thin film transistor provided by an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of another thin film transistor provided by an embodiment of the present invention;

FIG. 4 is a flowchart of a method for manufacturing a source and a drain of a thin film transistor according to an embodiment of the present invention;

5-8 are schematic structural diagrams of different stages in the manufacturing process of a thin film transistor provided by Embodiment 1 of the present invention;

9-11 are schematic structural diagrams of different stages in the manufacturing process of a thin film transistor provided by Embodiment 2 of the present invention;

FIG. 12 is a schematic structural diagram of another thin film transistor provided by Embodiment 2 of the present invention.

Detailed ways

Embodiments of the present invention provide a thin film transistor and its manufacturing method, an array substrate, and a display device, which are used to reduce one mask plate, save production capacity, and increase the aperture ratio of pixels.

In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The thin film transistor and its manufacturing method provided by specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

As shown in FIG. 2 , a specific embodiment of the present invention provides a thin film transistor, including a base substrate 10, a gate 11 located on the base substrate 10, a gate insulating layer 12, an active layer 13, and a source 24 and Drain electrode 25, source electrode 24 comprises the first source electrode 241 contacting with active layer 13, is positioned at the second source electrode 242 on the first source electrode 241; Drain electrode 25 comprises the first drain electrode contacting with active layer 13 251, the second drain 252 located on the first drain 251; wherein, the material of the first source 241 and the first drain 251 is a conductive polymer; the material of the second source 242 and the second drain 252 is Metal.

Preferably, the first source electrode 241 and the first drain electrode 251 in the specific embodiment of the present invention are polyacetylene, or polythiophene, or polypyrrole, or polyaniline. The specific embodiment of the present invention does not limit the specific materials of the first source electrode 241 and the first drain electrode 251. In the specific implementation process, it can also be other types of conductive polymers, as long as it can resist the engraving when etching metal later. Any conductive polymer that acts as a barrier to the etchant is acceptable.

Preferably, the second source electrode 242 and the second drain electrode 252 in the specific embodiment of the present invention are single-layer metals of copper (Cu), molybdenum (Mo), aluminum (Al), neodymium (Nd), or are made of Cu , Mo, Al, Nd composite metal. The specific embodiment of the present invention does not limit the specific materials of the second source 242 and the second drain 252. During the specific implementation process, they can also be other types of single-layer metal or composite metal. Preferably, the second source 242 and the second drain 252 are made of the same material as the gate 11 .

In the actual production process, when the material of the second source electrode 242 and the second drain electrode 252 in the specific embodiment of the present invention is copper, the first source electrode 241 and the first drain electrode 251 in the specific embodiment of the present invention can be Diffusion of copper into active layer 13 is prevented.

As shown in FIG. 3 , the thin film transistor in the specific embodiment of the present invention further includes a passivation layer 31 on the second source 242 and the second drain 252 . The passivation layer 31 can protect the active layer 13 , the second source 242 and the second drain 252 . In the specific embodiment of the present invention, a via hole 32 penetrating through the passivation layer 31 is provided in the passivation layer 31, and the setting of the via hole 32 can make the pixel electrode fabricated subsequently contact the second drain electrode 252, so as to input signals to the pixel electrode. .

Preferably, the material of the passivation layer 31 in the specific embodiment of the present invention is a silicon oxide (SiO2) layer, or a silicon nitride (SiN) layer, or a composite layer composed of SiO2 and SiN, and the specific embodiment of the present invention does not The material of the passivation layer 31 is not specifically limited.

The specific embodiment of the present invention also provides an array substrate, which includes the above-mentioned thin film transistor provided by the specific embodiment of the present invention. Compared with the prior art, the thin film transistor provided by the specific embodiment of the present invention does not need to be etched. The barrier layer can save production capacity and increase the aperture ratio of pixels. Therefore, the array substrate provided by the specific embodiment of the present invention can also save production capacity and increase the aperture ratio of pixels.

The specific embodiment of the present invention also provides a display device, the display device includes the array substrate provided by the specific embodiment of the present invention, and the display device can be a liquid crystal panel, a liquid crystal display, a liquid crystal TV, an organic light emitting diode (OrganicLightEmittingDiode, OLED) panel , OLED display, OLED TV or electronic paper and other display devices.

As shown in FIG. 4, a specific embodiment of the present invention also provides a method for manufacturing a thin film transistor, including a method for manufacturing a gate, a gate insulating layer, an active layer, and a source and a drain on a base substrate. The source electrode includes a first source electrode in contact with the active layer, and a second source electrode located on the first source electrode; the drain electrode includes a first drain electrode in contact with the active layer, located on a second drain on the first drain;

The method for making source and drain includes:

S401, sequentially depositing a conductive polymer layer and a metal layer on the active layer;

S402 , forming a second source and a second drain on the metal layer by using a patterning process, and forming a first source and a first drain on the conductive polymer layer by using a patterning process.

The method for fabricating a thin film transistor according to a specific embodiment of the present invention will be described in detail below in conjunction with the accompanying drawings.

Embodiment one:

As shown in FIG. 5 , first deposit a layer of metal thin film on the base substrate 10, and then use a patterning process on the metal thin film to make the metal thin film form a gate 11. The specific process of making the gate 11 is the same as that of the prior art. I won't go into details here. The base substrate 10 in the specific embodiment of the present invention is preferably a glass substrate. Of course, in practical applications, the base substrate 10 may also be other types of substrates such as ceramic substrates. The metal film deposited in the specific embodiment of the present invention can be a single-layer metal film of Cu, Mo, Al, Nd, or a composite metal film composed of Cu, Mo, Al, Nd. In a specific production process, it can also be For other single-layer metal films or composite metal films, the specific embodiment of the present invention does not limit the specific material of the metal film. The patterning process in the specific embodiment of the present invention includes photoresist coating, exposure, development, etching and part or all processes of photoresist removal.

Next, the gate insulating layer 12 is fabricated on the base substrate 10 with the gate 11 fabricated. The specific process of fabricating the gate insulating layer 12 in the specific embodiment of the present invention is the same as that of the prior art, and will not be repeated here. The gate insulating layer 12 produced by the specific embodiment of the present invention is a silicon oxide layer, or a silicon nitride layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer. Specific materials are limited.

Next, the active layer 13 is fabricated on the base substrate with the gate insulating layer 12 through a patterning process. The specific process of fabricating the active layer 13 in the specific embodiment of the present invention is the same as that of the prior art, and will not be repeated here. Preferably, the active layer 13 in the specific embodiment of the present invention is an oxide active layer, and the specific material is indium gallium zinc oxide (IGZO). The specific embodiment of the present invention does not limit the specific material of the active layer.

As shown in Figure 6, a conductive polymer layer 61 and a metal layer 62 are sequentially deposited on the active layer 13. The deposition method of the metal layer 62 can be a magnetron sputtering method or a thermal evaporation method. Of course, in the actual production process Other deposition methods are possible. The deposition method of the conductive polymer layer 61 may be spin coating, drop coating, spray coating, inkjet printing, and of course, other deposition methods may also be used in the actual production process. Afterwards, a photoresist 60 is coated on the metal layer 62, and the photoresist is exposed and developed to only retain the light at the positions where the first source, the first drain, the second source and the second drain need to be formed. Resist, remove the photoresist at the remaining positions, the photoresist 60 coated in the specific embodiment of the present invention is a positive photoresist, certainly, in the actual production process, the photoresist coated can also be a negative photoresist. permanent photoresist.

As shown in Figure 7, the exposed metal layer is removed by the first etching. In the specific embodiment of the present invention, the first etching is wet etching. After the wet etching, the metal layer in the specific embodiment of the present invention is exposed. Conductive polymer layer 61 . During the wet etching process, the conductive polymer layer 61 has a blocking effect on the etching solution, effectively protecting the active layer 13 . The specific embodiment of the present invention protects the active layer 13 from being corroded by the etching solution through the provision of the conductive polymer layer 61 , and does not need to provide an etching stopper layer.

As shown in Figure 8, the exposed conductive polymer layer is removed by etching for the second time. In the specific embodiment of the present invention, the second etching is dry etching, because dry etching is used when etching the conductive polymer layer. Therefore, the active layer 13 will not be corroded. Finally, the remaining photoresist is removed to form the first source 241 , the first drain 251 , the second source 242 and the second drain 252 , as shown in FIG. 2 .

Embodiment two:

As shown in FIG. 9, firstly, the gate 11 and the gate insulating layer 12 are fabricated on the base substrate 10. The method for fabricating the gate 11 and the gate insulating layer 12 in the second embodiment of the present invention is the same as that in the first embodiment, and is not mentioned here. Let me repeat. Next, the oxide semiconductor layer 90, the conductive polymer layer 61 and the metal layer 62 are sequentially deposited on the gate insulating layer 12. The deposition method of the oxide semiconductor layer 90 can be a magnetron sputtering method or a thermal evaporation method. Of course, in Other deposition methods may also be used in the actual production process.

Afterwards, a photoresist is coated on the metal layer 62, and the photoresist is exposed and developed using a halftone mask or a gray tone mask to form a photoresist completely removed area, a photoresist partially reserved area, and a photoresist. Resist completely reserved area, the photoresist fully reserved area corresponds to the area where the first source, the first drain, the second source and the second drain are formed, and the photoresist partially reserved area corresponds to the channel where the active layer is formed The region where the photoresist is completely removed corresponds to other regions on the substrate. The half-tone mask or the gray-tone mask includes a light-shielding area, a full light-transmitting area and a partial light-transmitting area. The photoresist is illustrated by taking the positive photoresist as an example. The completely removed area of the photoresist corresponds to the fully transparent area of the halftone mask or the gray tone mask, and the partially reserved area of the photoresist corresponds to the halftone mask. Part of the light-transmitting area of the stencil or the gray-tone mask, and the complete reserved area of the photoresist corresponds to the light-shielding area of the half-tone mask or the gray-tone mask. Of course, the photoresist in the specific embodiments of the present invention is also It can be a negative photoresist. When the photoresist is a negative photoresist, the completely removed area of the photoresist corresponds to the light-shielding area of the halftone mask or the gray tone mask, and the completely reserved area of the photoresist Corresponds to the fully transparent area of a halftone mask or a gray tone mask.

The oxide semiconductor layer 90 , the conductive polymer layer 61 and the metal layer 62 corresponding to the photoresist completely removed region are removed by wet etching to form the active layer 13 , as shown in FIG. 10 . Next, remove the photoresist in the photoresist partially reserved area, and only the photoresist 100 in the photoresist completely reserved area is left at this time. The specific embodiment of the present invention removes the photoresist in the photoresist partially reserved area by ashing method. The resist exposes the metal layer 62 in the channel region, and removes the exposed metal layer by wet etching. During the wet etching process, the conductive polymer layer 61 has a blocking effect on the etching solution, effectively protecting the active layer 13 . In Embodiment 1 of the present invention, a mask plate is required to fabricate the active layer 13 . In Embodiment 2 of the present invention, a separate mask plate is not required to fabricate the active layer 13 , which can reduce production costs.

As shown in FIG. 11 , the exposed conductive polymer layer is then removed by dry etching. Since dry etching is used when etching the conductive polymer layer, the active layer 13 will not be corroded. Finally, the remaining photoresist is removed to form the first source 241 , the first drain 251 , the second source 242 and the second drain 252 . The specific embodiment of the present invention removes the remaining photoresist by stripping.

Preferably, the method for manufacturing a thin film transistor according to the specific embodiment of the present invention further includes fabricating a thin film transistor by a patterning process on the base substrate on which the first source 241, the first drain 251, the second source 242, and the second drain 252 are formed. The passivation layer 31 is shown in FIG. 3 and FIG. 12 . The specific process of making the passivation layer 31 is the same as that of the prior art, and will not be repeated here.

In summary, specific embodiments of the present invention provide a thin film transistor and its manufacturing method, an array substrate, and a display device. The thin film transistor includes a base substrate, a gate electrode, a gate insulating layer, and an active layer on the and a source and a drain; the source includes a first source in contact with the active layer, and a second source on the first source; the drain includes a first drain in contact with the active layer, located on the first The second drain on the drain; wherein, the material of the first source and the first drain is conductive polymer; the material of the second source and the second drain is metal. Compared with the prior art, the thin film transistor in the specific embodiment of the present invention does not need to be provided with an etching stopper layer, so one mask plate can be reduced and production capacity can be saved; since the first source and the first The material of the drain electrode is a conductive polymer, and compared with the prior art, no via hole is required, and the aperture ratio of the pixel can be increased. In addition, in the specific embodiment of the present invention, the first source electrode and the first drain electrode are in contact with the active layer, and the material of the first source electrode and the first drain electrode is a conductive polymer, and the conductive polymer can act on the etching solution. It has a blocking effect and can protect the active layer from being corroded by the etching solution.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and equivalent technologies thereof, the present invention also intends to include these modifications and variations.

Claims (10)

1. A thin film transistor, comprising a base substrate, a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode positioned on the base substrate, characterized in that, The source includes a first source in contact with the active layer, and a second source on the first source; The drain includes a first drain in contact with the active layer, and a second drain on the first drain; Wherein, the material of the first source and the first drain is conductive polymer; the material of the second source and the second drain is metal. 2. The thin film transistor according to claim 1, wherein the conductive polymer is polyacetylene, or polythiophene, or polypyrrole, or polyaniline. 3 . The thin film transistor according to claim 1 , wherein the metal is a single-layer metal of copper, molybdenum, aluminum, and neodymium, or a composite metal composed of copper, molybdenum, aluminum, and neodymium. 4. The thin film transistor according to claim 1, further comprising a passivation layer on the second source and the second drain. 5. The thin film transistor according to claim 4, wherein the material of the passivation layer is a silicon oxide layer, or a silicon nitride layer, or a composite layer of silicon oxide and silicon nitride. 6. An array substrate, characterized in that the array substrate comprises the thin film transistor according to any one of claims 1-5. 7. A display device, characterized in that the display device comprises the array substrate according to claim 6. 8. A method for manufacturing a thin film transistor, comprising a method for manufacturing a gate, a gate insulating layer, an active layer, a source electrode and a drain electrode on a base substrate, wherein the source electrode includes a A first source electrode contacted by the source layer, a second source electrode located on the first source electrode; the drain electrode includes a first drain electrode in contact with the active layer, and a second source electrode located on the first drain electrode second drain; The method for making source and drain includes: sequentially depositing a conductive polymer layer and a metal layer on the active layer; The second source and the second drain are formed by patterning the metal layer, and the first source and the first drain are formed by patterning the conductive polymer layer. 9. The method according to claim 8, wherein the second source and the second drain are formed by patterning the metal layer, and the first source is formed by patterning the conductive polymer layer. pole and the first drain, specifically including: Coating photoresist on the metal layer, exposing and developing the photoresist, retaining the light at the positions where the first source, the first drain, the second source and the second drain need to be formed Engraving; Removing the exposed metal layer by first etching; removing the exposed conductive polymer layer by second etching, the first etching being wet etching, and the second etching being dry etching; The remaining photoresist is removed to form a first source, a first drain, a second source and a second drain. 10. The method according to claim 9, characterized in that, the method further comprises forming the first source, the first drain, the second source and the second drain on the base substrate through a patterning process Make a passivation layer.