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CN105185703A - Wafer edge leveling method - Google Patents

Wafer edge leveling method Download PDF

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Publication number
CN105185703A
CN105185703A CN201410273168.XA CN201410273168A CN105185703A CN 105185703 A CN105185703 A CN 105185703A CN 201410273168 A CN201410273168 A CN 201410273168A CN 105185703 A CN105185703 A CN 105185703A
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China
Prior art keywords
exposing unit
incomplete
exposure
scanned
wafer
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CN201410273168.XA
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CN105185703B (en
Inventor
叶序明
宣胤杰
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Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
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Priority to CN201410273168.XA priority Critical patent/CN105185703B/en
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  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

Provided is a wafer edge leveling method. A plurality of exposure units are formed on a wafer. Non-complete exposure units which can carry out horizontal correction automatically in a subsequent exposure process are determined through a system in advance, then the non-complete exposure units above the central line of the wafer are scanned from bottom to top, and the non-complete exposure units behind the central line of the wafer are scanned from top to bottom; finally, an ideal leveling way for problematic exposure units is obtained. Through the method, wafer edge non-complete exposure unit defocus risks can be reduced furthest. The product yield is raised.

Description

A kind of method that crystal round fringes is levelling
Technical field
The present invention relates to microelectronic, particularly relate to a kind of method that crystal round fringes is levelling.
Background technology
Wafer levelling (leveling) operation principle is illustrated in fig. 2 shown below (mainly to refer to step-by-step scanning photo-etching device scanner) in current semiconductor lithography exposure technology, while X-direction stepping, Y-direction scans, and the direction that the T1-T32 of simple following Fig. 3 is followed in scanning replaces way, the scanning direction of namely adjacent exposing unit is contrary and replaces down, this way is absolutely in most cases no problem, but to exposing unit (shot) size of specific products, tool parameters sets, board performance, and during the combination of product substrate thickness changing condition etc., can levelling problem be there is at the incomplete shot that partly itself automatically can do level correction and out of focus occur, and then affect product yield.
Chinese patent (CN101482705) describes a kind of mask aligner scan exposure system, the cylindrical mirror, varifocal mirror group, homogenizer, coupling light group, mask plate, object lens, the work stage that comprise light source and be arranged in order along the light path that light source outgoing beam is formed, between described varifocal mirror group and homogenizer, be provided with Beam rotation mirror group, described Beam rotation mirror group is made up of some groups of optical elements.During scan exposure, first to after the exposure of exposure field sector scanning, described Beam rotation mirror group is moved in described light path, again exposure field sector scanning is exposed, remove described Beam rotation mirror group after completing scan exposure, improve the dose uniformity of exposure field Y-direction, the dose uniformity of X-direction can be improved again, thus change the systematic function of exposure dose, improve the uniformity of lithographic line width.
Chinese patent (CN101750901A) describes a kind of scanning exposure method, comprise: by a mask and a substrate toward a direction relative movement, wherein this mask and this substrate are in the moving process of single fraction irradiation, there is relative velocities such as grade different at least two, with the irradiation area making this substrate one times expose, there is a desired size.
Above-mentioned two patents all do not record the technical characteristic about exposure scanning direction changes.
Summary of the invention
In view of the above problems, the invention provides a kind of levelling method of crystal round fringes.
The technical scheme that technical solution problem of the present invention adopts is:
The method that crystal round fringes is levelling, wherein, forms some complete exposing units and incomplete exposing unit on wafer, first prejudges out and self automatically can do the incomplete exposing unit of level correction in post-exposure process;
Then the above incomplete exposing unit of crystal circle center's line is scanned from bottom to top, crystal circle center's incomplete exposing unit of line the following stated is scanned from the top down;
Finally obtain the optimal levelling mode of problematic exposing unit.
Above-mentioned method, wherein, by the system made by exposure file, and in conjunction with the setting parameter of exposure bench, the layout of photoetching level figure of specific product and the size of described exposing unit, prejudge out and self automatically can do the incomplete exposing unit of level correction in post-exposure process.
Above-mentioned method, wherein, the setting parameter of described exposure bench comprises exposure bench and can not do defining of level correction scope to crystal round fringes.
Above-mentioned method, wherein, the planar graph of described complete exposing unit is rectangle.
Above-mentioned method, wherein, is scanned described incomplete exposing unit by step photo-etching machine.
Technique scheme tool has the following advantages or beneficial effect:
By said method, reduce the out of focus risk of the incomplete exposing unit of crystal round fringes to greatest extent, improve the yield of product.
Accompanying drawing explanation
With reference to appended accompanying drawing, to describe embodiments of the invention more fully.But, appended accompanying drawing only for illustration of and elaboration, do not form limitation of the scope of the invention.
Fig. 1 is the schematic diagram of crystal round fringes incomplete exposing unit exposure scanning direction;
Fig. 2 is the levelling schematic diagram of step-by-step scanning photo-etching device scanner wafer;
Fig. 3 is the schematic diagram of step-by-step scanning photo-etching device scanner exposure scanning direction.
Embodiment
The invention provides a kind of method that crystal round fringes is levelling, can be applicable to semiconductor lithography process field, preferably can be applicable to be more than or equal to 130nm, 90nm, 65/55nm, 45/40nm, 32/28nm and be less than or equal in the technique of the technology nodes such as 22nm, and apply in the technology module of the technology platforms such as Logic and Litho, when after use the method, reduce the risk of the incomplete exposing unit out of focus of crystal round fringes to greatest extent, improve product yield.
Core concept of the present invention is first prejudged by the incomplete exposing unit of prior art means to crystal round fringes, obtain some and self automatically can do the incomplete exposing unit of level correction in post-exposure process, then the incomplete exposing unit of more than crystal circle center's line this part is scanned from the bottom up, crystal circle center's line this part incomplete exposing unit is once scanned from top to bottom.
As shown in Figure 1, the method that a kind of crystal round fringes of the present invention is levelling, in the system that existing exposure file is made, some complete exposing units and incomplete exposing unit is formed on wafer, the planar graph of complete exposing unit is that rectangle is (as exposing unit 55, 56 etc.), by simple software function optimization, make it in conjunction with the setting of exposure bench parameter, size of specific product photoetching level pattern layout and exposing unit size etc., carry out automatic decision in advance to go out itself automatically can do the incomplete exposing unit of level correction in post-exposure process, automatic decision in advance can come for existing exposure system, also can have been come by artificial subjective judgement, wherein exposure bench parameter mainly board can not do defining of level correction scope to crystal round fringes.
The incomplete exposing unit of level correction itself automatically can be done for these, by exposing the optimization of scanning direction, reach improvement levelling, improve the target of product yield: obtain those scanning directions automatically doing the incomplete exposing unit of level correction from the larger-size scanning direction less to size of efficient frontier by by judgement, namely from the interior boundary scan of wafer, the out-of-flatness of crystal round fringes is reduced on the levelling impact of the incomplete exposing unit of correspondence or erroneous judgement.Wherein, shown in Fig. 1, ("+" expression scans from the top down, "-" represents scanning from bottom to top), wafer is formed a center line, incomplete exposing unit on crystal circle center's line is scanned from bottom to top, incomplete exposing unit below center line is scanned from the top down, ensures that the exposing unit of potential problems can obtain optimal levelling mode, to reduce out of focus risk to greatest extent like this.
Such as exposing unit 77 and 87,22 and 14, as according to former scan mode, be then single scanning from top to bottom, then exposing unit 77 and 87 just can not better be levelling, as single scanning from the bottom up, then exposing unit 22 and 14 just can not better be levelling, so in order to improve product yield, reducing crystal round fringes incomplete exposing unit out of focus risk to greatest extent, improving the exposure directions of wafer.
By illustrating and accompanying drawing, giving the exemplary embodiments of the ad hoc structure of embodiment, based on the present invention's spirit, also can do other conversion.Although foregoing invention proposes existing preferred embodiment, but these contents are not as limitation.
For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.

Claims (5)

1. the method that crystal round fringes is levelling, is characterized in that: on wafer, form some complete exposing units and incomplete exposing unit, first prejudges out and self automatically can do the incomplete exposing unit of level correction in post-exposure process;
Then the above incomplete exposing unit of crystal circle center's line is scanned from bottom to top, crystal circle center's incomplete exposing unit of line the following stated is scanned from the top down;
Finally obtain the optimal levelling mode of problematic exposing unit.
2. method according to claim 1, it is characterized in that: by the system made by exposure file, and in conjunction with the setting parameter of exposure bench, the layout of photoetching level figure of specific product and the size of described exposing unit, prejudge out and self automatically can do the incomplete exposing unit of level correction in post-exposure process.
3. method according to claim 2, is characterized in that: the setting parameter of described exposure bench comprises exposure bench and can not do defining of level correction scope to crystal round fringes.
4. method according to claim 1, is characterized in that: the planar graph of described complete exposing unit is rectangle.
5. method according to claim 1, is characterized in that: scanned described incomplete exposing unit by step photo-etching machine.
CN201410273168.XA 2014-06-18 2014-06-18 A kind of method that crystal round fringes are levelling Active CN105185703B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
CN201410273168.XA CN105185703B (en) 2014-06-18 2014-06-18 A kind of method that crystal round fringes are levelling

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CN105185703A true CN105185703A (en) 2015-12-23
CN105185703B CN105185703B (en) 2019-09-17

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109782545A (en) * 2017-11-15 2019-05-21 台湾积体电路制造股份有限公司 Exposure method and exposure device
CN110634729A (en) * 2019-09-12 2019-12-31 上海华力集成电路制造有限公司 Method for preventing surface film of incomplete exposure unit on edge of wafer from being stripped
CN110631518A (en) * 2019-09-25 2019-12-31 上海华力集成电路制造有限公司 Wafer surface flatness detection and incomplete exposure unit flatness detection compensation method
CN111103768A (en) * 2019-12-26 2020-05-05 华虹半导体(无锡)有限公司 Method for reducing poor focusing of wafer edge

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10270317A (en) * 1997-03-25 1998-10-09 Nikon Corp Method of scanning exposure
CN1416019A (en) * 2001-11-02 2003-05-07 株式会社东芝 Exposure method and exposure device
KR100678469B1 (en) * 2005-01-17 2007-02-02 삼성전자주식회사 Exposure Stage Wafer Stage and Wafer Parallelism Control Method Using the Same
KR100776496B1 (en) * 2006-12-04 2007-11-16 동부일렉트로닉스 주식회사 Wafer Leveling Method
CN101276151A (en) * 2008-05-14 2008-10-01 上海微电子装备有限公司 Method and device for measuring flatness of wafer surface
CN101482705A (en) * 2009-02-23 2009-07-15 上海微电子装备有限公司 Scanning exposure system and method of photo-etching machine
CN102625924A (en) * 2009-08-25 2012-08-01 株式会社尼康 Exposure method, exposure apparatus, and device manufacturing method
KR20120108615A (en) * 2011-03-25 2012-10-05 삼성전자주식회사 Method of measure an expose energy in photolithography system
CN103782238A (en) * 2011-08-31 2014-05-07 Asml荷兰有限公司 A method of determining focus corrections, lithographic processing cell and device manufacturing method

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10270317A (en) * 1997-03-25 1998-10-09 Nikon Corp Method of scanning exposure
CN1416019A (en) * 2001-11-02 2003-05-07 株式会社东芝 Exposure method and exposure device
KR100678469B1 (en) * 2005-01-17 2007-02-02 삼성전자주식회사 Exposure Stage Wafer Stage and Wafer Parallelism Control Method Using the Same
KR100776496B1 (en) * 2006-12-04 2007-11-16 동부일렉트로닉스 주식회사 Wafer Leveling Method
CN101276151A (en) * 2008-05-14 2008-10-01 上海微电子装备有限公司 Method and device for measuring flatness of wafer surface
CN101482705A (en) * 2009-02-23 2009-07-15 上海微电子装备有限公司 Scanning exposure system and method of photo-etching machine
CN102625924A (en) * 2009-08-25 2012-08-01 株式会社尼康 Exposure method, exposure apparatus, and device manufacturing method
KR20120108615A (en) * 2011-03-25 2012-10-05 삼성전자주식회사 Method of measure an expose energy in photolithography system
CN103782238A (en) * 2011-08-31 2014-05-07 Asml荷兰有限公司 A method of determining focus corrections, lithographic processing cell and device manufacturing method

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109782545A (en) * 2017-11-15 2019-05-21 台湾积体电路制造股份有限公司 Exposure method and exposure device
CN109782545B (en) * 2017-11-15 2021-06-08 台湾积体电路制造股份有限公司 Exposure method and exposure apparatus
CN110634729A (en) * 2019-09-12 2019-12-31 上海华力集成电路制造有限公司 Method for preventing surface film of incomplete exposure unit on edge of wafer from being stripped
CN110634729B (en) * 2019-09-12 2021-08-10 上海华力集成电路制造有限公司 Method for preventing surface film of incomplete exposure unit on edge of wafer from being stripped
CN110631518A (en) * 2019-09-25 2019-12-31 上海华力集成电路制造有限公司 Wafer surface flatness detection and incomplete exposure unit flatness detection compensation method
CN110631518B (en) * 2019-09-25 2021-06-15 上海华力集成电路制造有限公司 Wafer surface flatness detection and incomplete exposure unit flatness detection compensation method
CN111103768A (en) * 2019-12-26 2020-05-05 华虹半导体(无锡)有限公司 Method for reducing poor focusing of wafer edge
CN111103768B (en) * 2019-12-26 2022-06-07 华虹半导体(无锡)有限公司 Method for reducing poor focusing of wafer edge

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