CN105185307A - Pixel circuit - Google Patents
Pixel circuit Download PDFInfo
- Publication number
- CN105185307A CN105185307A CN201510612998.5A CN201510612998A CN105185307A CN 105185307 A CN105185307 A CN 105185307A CN 201510612998 A CN201510612998 A CN 201510612998A CN 105185307 A CN105185307 A CN 105185307A
- Authority
- CN
- China
- Prior art keywords
- pixel compensation
- compensation unit
- transistor
- capacitance value
- storage capacitance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims abstract description 7
- 230000008569 process Effects 0.000 claims abstract description 5
- 230000000694 effects Effects 0.000 claims description 9
- 238000013461 design Methods 0.000 abstract description 4
- 229920001621 AMOLED Polymers 0.000 abstract description 2
- 239000003990 capacitor Substances 0.000 abstract 1
- 230000004044 response Effects 0.000 description 5
- 230000009471 action Effects 0.000 description 4
- 101150076592 CST3 gene Proteins 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 101150037603 cst-1 gene Proteins 0.000 description 3
- -1 Cst2 Proteins 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 206010021703 Indifference Diseases 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention mainly relates to the field of displayers, and more particularly relates to the design of an AMOLED pixel circuit area. A pixel compensation array comprises multiple pixel compensation units. Any one column of pixel compensation units comprise first part pixel compensation units and second part pixel compensation units which are different in storage capacitance value so that difference of the voltage value achieved in the charging process of the storage capacitor of each pixel compensation unit in the same column of pixel compensation units can be reduced, and brightness difference of different areas can be improved.
Description
Technical field
The present invention, mainly about field of display, or rather, is the design about AMOLED pixel circuit region.
Background technology
In the prior art, if attempt the panel size of increase display to cater to consumer demand, then along with the increase of the size of screen, thing followed load also can be increasing, a drawback clearly can there is RCloading load effect from the bottom of screen to top, causes the data-signal of each zones of different of screen slightly different, the data-signal that bottom and top for example may occur in a row pixel is inconsistent, causes the display difference of screen.But prior art does not propose the counte-rplan of head it off, therefore while screen display panel size increases, be necessary to provide a kind of method to ensure can bottom of screen consistent with the display effect at top.
Summary of the invention
In one alternate embodiment, the invention provides a kind of image element circuit, and comprised pixel compensation array, described pixel compensation array comprises multiple pixel compensation unit; Wherein
The described pixel compensation unit of any row in described pixel compensation array, all comprises the different Part I pixel compensation unit of storage capacitance value and Part II pixel compensation unit.
Above-mentioned a kind of image element circuit, the described storage capacitance value of the first described pixel compensation unit in the described pixel compensation unit of any row is set to the described storage capacitance value lower than pixel compensation unit described in end.
Above-mentioned a kind of image element circuit, in the described pixel compensation unit of any row, makes the described storage capacitance value of each described pixel compensation unit progressively increase progressively successively by from the order of pixel compensation unit described in first described pixel compensation unit to end.
Above-mentioned a kind of image element circuit, the described pixel compensation unit of any row in described pixel compensation array, comprise multistage pixel compensation module, and described in every one-level, pixel compensation module comprises pixel compensation unit described in one or more continuous print; Wherein, in a described pixel compensation module, the described storage capacitance value of each described pixel compensation unit is all greater than the described storage capacitance value of each described pixel compensation unit in pixel compensation module described in other.
Above-mentioned a kind of image element circuit, in described multistage pixel compensation module, described in each in pixel compensation module described in any one-level, the described storage capacitance value of pixel compensation unit is all equal.
In another embodiment, the invention provides a kind of image element circuit, comprise pixel compensation array, it is characterized in that, described pixel compensation array comprises multiple pixel compensation unit, the described pixel compensation unit of any row in described pixel compensation array, all comprise the different Part I pixel compensation unit of storage capacitance value and Part II pixel compensation unit, with the distortion effect suppressing a data line of same row described pixel compensation units shared to be applied to the data-signal of different described pixel compensation unit, the difference of the magnitude of voltage that the described memory capacitance reducing each described pixel compensation unit in same row described pixel compensation unit by this reaches in charging process.
Above-mentioned a kind of image element circuit, in the described pixel compensation unit of same row, the described storage capacitance value in pixel compensation unit described in a part for the described data-signal generation severe received distortion is adjusted to the described storage capacitance value than the described data-signal received, slight distortion occurring or do not occur in pixel compensation unit described in another part of distorting large.
Accompanying drawing explanation
Read following detailed description also with reference to after the following drawings, Characteristics and advantages of the present invention will be apparent:
Fig. 1 is the basic framework of compensating circuit;
Fig. 2 is the sequential control of compensating circuit;
Fig. 3 A ~ 3D is the response schematic diagram of compensating circuit based on the sequential control of Fig. 2;
Fig. 4 is the layout of compensating circuit array on substrate;
Fig. 5 be data line data-signal on the display screen bottom and top occur distort schematic diagram;
Fig. 6 is the difference at electric current bottom and the top on the display screen flowing through diode;
Fig. 7 is voltage after changing capacitance in memory capacitance in the difference at bottom of screen and top;
Fig. 8 is the difference at electric current bottom and the top on the display screen flowing through diode after changing capacitance;
Fig. 9 is an embodiment of the capacitance of a series of storage in change one row pixel supplementary circuitry.
Embodiment
Below in conjunction with each embodiment; clear complete elaboration is carried out to technical scheme of the present invention; but described embodiment is only that the present invention is with being described herein the embodiment that embodiment used and not all are described; based on these embodiments, those skilled in the art belongs to protection scope of the present invention not making the scheme obtained under the prerequisite of creative work.As Fig. 1, carry out describing explanation with conventional high definition 6HD (highdefinition) pixel compensation circuit or unit.
In pixel compensation circuit, memory capacitance Cst is connected to first node N1 and provides between the first voltage input end ELVDD of supply voltage VDD, the first transistor M1 and transistor seconds M2 is in series with between first node N1 and second voltage input end, this second voltage input end inputs a reference voltage Vin, and the first end of transistor seconds M2 is connected to reference voltage Vin, and second end of transistor seconds M2 is connected with the first end of the first transistor M1, second end of the first transistor M1 is connected to first node N1.In addition, a the 7th transistor M7 is connected with between the first voltage input end ELVDD and Section Point N2, and between a Section Point N2 and data line input end Dlin, be connected with a 5th transistor M5, the first end of the 7th transistor M7 is connected to Section Point N2 and the second end is connected to the first voltage input end ELVDD, and the first end of the 5th transistor M5 is connected to data line input end Dlin and the second end is connected to Section Point N2.
In addition, the 6th transistor M6 and the 8th transistor M8 is in series with between the anode and Section Point N2 of OLED light-emitting component D1, the first end of the 8th transistor M8 is connected to Section Point N2 and the second end is connected to the first end of the 6th transistor M6, second end of the 6th transistor M6 is then connected to the anode of light-emitting component D1, and wherein the control end of the 8th transistor M8 is connected to first node N1.And, second end of the 8th transistor M8 and the first end of the 6th transistor M6 are interconnected to a 3rd node N3, transistor seconds M3 and the 4th transistor M4 is in series with between the 3rd node N3 and first node N1, second end of third transistor M3 is connected to first node N1, the first end of the 4th transistor M4 is connected to the 3rd node N3, the first end of third transistor M3 and the second end interconnection of the 4th transistor M4.9th transistor M9 is connected between the anode of light-emitting component D1 and the second voltage input end providing reference voltage Vin, and its first end is connected to the anode of D1 and the second end is connected to the second voltage input end.
In certain embodiments, the first transistor mentioned herein can select the thin film transistor (TFT) TFT of P type to the 9th transistor M1 ~ M9.In addition setting the first transistor is grid to the 9th transistor M1 ~ M9 control end separately, and these transistors first end separately can be such as that source electrode (or drain electrode) the second end then corresponds to drain electrode (or source electrode).As electronic switch, the control end of transistor can control turning on and off between its first end and the second end.In FIG, first sweep signal Sn-1 is coupled to the control end of first, second transistor M1, M2 simultaneously, second sweep signal Sn is coupled to the control end of the 3rd, the 4th and the 5th transistor M3, M4 and M5 simultaneously, 3rd sweep signal Sn+1 is coupled to the control end of the 9th transistor M9, and enable signal En is then coupled to the control end of the 6th, the 7th transistor M6, M7 simultaneously.The negative electrode of light-emitting component D1 is connected to a tertiary voltage input end ELVSS, and generally inputs earth potential at tertiary voltage input end ELVSS or be the negative voltage VSS of negative value than positive voltage VDD.
See Fig. 3 A, each transistor illustrated in pixel compensation unit corresponds to the switching response action of the period T1 of the sequential control of Fig. 2.At this period T1, enable signal En is high level state, and the 6th transistor M6 controlled by enable signal En and the 7th transistor M7 is turned off.Second sweep signal Sn is high level state, and the third transistor M3 controlled by the second sweep signal Sn and the 4th transistor M4 and the 5th transistor M5 is turned off.3rd sweep signal Sn+1 is also high level state, then the 9th transistor M9 controlled by the 3rd sweep signal Sn+1 is also turned off, and is also turn off at this stage the 8th transistor M8.First sweep signal Sn-1 is low level state, the first transistor M1 controlled by the first sweep signal Sn-1 and transistor seconds M2 connects, first sweep signal Sn-1 charges to memory capacitance Cst at node N1 place as the initialization signal of memory capacitance Cst, make the voltage signal of reference voltage Vin be written to memory capacitance Cst, now the current potential of first node N1 is Vin substantially.
See Fig. 3 B, each transistor illustrated in pixel compensation unit corresponds to the switching response action of the period T2 of the sequential control of Fig. 2.At this period T2, enable signal En is high level state, and the 6th transistor M6 and the 7th transistor M7 is turned off.First sweep signal Sn-1 is high level state, and the first transistor M1 and transistor seconds M2 turns off.3rd sweep signal Sn+1 is also high level state, and the 9th transistor M9 is also turned off.Second sweep signal Sn is low level state, and third transistor M3 and the 4th transistor M4 and the 5th transistor M5 is switched on, and the current potential of Section Point N2 is greater than the current potential of first node N1, and the 8th transistor M8 is also switched on.Second sweep signal Sn is responsible for writing at first node N1 the data be provided on data line dataline, also the voltage signal Vdata that data line input end Dlin inputs namely is written in, when the branch road be embodied in by the 3rd to the 5th transistor M3 ~ M5 of conducting and the 8th transistor M8 of conducting is in critical conduction equilibrium state, force the current potential of first node N1 to be changed to Vdata-|Vthp| substantially, this Vthp is the threshold voltage of the 8th transistor M8 as driving tube.
See Fig. 3 C, each transistor illustrated in pixel compensation unit corresponds to the switching response action of the period T3 of the sequential control of Fig. 2.At this period T3, enable signal En is high level state, and the 6th transistor M6 and the 7th transistor M7 is turned off.First sweep signal Sn-1 is high level state, and the first transistor M1 and transistor seconds M2 turns off.Second sweep signal Sn is high level state, and third transistor M3 and the 4th transistor M4 and the 5th transistor M5 is turned off, and is also turn off at this stage the 8th transistor M8.But the 3rd sweep signal Sn+1 becomes low level, this stage performs the initialized step of anode, 9th transistor M9 conducting is also about to the second voltage input end institute and inputs the anode that a reference voltage Vin is transferred to OLED light-emitting component D1, then the refreshing of the anode residual charge of light-emitting component D1 can be extended serviceable life of OLED by the 3rd sweep signal Sn+1.
See Fig. 3 D, illustrate each transistor in pixel compensation unit and correspond to of the sequential control of Fig. 2 and light or the switching response action of light-emitting period.In ignition phase, the first sweep signal Sn-1 is high level state, and the first transistor M1 and transistor seconds M2 turns off.Second sweep signal Sn is high level state, and third transistor M3 and the 4th transistor M4 and the 5th transistor M5 is turned off.3rd sweep signal Sn+1 is also high level state, and the 9th transistor M9 is turned off.Enable signal En is low level state, and the 6th transistor M6 and the 7th transistor M7 is switched on, and the current potential of Section Point N2 is supply voltage VDD is greater than the current potential Vdata-|Vthp| of first node N1, and the 8th transistor M8 is also conducting.Final formation is from providing the first voltage input end ELVDD of supply voltage VDD to the 7th transistor M7, the 8th transistor M8 and the 6th transistor M6 again to the conducting branches of the negative electrode of OLED light-emitting component D1, make OLED light-emitting component D1 luminous, rough calculation, the electric current I flowing through light-emitting component D1 meets funtcional relationship (wherein parameter μ
prepresent the carrier mobility of the 8th transistor M8, C
oXrepresent the unit area gate oxide capacitance of the 8th transistor M8, W/L then represents the channel width-over-length ratio of the 8th transistor M8):
Then
Along with the size of screen panel increases, load loading on data line dataline thereupon also can be increasing, then can there is the RCloading load effect of dead resistance electric capacity in same data lines from the bottom of screen to top, cause further there are differences with the data-signal at top bottom same data lines.
Be easy to learn by the funtcional relationship flowing through the electric current I of OLED light-emitting component D1 disclosed above, if the Vdata that data line provides is different, direct result is that current value is different, be then easy to the display difference causing the bottom of screen to top.Therefore same screen is necessary that subregion is to design different capacitances, carries out different designs according to different RC, reduces the voltage level difference of data-signal, impel the bottom of screen to reach substantially identical display effect to top.
See Fig. 4, we are described for the layout of the pixel compensation array of full HD FHD (fullhighdefinition) structure based on a GEOA framework (gateemissiondriveronarray), and pixel compensation array is arranged on a substrate.Be connected to each data line DL1, DL2, DL3 of driving chip IC101 ... the pixel compensation unit that DLm is respectively different lines provides the data voltage signal Vdata produced by drive IC 101.First row pixel compensation unit P11, P21 in selected pixels compensated array, P31 ... Pn1 (n be more than or equal to 1 natural number) as research object, first row pixel compensation unit P11, P21, P31 ... Pn1 public same data line DL1, wherein first pixel compensation unit P11 is near drive IC 101, second pixel compensation unit P12 takes second place, by that analogy, last compensating unit Pn1 is farthest away from drive IC 101.The fluctuation of data voltage signal is now described for two pixel compensation unit of head and the tail, because the data-signal Vdata on first pixel compensation unit P11 is closest to original waveform, generally speaking, first pixel compensation unit P11 is without the need to performing the rectification of any electric capacity, by contrast, data-signal Vdata in these row on last compensating unit Pn1 and original waveform can because there is phase shift slightly in capacitance-resistance RCloading load effect, and the electric capacity in apparent last compensating unit Pn1 needs to correct.
As shown in Figure 5, memory capacitance Cst in first pixel compensation unit P11 and the memory capacitance Cst in last compensating unit Pn1 is fixed value (such as adopting 0.2pF), the capacitance of in other words different in different regions pixel compensation unit is identical, but when screen size becomes large, RC becomes large, can see that the data signal curves 203 of applying on the upper data signal curves 202 that applies of the pixel compensation unit P11 of bottommost and top pixel compensation unit Pn1 will exist different wave shape and distortion.This voltage level (characterizing with curve 204) that the memory capacitance Cst in first pixel compensation unit P11 can be caused further to charge reach and the memory capacitance Cst in the last compensating unit Pn1 voltage level (characterizing with curve 205) reached of charging there are differences, such as when 37.399us, voltage after the charging of the memory capacitance Cst in first pixel compensation unit P11 is about 0.33558V, and the voltage of memory capacitance Cst in last compensating unit Pn1 is 0.57079V, both difference the chances are 0.24V.Corresponding is, see Fig. 6, in the ignition phase of OLED light-emitting component D1, the current value flowing through light-emitting component D1 in first pixel compensation unit P11 is curve 302, and the current value flowing through light-emitting component D1 in last compensating unit Pn1 is curve 302, such as when 7.9343ms, the current value flowing through light-emitting component D1 in first pixel compensation unit P11 equals-181.76nA, the current value flowing through light-emitting component D1 in last compensating unit Pn1 equals-157.71nA, simulated current difference 24nA, difference ratio is 24nA/157.7nA=15%.This is enough to the luminance difference causing OLED.Typically, the data-signal Vdata wave form distortion of transmission is more serious, then the corresponding charging voltage drift received in the pixel compensation unit of this data-signal Vdata in memory capacitance is more severe, and these signals are carried in those pixel supplementary units away from drive IC or initial data signal Vdata often.Vice versa, receive charging voltage in memory capacitance slightly or in the pixel compensation unit of the data-signal Vdata waveform do not distorted relatively close to predetermined value, this part signal is carried in those pixel supplementary units close to drive IC or initial data signal Vdata often.
The present invention proposes a row pixel compensation unit P11, P21, P31 ... in Pn1, all comprise the different Part I pixel compensation unit of storage capacitance value and Part II pixel compensation unit.The capacitance of the memory capacitance Cst that last compensating unit Pn1 has such as at least is set, it is the capacitance being greater than the memory capacitance Cst that first pixel compensation unit P11 has, thus in a row pixel compensation unit, memory capacitance Cst charging problem of non-uniform in each pixel compensation unit that the distorted waveform in various degree that the data line DL1 correspondence that improvement shares is applied to the data-signal Vdata of different pixels compensating unit causes.As shown in Figure 7, memory capacitance Cst (such as adopting 0.2pF) in first pixel compensation unit P11 and the memory capacitance Cst in last compensating unit Pn1 is different value (such as adopting 0.3pF), the capacitance of in other words different in different regions pixel compensation unit is not identical, in the charging stage of memory capacitance Cst, because the capacitance of the memory capacitance Cst in last compensating unit Pn1 increases, difference between the voltage level (characterizing with curve 208) that reaches of charging memory capacitance Cst in the first pixel compensation unit P11 memory capacitance Cst charged in the voltage level (characterizing with curve 204) and last compensating unit Pn1 that reach reduces, such as still when 37.399us, voltage after memory capacitance Cst charging in first pixel compensation unit P11 is approximately 0.33558V, the voltage of the memory capacitance Cst in last compensating unit Pn1 is then changed to 0.41911V, both differences are only 0.0835V.Correspondence is with it, with reference to figure 8, in the ignition phase of OLED light-emitting component D1, the current value flowing through light-emitting component D1 in first pixel compensation unit P11 is curve 302, and the current value flowing through light-emitting component D1 in last compensating unit Pn1 is curve 306, such as when 7.9343ms, the current value flowing through light-emitting component D1 in first pixel compensation unit P11 equals-181.76nA, the current value flowing through light-emitting component D1 in last compensating unit Pn1 equals-186.93nA, simulated current difference 5.17nA, difference ratio is 5.17nA/157.7nA=3%, this almost can't see the luminance difference of OLED.It is emphasized that the application's partial data be disclosed in Fig. 5 ~ Fig. 8 is only used for explaining to reader the obvious beneficial effect that this case can reach, these concrete numerical value should not be considered to the restrictive condition constituting this case.
In fact the memory capacitance Cst in first pixel compensation unit P11 and the memory capacitance Cst in last compensating unit Pn1 is implemented differentiation, it is only an optional special case of the present invention, widely, for a whole row pixel compensation unit P11, P21, P31 ... Pn1, as long as a part of continuous print pixel compensation unit P11, P21, P31 of arranging wherein ... the respective storage capacitance value of Pi1 and another part continuous print pixel compensation unit P (i+1) 1, P (i+2) 1 ... Pn1 storage capacitance value is separately different.Specifically, because Part I pixel compensation unit P11, P21, P31 ... Pi1 contains first pixel compensation unit P11, Part II pixel compensation unit P (i+1) 1 simultaneously, P (i+2) 1, Pn1 contains last compensating unit Pn1, notice that a pixel compensation unit (such as Pi1) at end in Part I pixel compensation unit is front and back continuous print two pixel compensation unit with first pixel compensation unit (such as P (i+1) 1) in Part II pixel compensation unit, storage capacitance value in then forward Part I pixel compensation unit should be less than the storage capacitance value in Part II pixel compensation unit rearward, here i can be more than or equal to 1 natural number and be less than n.
In other optional but nonessential embodiment, at the pixel compensation unit P11 of any row, P21, P31, in Pn1, each pixel compensation unit P11 can be made, P21, P31, Pn1 memory capacitance Cst1 separately, Cst2, Cst3 ... the capacitance of Cstn, progressively increase progressively successively by from first pixel compensation unit to the order of last compensating unit, also be in two pixel compensation unit of arbitrary neighborhood, the capacitance of the memory capacitance Cst (k+1) in a rear pixel compensation unit is greater than the capacitance of the memory capacitance Cstk in previous pixel compensation unit, here k can be more than or equal to 1 natural number and be less than n.
If by a series of different memory capacitance Cst1, Cst2, Cst3 ... the capacitance of Cstn is set as progressively increasing progressively successively, the size of changing each electric capacity will be required, although the charging voltage of different memory capacitance can be suppressed to drift about, attempt to change each electric capacity and but compare and expend time in and cost.
See Fig. 9, in other optional but nonessential embodiment, more the method for economization is, by any one row pixel compensation unit P11, P21, P31 ... Pn1 is divided into multistage pixel compensation module S1, S2, S3 ..., and any one-level pixel compensation module S
lcomprise the one or more pixel compensation of continuous print in position unit (Pm1, P (m+1) 1, P (m+2) 1 ...), note in the two-stage pixel compensation module that front and back are adjacent, previous stage pixel compensation module S
l-1a pixel compensation unit (such as P (m-1) 1) and the rear stage pixel compensation module S at middle end
lin first pixel compensation unit (such as P (m) 1) be continuous print, with ensure pixel compensation unit P11, P21, P31 ... each divided delimitation in Pn1 is in the pixel compensation module of specifying, here L, m be greater than 1 natural number and be less than n.Advantage is, memory capacitance Cst1, Cst2, Cst3 ... the capacitance of Cstn need not reset as not identical each other, the substitute is, at multistage pixel compensation module S1, S2, S3 ... in, the capacitance of the memory capacitance Cst of each pixel compensation unit in any one-level pixel compensation module is equal.Such as, previous stage pixel compensation module S
l-1pixel compensation unit (... P (m-2) 1, P (m-1) 1) in respective memory capacitance ..., Cst (m-2), Cst (m-1) capacitance all identical, and neighboring later stage pixel compensation module S
lmiddle pixel compensation unit (Pm1, P (m+1) 1, P (m+2) 1 ...) respective memory capacitance Cst (m), Cst (m+1) ... capacitance also all identical.Problems faced remains, and same data line is applied to the distortion data signal in various degree of different pixels compensating unit, and our essential requirement improves this negative effect, so we still require rear stage pixel compensation module S
lmiddle pixel compensation unit (Pm1, P (m+1) 1, P (m+2) 1 ...) respective memory capacitance Cst (m), Cst (m+1) ... capacitance, be greater than previous stage pixel compensation module S
l-1pixel compensation unit (... P (m-2) 1, P (m-1) 1) in respective memory capacitance ..., Cst (m-2), Cst (m-1) capacitance.In this embodiment, be not restricted to the head and the tail pixel compensation unit of row, meaning is widely, arranges one part of pixel compensating unit (such as previous stage pixel compensation module S
l-1in pixel compensation unit) storage capacitance value and another part pixel compensation unit (such as rear stage pixel compensation module S
lin pixel compensation unit) storage capacitance value different, be applied to different pixels compensating unit (such as pixel compensation module S to suppress a data line DL1 of same row pixel compensation units shared
l-1, S
lin pixel compensation unit) the distortion of data-signal, reduce pixel compensation module S by this
l-1, S
lthe difference of the magnitude of voltage that middle different pixel compensation unit memory capacitance separately reaches in charging process.
In the embodiment in fig. 9, generally speaking, rule is (such as rear stage pixel compensation module S in the one part of pixel compensating unit data-signal generation severe received distorted
lin pixel compensation unit) storage capacitance value, be adjusted to (such as previous stage pixel compensation module S in slight distortion occurring than the data-signal received or another part pixel compensation unit of distorting not occurring
l-1in pixel compensation unit) storage capacitance value large.
Describe pixel compensation module S above
l-1or S
lin each memory capacitance equivalent, but if attempt at pixel compensation module S
l-1the middle a series of memory capacitance arranged contained by it ..., Cst (m-2), Cst (m-1) progressively increase progressively successively is also allow, also i.e. pixel compensation module S
l-1in storage capacitance value arbitrarily in a rear pixel compensation unit be greater than storage capacitance value in adjacent previous pixel compensation unit.Equally, at pixel compensation module S
lmiddle arrange a series of memory capacitance Cst (m) contained by it, Cst (m+1) ... progressively increase progressively successively is also allow.
In addition, although be with adjacent two pixel compensation module S above
l-1or S
lfor example is illustrated, but it should be noted that, the storage capacitance value of each pixel compensation unit in second pixel compensation module of specifying is set, all be greater than the storage capacitance value of each pixel compensation unit in another first pixel compensation module, wherein first, both second pixel compensation module are non-conterminous to be also allowed to, our object is, by the storage capacitance value of (the pixel compensation unit as in the second pixel compensation module) in the one part of pixel compensating unit of the data-signal generation severe of reception distortion, be adjusted to larger than the storage capacitance value of (the pixel compensation unit as in the first pixel compensation module) in the slight distortion of data-signal generation received or another part pixel compensation unit that distortion does not occur, reduce first by this, the difference of the magnitude of voltage that the memory capacitance of each pixel compensation unit reaches in charging process in second pixel compensation module, realize the display effect indifference both them.
Above, by illustrating and accompanying drawing, give the exemplary embodiments of the ad hoc structure of embodiment, foregoing invention proposes existing preferred embodiment, but these contents are not as limitation.For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (7)
1. an image element circuit, comprises pixel compensation array, it is characterized in that, described pixel compensation array comprises multiple pixel compensation unit; Wherein
The described pixel compensation unit of any row in described pixel compensation array, all comprises the different Part I pixel compensation unit of storage capacitance value and Part II pixel compensation unit.
2. image element circuit according to claim 1, is characterized in that, the described storage capacitance value of the first described pixel compensation unit in the described pixel compensation unit of any row is set to the described storage capacitance value lower than pixel compensation unit described in end.
3. image element circuit according to claim 1, it is characterized in that, in the described pixel compensation unit of any row, the described storage capacitance value that each described pixel compensation unit has progressively increases progressively successively by from the order of pixel compensation unit described in first described pixel compensation unit to end.
4. image element circuit according to claim 1, it is characterized in that, the described pixel compensation unit of any row in described pixel compensation array, comprise multistage pixel compensation module, and described in every one-level, pixel compensation module comprises pixel compensation unit described in one or more continuous print; Wherein, in a described pixel compensation module, the described storage capacitance value of each described pixel compensation unit is all greater than the described storage capacitance value of each described pixel compensation unit in pixel compensation module described in other.
5. image element circuit according to claim 4, is characterized in that, in multistage described pixel compensation module, described in each in pixel compensation module described in any one-level, the described storage capacitance value of pixel compensation unit is all equal.
6. an image element circuit, comprise pixel compensation array, it is characterized in that, described pixel compensation array comprises multiple pixel compensation unit, the described pixel compensation unit of any row in described pixel compensation array, all comprise the different Part I pixel compensation unit of storage capacitance value and Part II pixel compensation unit, with the distortion effect suppressing a data line of same row described pixel compensation units shared to be applied to the data-signal of different described pixel compensation unit, the difference of the magnitude of voltage that the described memory capacitance reducing each described pixel compensation unit in same row described pixel compensation unit by this reaches in charging process.
7. image element circuit according to claim 6, it is characterized in that, in the described pixel compensation unit of same row, the described storage capacitance value in pixel compensation unit described in a part for the described data-signal generation severe distortion of reception there is slight distortion than the described data-signal received or the described storage capacitance value that do not occur in pixel compensation unit described in another part of distorting large.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510612998.5A CN105185307A (en) | 2015-09-23 | 2015-09-23 | Pixel circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510612998.5A CN105185307A (en) | 2015-09-23 | 2015-09-23 | Pixel circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105185307A true CN105185307A (en) | 2015-12-23 |
Family
ID=54907342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510612998.5A Pending CN105185307A (en) | 2015-09-23 | 2015-09-23 | Pixel circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105185307A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107644615A (en) * | 2016-07-20 | 2018-01-30 | 上海和辉光电有限公司 | One kind reduces capacity coupled circuit and AMOLED display circuits |
| CN107665672A (en) * | 2016-07-27 | 2018-02-06 | 上海和辉光电有限公司 | Image element circuit and its driving method |
| CN109147670A (en) * | 2017-06-16 | 2019-01-04 | 上海和辉光电有限公司 | A kind of pixel compensation circuit and its driving method, display device |
| CN110930925A (en) * | 2019-12-09 | 2020-03-27 | 上海天马有机发光显示技术有限公司 | Display panel driving method and display panel |
| CN111243522A (en) * | 2018-11-29 | 2020-06-05 | 上海和辉光电有限公司 | Display device and driving method thereof |
| CN112466255A (en) * | 2020-11-23 | 2021-03-09 | 上海和辉光电股份有限公司 | Method for repairing pixel circuit of active matrix organic light-emitting display |
| CN113205747A (en) * | 2021-04-30 | 2021-08-03 | 惠科股份有限公司 | Array substrate, display panel and display device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1409292A (en) * | 2001-09-25 | 2003-04-09 | 三星电子株式会社 | Liquid crystal display unit and its driving method |
| CN101090095A (en) * | 2006-06-15 | 2007-12-19 | 中华映管股份有限公司 | Active component array substrate and manufacturing method thereof |
| KR20080002564A (en) * | 2006-06-30 | 2008-01-04 | 엘지.필립스 엘시디 주식회사 | Pixel Voltage Distortion Prevention Circuit of LCD |
| CN103077680A (en) * | 2013-01-10 | 2013-05-01 | 上海和辉光电有限公司 | Organic light-emitting diode (OLE) pixel driving circuit |
| US20140138693A1 (en) * | 2008-07-08 | 2014-05-22 | Samsung Display Co., Ltd. | Array substrate and liquid crystal display apparatus having the same |
| CN104050918A (en) * | 2014-06-16 | 2014-09-17 | 上海和辉光电有限公司 | Pixel unit drive circuit and display device |
| CN104267552A (en) * | 2014-09-24 | 2015-01-07 | 深圳市华星光电技术有限公司 | Array substrate and liquid crystal display panel |
-
2015
- 2015-09-23 CN CN201510612998.5A patent/CN105185307A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1409292A (en) * | 2001-09-25 | 2003-04-09 | 三星电子株式会社 | Liquid crystal display unit and its driving method |
| CN101090095A (en) * | 2006-06-15 | 2007-12-19 | 中华映管股份有限公司 | Active component array substrate and manufacturing method thereof |
| KR20080002564A (en) * | 2006-06-30 | 2008-01-04 | 엘지.필립스 엘시디 주식회사 | Pixel Voltage Distortion Prevention Circuit of LCD |
| US20140138693A1 (en) * | 2008-07-08 | 2014-05-22 | Samsung Display Co., Ltd. | Array substrate and liquid crystal display apparatus having the same |
| CN103077680A (en) * | 2013-01-10 | 2013-05-01 | 上海和辉光电有限公司 | Organic light-emitting diode (OLE) pixel driving circuit |
| CN104050918A (en) * | 2014-06-16 | 2014-09-17 | 上海和辉光电有限公司 | Pixel unit drive circuit and display device |
| CN104267552A (en) * | 2014-09-24 | 2015-01-07 | 深圳市华星光电技术有限公司 | Array substrate and liquid crystal display panel |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107644615A (en) * | 2016-07-20 | 2018-01-30 | 上海和辉光电有限公司 | One kind reduces capacity coupled circuit and AMOLED display circuits |
| CN107644615B (en) * | 2016-07-20 | 2020-06-30 | 上海和辉光电有限公司 | Circuit for reducing capacitive coupling and AMOLED display circuit |
| CN107665672A (en) * | 2016-07-27 | 2018-02-06 | 上海和辉光电有限公司 | Image element circuit and its driving method |
| US10453390B2 (en) | 2016-07-27 | 2019-10-22 | Everdisplay Optronics (Shanghai) Limited | Pixel circuit and method for driving the same |
| CN109147670A (en) * | 2017-06-16 | 2019-01-04 | 上海和辉光电有限公司 | A kind of pixel compensation circuit and its driving method, display device |
| CN111243522A (en) * | 2018-11-29 | 2020-06-05 | 上海和辉光电有限公司 | Display device and driving method thereof |
| CN110930925A (en) * | 2019-12-09 | 2020-03-27 | 上海天马有机发光显示技术有限公司 | Display panel driving method and display panel |
| CN112466255A (en) * | 2020-11-23 | 2021-03-09 | 上海和辉光电股份有限公司 | Method for repairing pixel circuit of active matrix organic light-emitting display |
| CN113205747A (en) * | 2021-04-30 | 2021-08-03 | 惠科股份有限公司 | Array substrate, display panel and display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109859678B (en) | Gate driving circuit and light emitting display device including the same | |
| CN105185307A (en) | Pixel circuit | |
| CN104112427B (en) | Image element circuit and its driving method and display device | |
| CN103915061B (en) | Organic LED display device and driving method thereof | |
| CN106486053B (en) | Organic light emitting display | |
| CN103714784B (en) | Comprise the liquid crystal display device of TFT compensating circuit | |
| US8130181B2 (en) | Luminescence display and driving method thereof | |
| EP2747064B1 (en) | Organic light emitting diode display device and method for driving the same | |
| CN104992674A (en) | Pixel compensation circuit | |
| CN108022562B (en) | Gate driver and display device using the same | |
| CN109935212A (en) | Display panel, display device and driving method | |
| CN101978414B (en) | Display pixel and method for applying current to the display pixel | |
| KR20190003334A (en) | Display device and gate driving circuit thereof | |
| CN101645236B (en) | Display panel module and electronic apparatus | |
| US9472140B2 (en) | Drive circuit, optoelectronic device, electronic device, and drive method | |
| KR20180061524A (en) | Display panel and electroluminescence display using the same | |
| KR100667664B1 (en) | Driving method of pixel circuit, pixel circuit and electronic device | |
| CN110429120B (en) | Array substrate, driving method thereof, display panel and display device | |
| CN103474024A (en) | Pixel circuit and displayer | |
| TW200300244A (en) | Signal line drive circuit, light emitting device, and the drive method | |
| CN108922474A (en) | A kind of pixel compensation circuit and its driving method, AMOLED display panel | |
| CN103177686B (en) | Display device | |
| CN101714331A (en) | Display panel module and electronic apparatus | |
| US20230215381A1 (en) | Gate driver circuit, display panel and display device including the same | |
| CN103474026A (en) | Pixel circuit and displayer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20151223 |
|
| WD01 | Invention patent application deemed withdrawn after publication |