CN105161501B - Array base palte and preparation method thereof, display panel and display device - Google Patents

Abstract

The invention provides an array substrate and a manufacturing method thereof, a display panel and a display device. The array substrate includes: a substrate, and a grid line pattern and a data line pattern formed on the substrate; the gate line pattern and the data line pattern The line pattern defines a plurality of pixels; two columns of adjacent data lines form a data line group, and the two columns of data lines in each data line group are connected to the same data voltage input terminal; it also includes the display area formed on the substrate. An overlapping line pattern, the overlapping line pattern includes conductive overlapping lines, and two rows of data lines in the same data line group are connected by at least one overlapping line in the display area. Compared with the array substrate in the prior art, the array substrate provided by the present invention can reduce the transmission delay of the data voltage signal on the data line.

Description

Array substrate and manufacturing method thereof, display panel and display device

technical field

The present invention relates to the field of display technology, in particular to an array substrate and a manufacturing method thereof, a display panel and a display device.

Background technique

With the development of display device manufacturing technology, liquid crystal display device technology has developed rapidly, and has replaced traditional picture tube displays and become the mainstream of future flat panel displays. In the field of liquid crystal display technology, TFT-LCD (Thin Film Transistor Liquid Crystal Display) is widely used in televisions, computers, and mobile phones due to its large size, high integration, powerful functions, flexible process, and low cost. machines and other fields.

TFT-LCD adopts row-column matrix driving mode. For example, when the product resolution of the display device is 320x240, 320 Gate IC lines are required, and 240x3 data lines (RGB) are required to realize the control of each pixel. Specifically, in each frame, the gate drive circuit controls the TFTs connected to each pixel to be turned on sequentially, and the data drive circuit writes the corresponding data voltage signal into each pixel through the connected data line, so that each Pixels have a corresponding luminous brightness.

Due to the limitation of the width, the data line generally has a relatively high resistance, which will cause a relatively high transmission delay of the data voltage signal on the data line and affect the light-emitting display.

Contents of the invention

An object of the present invention is to reduce the transmission delay of a data voltage signal on a data line.

In a first aspect, the present invention provides an array substrate, including a substrate and a grid line pattern and a data line pattern formed on the substrate; the gate line pattern and the data line pattern define a plurality of pixels; Adjacent data lines form a data line group, and the two columns of data lines in each data line group are connected to the same data voltage input terminal; it also includes a lapping line pattern formed on the display area on the substrate, and the lapping line The graph includes conductive overlapping lines, and two rows of data lines in the same data line group are connected by at least one overlapping line in the display area.

Further, the overlapping line pattern and the data line pattern are formed through the same process.

Further, the overlapping lines in the overlapping line pattern are formed in non-opening areas.

Further, each row of pixels is connected to two rows of grid lines, the first grid line is located above the row of pixels, and the second grid line is located below the row of pixels; the overlapping lines in the overlapping line pattern are located in two adjacent columns Between the second gate line of the upper row of pixels and the first gate line of the next row of pixels among the pixels.

Further, the pixels defined by the grid line pattern and the data line pattern are used to display three colors, the pixels used to display the first color, the pixels used to display the second color and the pixels used to display the third color. The pixels of each color are arranged in delta.

In a second aspect, the present invention provides a method for manufacturing an array substrate, including:

A step of forming a grid line pattern and a data line pattern on a substrate, wherein the formed gate line pattern and the formed data line pattern define a plurality of pixels; two columns of adjacent data lines form a data line group, and each data line The two columns of data lines in the group are connected to the same data voltage input terminal;

It also includes forming a lap line pattern in the display area on the substrate, the formed lap line pattern includes a plurality of conductive lap lines, and two columns of data lines in the same data line group are connected by at least one lap line in the display area .

Further, said forming the overlapping line pattern on the substrate includes:

The lap line pattern is formed in the same process as the data line pattern is formed.

Further, said forming the overlapping line pattern on the substrate includes:

Each overlapping line in the overlapping line pattern is formed in the non-opening area.

Further, in the formed grid pattern, each row of pixels is connected to two rows of grid lines, the first grid line is located above the row of pixels, and the second grid line is located below the row of pixels;

The forming of the overlapping line pattern on the substrate includes: forming the overlapping line in the overlapping line pattern between the second gate line of the upper row of pixels and the first gate line of the next row of pixels in two adjacent columns of pixels .

In a third aspect, the present invention provides a display panel, including the array substrate described in any one of the above.

In a fourth aspect, the present invention provides a display device, including the above-mentioned display panel.

In the array substrate provided by the present invention, a lap line pattern is formed in the display area on the substrate, and the lap line pattern includes conductive lap lines, and the first data line and the second data line in the same data line group are The display areas are connected by at least one overlapping line. Compared with the array substrate in the prior art, the array substrate provided by the present invention can reduce the transmission delay of the data voltage signal on the data line.

Description of drawings

FIG. 1 is a schematic diagram of an array substrate using a dual-gate technology in the prior art;

FIG. 2, FIG. 3 and FIG. 4 are schematic structural views of the array substrate provided by the embodiment of the present invention;

5 is a resistance equivalent diagram of a data line of an array substrate in the prior art;

FIG. 6 is an equivalent resistance diagram of the data lines of the array substrate provided by the embodiment of the present invention.

Detailed ways

The specific implementation manners of the present invention will be further described below in conjunction with the drawings and examples. The following examples are only used to illustrate the technical solution of the present invention more clearly, but not to limit the protection scope of the present invention.

Generally speaking, data driving circuits are much more expensive than gate driving circuits. Therefore, a dual gate technology is proposed in the prior art, which reduces the number of data driving circuits by increasing the number of gate lines while ensuring the display of the same number of pixels, so as to reduce the product cost. Figure 1 is an existing array substrate using double-gate technology, in which any row of pixels in a row of pixels, for example, the first row of pixels R1 is connected to two rows of gate lines G1 and G2, wherein one row of gate lines G1 controls pixels in odd columns, and the other row of pixels The gate line G2 controls the pixels in the even columns, and the data lines of two adjacent columns are connected to the same data voltage input terminal, for example, the data lines D1 and D2 are connected to the same data voltage input terminal I1, so that the number of required data voltage input terminals is reduced by half , can greatly reduce the number of data driving circuits to be used, thereby reducing the cost of the corresponding display device.

The array substrate provided by the present invention is also similar to that in Figure 1, that is, the data lines in two adjacent columns in the data line pattern formed on the base of the array substrate form a data line group, and the data lines in the same data line group The two columns of data lines are connected to the same data voltage input terminal. The difference is that the array substrate provided by the present invention also includes a lap line pattern formed in the display area of the base, and the two columns of data lines in the same data line group are connected by the lap line in the display area, which is equivalent to connecting the two columns of data The lines are connected in parallel through the bonding wires, which can reduce the resistance between the pixels connected to the two columns of data lines and located below the bonding wires (assuming that the data voltage input terminal is set above) to the data voltage input terminal, thereby reducing the data voltage. The propagation delay of the voltage signal to the pixel.

On the other hand, the present invention also provides a method for manufacturing an array substrate, which can be used to manufacture the array substrate provided by the present invention, and the method includes:

A step of forming a grid line pattern and a data line pattern on a substrate, wherein the formed gate line pattern and the formed data line pattern define a plurality of pixels; two columns of adjacent data lines form a data line group, and each data line The two columns of data lines in the group are connected to the same data voltage input terminal; it also includes forming a lap line pattern in the display area on the substrate, and the formed lap line pattern includes a plurality of conductive lap lines, and the same data line group The first data line and the second data line in the display area are connected by at least one overlapping line.

In actual implementation, the above-mentioned array substrate may exhibit various specific structures. The corresponding manufacturing methods may also be different, which will be described below in conjunction with the accompanying drawings.

Referring to Fig. 2, Fig. 3 and Fig. 4, it is a schematic structural diagram of an array substrate provided by an embodiment of the present invention, the array substrate includes: a substrate (not shown in the figure), a gate line pattern and a data line pattern formed on the substrate , the gate line pattern includes multiple rows of gate lines G1-G8, the data line pattern includes multiple columns of data lines D1-D6, the gate line pattern and the data line pattern define pixels in 4 rows and 6 columns (one pixel connects two rows of adjacent A rectangular or approximately rectangular area defined by a gate line and two columns of adjacent data lines), each pixel has three colors: R, G, and B. Wherein, each row of pixels is connected with two rows of grid lines, one row of grid lines is located above the row of pixels, connecting the odd-numbered columns of pixels, and the other row of grid lines is located below the row of pixels, connecting the even-numbered columns of pixels therein; for example, for the first A row of pixels R1, wherein the pixels in the S1, S3 and S5 columns are connected to the gate line G1 located above the row of pixels, and the S2, S4 and S6 columns of pixels are connected to the gate line G2 located below the row of pixels; The two columns of data lines form a data line group, and the two columns of data lines in a data line group are connected to the same data voltage input terminal, and each column of data lines is connected to the pixel immediately to the left; for example, for data line D1, it is connected to the left side The pixel column S1 of the pixel column, the data line D2 is connected to the pixel column S2 on the left side, and the data lines D1 and D2 are connected to the same data voltage input terminal I1;

In addition, referring to FIG. 2 , FIG. 3 and FIG. 4 , the array substrate further includes a lap line pattern formed in the display area on the base, and the lap line pattern includes a plurality of conductive lap lines L shown in the figures; Two columns of data lines in the same data line group are connected through a plurality of overlapping lines L in the display area. Each overlapping line can be formed between the gate line connecting the pixels in the previous row and located below the pixels in the previous row in two adjacent columns of pixels and the gate line connecting the pixels in the next row and located above the pixels in the next row, such as in FIG. 2, FIG. 3 and FIG. 4 , the overlapping line L shown with a label is connected between the gate line G2 connected to the pixels in the R1 row and located below the R1 row pixels, and the gate line G3 connected to the R2 row pixels and located above the R2 row pixels. In FIG. 2 , FIG. 3 and FIG. 4 , it refers to the side away from the data voltage input terminal, and the upper side refers to the side close to the data voltage input terminal.

In the array substrate provided by the embodiment of the present invention, the two columns of data lines connected to the same data voltage input terminal are connected in the display area through multiple overlapping lines, which is equivalent to connecting the two columns of data lines in parallel, which can reduce the number of data lines located on the overlapping lines. The resistance between the lower pixel and the data voltage input terminal greatly reduces the transmission delay of the data voltage signal to the corresponding pixel.

Referring to FIG. 5 , it is an equivalent circuit diagram of data lines in an array substrate in the prior art. Assuming that the array substrate has 320*160 pixels, and the resistance of a section of data lines corresponding to one pixel is R, then for the Xth Pixel P-X, the resistance from the pixel P-X to the data voltage input terminal In is X*R∥(2x320-X)R, assuming that the above-mentioned X is 160, then the resistance from the pixel P-X to the data voltage input terminal In is 160*R∥(2x320 -160)R=120R. Referring to FIG. 6, it is an equivalent circuit diagram of the data lines in the array substrate provided by the present invention. Similarly, it is assumed that the array substrate has 320*160 pixels, and the resistance of a section of data lines corresponding to one pixel is R, then for the Xth Pixel P-X, the resistance X*R/2 from the pixel P-X to the data voltage input terminal In, when X is 160, the resistance from the pixel P-X to the data voltage input terminal In is 80R, it can be seen that the array substrate provided by the present invention can greatly reduce the pixel-to-data The resistor at the voltage input terminal reduces the transmission delay of the data voltage signal on the data line.

Moreover, in the embodiment of the present invention, the overlapping lines are formed between the two rows of gate lines. On the one hand, since they are arranged in non-opening regions, the aperture ratio of the corresponding pixels will not be affected; on the other hand, due to the overlapping lines It is formed between two rows of gate lines, so as to avoid the formation of capacitance between the overlapping lines and the gate lines, and reduce the transmission signal delay of voltage signals between the gate lines and the data lines.

It is not difficult to understand that, in a specific implementation, the grid lines located above a row of pixels are connected to the even-numbered columns of pixels in the pixel row, and the grid lines located below the pixels are connected to the odd-numbered columns of pixels in the pixel row, which will not affect this The implementation of the invention and the corresponding technical solutions should also fall within the scope of protection of the present invention.

It is not difficult to understand that, only for the purpose of not affecting the aperture ratio of the pixel, the above-mentioned overlapping line may be formed in the non-opening area, and does not need to be formed between two rows of gate lines. However, if it is only for the purpose of reducing the transmission delay of the data voltage signal on the data line, the above-mentioned overlapping line does not need to be formed in the non-opening area. These solutions should also fall within the protection scope of the present invention.

In a specific implementation, the above-mentioned overlapping line pattern and the data line pattern can be formed in the same process, which can reduce manufacturing difficulty. Of course, in practical applications, overlapping line patterns produced by other methods can also solve the basic problems raised by the present invention, and the corresponding technical solutions should also fall within the scope of protection of the present invention.

In actual implementation, the colors of the above-mentioned pixels are not limited to three, as long as a lap line pattern is formed in the display area, and two columns of data lines connected to the same data voltage input terminal are connected through the lap line, the corresponding technical solution All can achieve the basic purpose of the present invention, and all should fall into the protection scope of the present invention.

In a specific implementation, referring to FIG. 2 , the above-mentioned color pixels R, G, and B may be arranged in strips, that is, the pixels in each column are of the same color. Alternatively, as shown in FIG. 3 , three adjacent pixels of different colors, red pixel R, blue pixel B, and green pixel G, are distributed in a regular triangle, that is, arranged in a delta shape.

FIG. 4 is a schematic diagram of a partial structure of the array substrate in FIG. 3 when it is a liquid crystal array substrate in Twisted Nematic (TN) mode. It is not difficult to understand that, in practical applications, the above-mentioned liquid crystal array substrate may also be a liquid crystal array substrate in an advanced super dimension switching technology (ADvanced Super Dimension Switch, ADS) mode or a liquid crystal array substrate in other modes. Or in practical application, the above-mentioned array substrate may not be a liquid crystal array substrate, but other types of array substrates, and the corresponding technical solutions should fall within the protection scope of the present invention.

The manufacturing method of the array substrate described in Fig. 2, Fig. 3 and Fig. 4 may specifically include:

The gate pattern and the data line pattern are formed on the substrate through a patterning process, and the lap line pattern is formed in the non-opening area in the same process of forming the data line pattern. Specifically, each overlapping line pattern in the overlapping line pattern is formed between the gate line connecting the pixels in the previous row and located below the pixels in the previous row and the gate line connecting the pixels in the next row and located above the pixels in the next row. wiring.

For the specific process of forming the gate line pattern through the patterning process, and forming the data line pattern and the lap line pattern through the patterning process, reference may be made to the patterning process in the prior art, and the present invention will not describe it in detail here.

In a third aspect, the present invention further provides a display panel, including the above-mentioned array substrate.

In a fourth aspect, the present invention further provides a display device, including the above-mentioned display panel.

The display device here can be: electronic paper, mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame, navigator and any other product or component with display function.

The above is only a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the technical principle of the present invention, some improvements and modifications can also be made. These improvements and modifications It should also be regarded as the protection scope of the present invention.

Claims (11)

1. a kind of array base palte, including substrate and form grid line figure and data line graph on the substrate；The grid Line graph and the data line graph limit multiple pixels；The adjacent data wire of two row forms a data line group, each number Same data voltage input is linked into according to two column data lines in line group；Characterized in that, also include being formed in substrate The overlap joint line graph of viewing area, the overlap joint line graph include conductive overlap joint line, two column datas in same data line group Line is connected in viewing area by least one overlap joint line, and picture is provided between two column data lines in each group of data wire Element.

2. array base palte as claimed in claim 1, it is characterised in that the overlap joint line graph passes through same with the data line graph Technique is formed.

3. array base palte as claimed in claim 1 or 2, it is characterised in that the overlap joint line in the overlap joint line graph is formed Non-open areas.

4. array base palte as claimed in claim 3, it is characterised in that two row grid lines, the first grid line position are connected per one-row pixels In the top of the row pixel, the second grid line is located at the lower section of the row pixel；Overlap joint line in the overlap joint line graph is positioned at adjacent In two row pixels between the second grid line of lastrow pixel and the first grid line of next line pixel.

5. array base palte as claimed in claim 1, it is characterised in that the grid line figure and the data line graph are limited Each pixel be used for show three kinds of colors, for show the first color pixel, for show second of color pixel With the pixel for showing the third color in delta arrangements.

6. a kind of preparation method of array base palte, including：

Grid line figure is being formed in substrate and the step of data line graph, grid line figure formed in it and the data formed Line graph limits multiple pixels；The two adjacent data wires of row form a data line group, two columns in each data line group Same data voltage input is linked into according to line；Characterized in that,

Also include the viewing area in substrate and form overlap joint line graph, the overlap joint line graph formed includes a plurality of conductive take Wiring, two column data lines in same data line group are connected in viewing area by least one overlap joint line, each group of number According to being provided with pixel between two column data lines in line.

7. method as claimed in claim 6, it is characterised in that the overlap joint line graph that formed in substrate includes：

The overlap joint line graph is formed in the same technique for forming the data line graph.

8. method as claimed in claims 6 or 7, it is characterised in that the overlap joint line graph that formed in substrate includes：

Line is overlapped in each bar that non-open areas is formed in the overlap joint line graph.

9. method as claimed in claim 6, it is characterised in that in the grid line figure formed, the connection two per one-row pixels Row grid line, the first grid line are located on the top of the row pixel, and the second grid line is located at the lower section of the row pixel；

The overlap joint line graph that formed in substrate includes：In adjacent two row pixel the second grid line of lastrow pixel with it is next The overlap joint line formed between first grid line of row pixel in the overlap joint line graph.

10. a kind of display panel, it is characterised in that including the array base palte as described in claim any one of 1-5.

11. a kind of display device, it is characterised in that including display panel as claimed in claim 10.