CN105161133B - Shift register and output signal pull-down method thereof - Google Patents

Abstract

The present invention provides a shift register, which receives and generates an output signal according to an input signal and a first operation clock signal, and includes a main pull-down control circuit, a first and a second auxiliary pull-down control circuit, and a pull-down circuit. The main pull-down control circuit receives an input signal, a pull-down clock signal, and a reference potential, and outputs a pull-down control signal. The first auxiliary pull-down control circuit is electrically connected to the main pull-down control circuit and receives the reference potential, which is used to control the pull-down control signal to be floating. The second auxiliary pull-down control circuit receives the pull-down clock signal and the first operation clock signal, which is used to pull up the potential of the floating pull-down control signal. The pull-down circuit receives and pulls down the potential of the input signal and the output signal to the reference potential according to the pull-down control signal after the potential is pulled up.

Description

Shift register and its output signal pull-down method

technical field

The present invention relates to a shift register, in particular to a shift register and a method for pulling down an output signal thereof.

Background technique

Under the increasingly fierce competition in the panel industry, the goal pursued by various panel manufacturers is nothing more than light, thin and short, and if they want to make the panel achieve the effect of a narrow frame, the gate driver IC (gate driver IC) is integrated into the glass substrate. The above is a better technical solution. Therefore, based on the consideration of narrow frame and low cost, GOA (gate driveron array) has gradually become a technology researched by various panel manufacturers. Generally speaking, the current shift register generates an output signal according to the input signal and the high-frequency operation clock signal. However, after the next-stage shift register generates and outputs the output signal, the previous The output signal generated by the shift register should ideally be at a logic low level, but due to the influence of the high frequency operating clock signal or the unexpected coupling between other signals, the output signal may not be able to It is stably maintained at a logic low level. Therefore, in order to reduce the noise generated by the high-frequency operation clock signal or the unexpected coupling between other signals and affect the stability of the output signal, it is generally shifted in A plurality of pull-down circuits are arranged in the register to stably maintain the output signal at a logic low level.

The traditional shift register is equipped with two sets of pull-down circuits, and each receives two sets of complementary low-frequency signals during operation as its pull-down control signals. However, the voltage level of the pull-down control signal under this design will be It will be limited to the highest voltage level received by the entire circuit. In this case, if you want to make the pull-down circuit have better driving ability, the general practice is to increase the pull-down circuit to pull down the output signal. The size of the operating transistor, however, in addition to requiring a larger wiring area, this approach may also cause the shift register to generate more leakage current during operation. Accordingly, without increasing the size of the transistors in the pull-down circuit, how to improve the driving capability of the pull-down circuit to make the output signal of the shift register more stable has become a research goal of various manufacturers.

SUMMARY OF THE INVENTION

The present invention provides a shift register with better pull-down capability of output signals without increasing the size of transistors in the pull-down circuit.

The present invention further provides a method for pulling down an output signal of a shift register, which is suitable for the above-mentioned shift register.

A shift register provided by the present invention is used for receiving an input signal and a first operating clock signal to generate an output signal. The shift register includes a main pull-down control circuit and a first auxiliary pull-down control circuit , a second auxiliary pull-down control circuit and a pull-down circuit. The main pull-down control circuit is used for receiving the input signal, the pull-down clock signal and the reference potential, and outputs the pull-down control signal. The first auxiliary pull-down control circuit is electrically connected to the main pull-down control circuit and receives a reference potential. The first auxiliary pull-down control circuit is used for controlling the pull-down control signal to be floating. The second auxiliary pull-down control circuit is used for receiving the pull-down clock signal and the first operation clock signal. The second auxiliary pull-down control circuit is used for pulling up the potential of the floating pull-down control signal. The pull-down circuit is used for receiving and pulling down the potential of the input signal and the output signal to the reference potential according to the pull-down control signal after the potential is pulled up.

In an embodiment of the present invention, the second auxiliary pull-down circuit in the above-mentioned shift register includes a coupling control transistor and a coupling capacitor. The control end of the coupling control transistor receives the pull-down clock signal, the first end of the coupling control transistor receives the first operation clock signal, the first end of the coupling capacitor is electrically connected to the second end of the coupling control transistor, and the second end of the coupling capacitor Receive pull-down control signals. When the pull-down clock signal and the first operating clock signal are enabled, the coupling control transistor controls the coupling capacitor so as to couple the potential of the first operating clock signal to the second end of the coupling capacitor through the coupling effect of the coupling capacitor to pull the Raises the potential of the floating pull-down control signal.

In an embodiment of the present invention, the main pull-down control circuit in the above-mentioned shift register includes a first transistor, a second transistor, a third transistor and a fourth transistor. The control terminal of the first transistor and the first terminal of the first transistor receive the pull-down clock signal. The control terminal of the second transistor receives the input signal, the first terminal of the second transistor is electrically connected to the second terminal of the first transistor, and the second terminal of the second transistor receives the reference potential. The control end of the third transistor is electrically connected to the second end of the first transistor, and the first end of the third transistor receives the pull-down clock signal. The control end of the fourth transistor receives the input signal, the first end of the fourth transistor is electrically connected to the second end of the third transistor, and the second end of the fourth transistor receives the reference potential. When the pull-down clock signal is enabled, the second terminal of the third transistor outputs a pull-down control signal.

In an embodiment of the present invention, the above-mentioned first auxiliary pull-down control circuit includes a fifth transistor. The control terminal of the fifth transistor receives the first operation clock signal, the first terminal of the fifth transistor is electrically connected to the control terminal of the third transistor, the second terminal of the fifth transistor receives the reference potential, and the fifth transistor operates according to the first operation The third transistor is turned off by the pulse signal, so that the pull-down control signal is floating.

In another embodiment of the present invention, the above-mentioned first auxiliary pull-down control circuit further includes a sixth transistor. The control terminal of the sixth transistor receives the second operating clock signal, the first terminal of the sixth transistor is electrically connected to the first terminal of the fifth transistor, the second terminal of the sixth transistor receives the reference potential, and the second operating clock signal is earlier After the first operating clock signal is enabled, the sixth transistor turns off the third transistor before the fifth transistor according to the second operating clock signal to make the pull-down control signal floating.

In yet another embodiment of the present invention, the above-mentioned first auxiliary pull-down control circuit includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The first end of the fifth transistor is electrically connected to the control end of the third transistor, the second end of the fifth transistor receives the reference potential, the control end of the sixth transistor and the first end of the sixth transistor receive the first operation clock signal, The second end of the sixth transistor is electrically connected to the control end of the fifth transistor, the control end of the seventh transistor and the first end of the seventh transistor receive the second operating clock signal, and the second end of the seventh transistor is electrically connected to the fifth transistor The control terminal of the transistor, the control terminal of the eighth transistor receives the third operation clock signal, the first terminal of the eighth transistor is electrically connected to the control terminal of the fifth transistor, and the second terminal of the eighth transistor receives the reference potential, during the second operation The pulse signal is enabled earlier than the first operation clock signal, the third operation clock signal is enabled later than the first operation clock signal, and the sixth transistor and the seventh transistor are respectively based on the first operation clock signal and The second operating clock signal turns on the fifth transistor, thereby turning off the third transistor so that the pull-down control signal is floating.

The method for pulling down an output signal of a shift register provided by the present invention is suitable for a shift register including a main pull-down control circuit, a first auxiliary pull-down control circuit, a second auxiliary pull-down control circuit and a pull-down circuit, and the second pull-down control circuit is suitable for a shift register. The auxiliary pull-down control circuit includes a coupling control transistor and a coupling capacitor. The pull-down circuit is used to receive the output signal of the shift register and the reference potential. The output signal pull-down method includes the following steps: providing a pull-down clock signal to the main pull-down control circuit to make the main pull-down control circuit output the pull-down control signal; provide the first operation clock signal to the first auxiliary pull-down control circuit to control the pull-down control signal to be floating, and provide the pull-down clock signal and the first operation clock signal to the coupling The control transistor controls the coupling capacitor, so as to pull up the potential of the floating pull-down control signal through the coupling action of the coupling capacitor; and the pull-down circuit shifts the output signal of the shift register according to the pull-down control signal after pulling up the potential Pull down to reference potential.

Because the present invention adopts the above-mentioned circuit structure to pull down the output signal, the pull-down control signal output by the main pull-down control circuit is controlled to be floating through the first auxiliary pull-down control circuit, and then the coupling capacitor in the second auxiliary pull-down control circuit is used to control the pull-down control signal. The potential of the floating pull-down control signal is pulled up to exceed the highest voltage level received by the entire circuit, so the pull-down control signal after the pull-up potential can drive the pull-down circuit more effectively without increasing the size of the transistors in the pull-down circuit .

Description of drawings

1 is a block diagram of a shift register according to an embodiment of the present invention;

FIG. 2 is a timing diagram of a shift register according to an embodiment of the present invention.

3 is a circuit diagram of a shift register according to an embodiment of the present invention;

4 is a circuit diagram of a voltage regulator module according to another embodiment of the present invention;

5 is a timing diagram of an operating clock signal according to an embodiment of the present invention;

6 is a circuit diagram of a voltage regulator module according to another embodiment of the present invention;

FIG. 7 is a flowchart of a method for pulling down an output signal according to an embodiment of the present invention.

Explanation of reference numerals

100: Shift register

101, 102, 401, 601: voltage regulator module

10-1, 10-2: Main pull-down control circuit

11-1, 11-2: The first auxiliary pull-down control circuit

12-1, 12-2: Second auxiliary pull-down control circuit

13-1, 13-2: Pull-down circuit

Ta, Tb, Tc, Td, T32, T42, T51, T52, T53, T55, T56, T57, T58, T59: Transistors

T51-1, T52-1, T53-1, T54-1, T55-1, T56-1, T57-1, T58-1, T59-1: first end

T51-2, T52-2, T53-2, T54-2, T55-2, T56-2, T57-2, T58-2, T59-2: second end

T51-3, T52-3, T53-3, T54-3, T55-3, T56-3, T57-3, T58-3, T59-3: Control terminal

Ca, Cc: Capacitance

VSS: reference potential

Q(n), Q(n+2): Input signal

G(n), G(n+4): output signal

HC(n-1), HC(n), HC(n+2), HC1, HC2, HC3, HC4: Operation clock signal

LC1, LC2: pull-down clock signal

P(n), K(n): pull-down control signal

S701, S702, S703: Steps

VH, VL, VQ, VH': Potential

Detailed ways

FIG. 1 is a block diagram of a shift register according to an embodiment of the present invention. As shown in FIG. 1 , the shift register 100 includes a voltage regulator module 101 , a voltage regulator module 102 , a capacitor Ca, a transistor Ta, a transistor Tb, a transistor Tc, and a transistor Td. The transistor Ta generates the output signal G(n) according to the received input signal Q(n) and the first operating clock signal HC(n), and the transistor Tb generates the output signal G(n) according to the received input signal Q(n) and the outputs of the next four stages The signal G(n+4) pulls down the potential of the gate terminal of the transistor Ta to the reference potential VSS, where n is a positive integer. The transistor Tc transmits the first operating clock signal HC(n) to the gate terminal of the transistor Td according to the received input signal Q(n), so that the transistor Td transmits the output signal G(n) to the shifter of the subsequent stage. The bit register (not shown in the figure) is used as the input signal Q(n+2) of the second-stage shift register.

As mentioned above, the voltage regulator module 101 includes the main pull-down control circuit 10-1, the first auxiliary pull-down control circuit 11-1, the second auxiliary pull-down control circuit 12-1, and the pull-down circuit 13-1. The main pull-down control circuit 10-1 is used for receiving the input signal Q(n), the pull-down clock signal LC1 and the reference potential VSS, and outputs the pull-down control signal P(n). The first auxiliary pull-down control circuit 11-1 is electrically connected to the main pull-down control circuit 10-1 and receives the reference potential VSS. The first auxiliary pull-down control circuit 11-1 is used for controlling the pull-down control signal P(n) to be in a floating state. The second auxiliary pull-down control circuit 12-1 is used for receiving the pull-down clock signal LC1 and the first operating clock signal HC(n). The second auxiliary pull-down control circuit 12-1 is used for pulling up the potential of the pull-down control signal P(n) in a floating state. The pull-down circuit 13-1 is used for receiving and pulling down the potentials of the input signal Q(n) and the output signal G(n) to the reference potential VSS according to the pull-down control signal P(n) after the potential is pulled up.

Similarly, the voltage regulator module 102 includes a main pull-down control circuit 10-2, a first auxiliary pull-down control circuit 11-2, a second auxiliary pull-down control circuit 12-2, and a pull-down circuit 13-2. The main pull-down control circuit 10-2 is used for receiving the input signal Q(n), the pull-down clock signal LC2 and the reference potential VSS, and outputs the pull-down control signal K(n). The first auxiliary pull-down control circuit 11-2 is electrically connected to the main pull-down control circuit 10-2 and receives the reference potential VSS. The first auxiliary pull-down control circuit 11-2 is used to control the pull-down control signal K(n) to be in a floating state. The second auxiliary pull-down control circuit 12-2 is used for receiving the pull-down clock signal LC2 and the first operation clock signal HC(n). The second auxiliary pull-down control circuit 12-2 is used to pull up the potential of the pull-down control signal K(n) in a floating state. The pull-down circuit 13-2 is used for receiving and pulling down the potential of the input signal Q(n) and the output signal G(n) to the reference potential VSS according to the pull-down control signal K(n) after the potential is pulled up.

FIG. 2 is a timing diagram of a shift register according to an embodiment of the present invention. As shown in FIG. 2 , the enable periods of the pull-down clock signal LC1 and the pull-down clock signal LC2 are complementary, that is, the pull-down clock signal LC1 and the pull-down clock signal LC2 are used to drive the voltage regulator module 101 and the voltage regulator module in turn 102 , thereby reducing the operation burden of the voltage regulator module 101 and the voltage regulator module 102 respectively. In some embodiments, the duty cycles of the pull-down clock signal LC1 and the pull-down clock signal LC2 are designed to be greater than 50%, so the enabling periods of the two may overlap each other for a part of the time, so as to ensure voltage regulation At least one of the module 101 and the voltage regulator module 102 is in a working state, thereby improving the operational reliability of the shift register 100 . Besides, the enable period of the pull-down clock signal LC1 and the pull-down clock signal LC2 is longer than the enable period of the first operating clock signal HC(n).

Referring to FIG. 1 and FIG. 2 , when the shift register 100 receives the input signal Q(n) but has not received the first operating clock HC(n), the input signal Q(n) has the potential VQ, and when the shift register 100 receives the first operating clock HC(n) During the period when the bit register 100 receives the first operating clock HC(n), the potential of the output signal G(n) is gradually pulled up to the potential VH of the first operating clock HC(n) through the transistor Ta. When the input signal Q(n) is raised from the potential VQ to the potential VH through the coupling of the capacitor Ca, while the input signal Q(n) and the output signal G(n) are enabled, the pull-down control signals P(n) and K( n) It is in a disabled state due to the low potential VL. When the input signal Q(n) and the output signal G(n) are in the disabled state of the low potential VL, the voltage regulator circuit 101 and the voltage regulator circuit 102 respectively receive the pull-down clock signal LC1 and the pull-down clock signal LC2 to stabilize the voltage Taking the circuit 101 as an example, when the voltage regulator circuit 101 has not received the first operating clock signal HC(n), the pull-down control signal P(n) output by the main pull-down control circuit 10-1 is at a high level VH, and During the period when the voltage regulator circuit 101 receives the first operating clock signal HC(n), the pull-down control signal P(n) with a high level is controlled by the first auxiliary pull-down circuit 11-1 to be in a floating state, and the floating connection The potential of the pull-down control signal P(n) will be pulled up to the potential VH' by the second auxiliary pull-down circuit 12-1, and the potential VH' after being pulled up is substantially twice the potential VH when it is not pulled up, The pull-down control signal P(n) after pulling up the potential enables the pull-down circuit 13-1 to pull down the input signal Q(n) and the output signal G(n) to the reference potential VSS more quickly.

Next, the circuit structure of each circuit in the voltage regulator module 101 will be described in detail. Since the circuit structures of the voltage stabilization module 102 and the voltage stabilization module 101 are substantially the same, the only difference is that they receive different pull-down clock signals LC1 and LC2 respectively. Therefore, the detailed circuit structure of the voltage-stabilizing module 102 will be It is omitted without further description.

FIG. 3 is a circuit diagram of a shift register according to an embodiment of the present invention. Please refer to FIG. 2 and FIG. 3 to read the following description. As shown in FIG. 3 , the main pull-down control circuit 10 - 1 includes a first transistor T51 , a second transistor T52 , a third transistor T53 and a fourth transistor T54 . The control terminal T51-3 of the first transistor T51 and the first terminal T51-1 of the first transistor T51 receive the pull-down clock signal LC1. The control terminal T52-3 of the second transistor T52 receives the input signal Q(n). The first terminal T52-1 of the second transistor T52 is electrically connected to the second terminal T51-2 of the first transistor T51. The two terminals T52-2 receive the reference potential VSS. The control terminal T53-3 of the third transistor T53 is electrically connected to the second terminal T51-2 of the first transistor T51, and the first terminal T53-1 of the third transistor T53 receives the pull-down clock signal LC1. The control terminal T54-3 of the fourth transistor T54 receives the input signal Q(n). The first terminal T54-1 of the fourth transistor T54 is electrically connected to the second terminal T53-2 of the third transistor T53. The two terminals T54-2 receive the reference potential VSS. When the pull-down clock signal LC1 is enabled, the second terminal T53-2 of the third transistor T53 outputs the pull-down control signal P(n).

Please continue to refer to FIG. 2 and FIG. 3 , the first auxiliary pull-down control circuit 11-1 includes a fifth transistor T55, the control terminal T55-3 of the fifth transistor T55 receives the first operating clock signal HC(n), and the fifth transistor T55 The first terminal T55-1 is electrically connected to the control terminal T53-3 of the third transistor T53, the second terminal T55-2 of the fifth transistor receives the reference potential VSS, and the fifth transistor T55 is based on the first operating clock signal HC(n ) to turn off the third transistor T53 so that the pull-down control signal P(n) is floating. The second auxiliary pull-down control circuit includes a coupling control transistor T56 and a coupling capacitor Cc. The control terminal T56-3 of the coupling control transistor T56 receives the pull-down clock signal LC1, and the first terminal T56-1 of the coupling control transistor T56 receives the first operating clock signal HC(n). One end of the coupling capacitor Cc is electrically connected to the second end T56-2 of the coupling control transistor T56, and the other end of the coupling capacitor Cc receives the pull-down control signal P(n), when the pull-down clock signal LC1 and the first operation clock signal HC When (n) is enabled, the coupling control transistor T56 controls the coupling capacitor Cc to couple the potential of the first operating clock signal HC(n) from one end of the coupling capacitor Cc to the other end of the coupling capacitor Cc, thereby pulling up The potential of the floating pull-down control signal P(n). As mentioned above, since the potential VH' after being pulled up is substantially twice the potential before being pulled up, the transistor T42 and the transistor T32 in the pull-down circuit 13-1 can be turned on more quickly, so that the The input signal Q(n) and the output signal G(n) are quickly pulled down to the reference potential VSS.

FIG. 4 is a circuit diagram of a voltage regulator module according to another embodiment of the present invention. The same reference numerals in FIGS. 3 and 4 denote the same elements or signals. As shown in FIG. 4 , the difference between the voltage stabilization module 401 and the aforementioned voltage stabilization module 101 is only that the first auxiliary pull-down control circuit 41 - 1 in the voltage stabilization module 401 further includes a sixth transistor T57 . The control terminal T57-3 of the sixth transistor T57 receives the second operating clock signal HC(n-1), the first terminal T57-1 of the sixth transistor T57 is electrically connected to the first terminal T55-1 of the fifth transistor T55, The second terminal T57-2 of the sixth transistor T57 receives the reference potential VSS. The second operating clock signal HC(n-1) is enabled earlier than the first operating clock signal HC(n). Before T55, the third transistor T53 is turned off to make the pull-down control signal floating.

FIG. 5 is a timing diagram of an operating clock signal according to an embodiment of the present invention. As shown in FIG. 5 , assuming that n is equal to 2, the operation clock signal HC1 is enabled earlier than the operation clock signal HC2 , and the enable period of the operation clock signal HC1 partially overlaps with the enable period of the operation clock signal HC2 . Please refer to FIG. 4 and FIG. 5 , in this embodiment, the operating period of the operating clock HC1 is substantially overlapped with the operating period of the operating clock HC2 by 50%, so the pull-down control signal P(n) can be controlled to float in advance In the connected state, the voltage regulator module 401 can immediately pull the pull-down control signal P(n) from the potential VH to VH' through the coupling capacitor Cc when it receives the operation clock signal HC2.

FIG. 6 is a circuit diagram of a voltage regulator module according to another embodiment of the present invention. The same reference numerals in FIGS. 4 and 6 denote the same elements or signals. As shown in FIG. 6 , the difference between the voltage stabilization module 601 and the aforementioned voltage stabilization module 401 is only that the first auxiliary pull-down control circuit 61-1 in the voltage stabilization module 601 further includes a seventh transistor T58 and an eighth transistor T58. Transistor T59. The first terminal T55-1 of the fifth transistor T55 is electrically connected to the control terminal T53-3 of the third transistor T53, and the second terminal of the fifth transistor T55 receives the reference potential VSS. The control terminal T57-3 of the sixth transistor T57 and the first terminal T57-1 of the sixth transistor T57 receive the first operating clock signal HC(n), and the second terminal T57-2 of the sixth transistor T57 is electrically connected to the fifth The control terminal T55-3 of the transistor T55. The control terminal T58-3 of the seventh transistor T58 and the first terminal T58-1 of the seventh transistor T58 receive the second operation clock signal HC(n-1), and the second terminal T58-2 of the seventh transistor T58 is electrically connected to the first terminal T58-2 of the seventh transistor T58. The control terminal T55-3 of the five transistors T55. The control terminal T59-3 of the eighth transistor T59 receives the third operating clock signal HC(n+2), the first terminal T59-1 of the eighth transistor T59 is electrically connected to the control terminal T55-3 of the fifth transistor T55, and the eighth transistor T59 is electrically connected to the control terminal T55-3 of the fifth transistor T55. The second terminal T59-2 of the transistor T59 receives the reference potential VSS.

Based on the above, the second operation clock signal HC(n-1) is enabled earlier than the first operation clock signal HC(n), and the third operation clock signal HC(n+2) is enabled later than the first operation clock signal Signal HC(n) is enabled. The sixth transistor T57 and the seventh transistor T58 turn on the fifth transistor T55 according to the first operating clock signal HC(n) and the second operating clock signal HC(n-1) respectively, thereby turning off the third transistor T53 to The pull-down control signal P(n) is left floating. Besides, the enable period of the second operation clock signal HC(n-1) overlaps with the enable period of the first operation clock signal HC(n), and the third operation clock signal HC(n+2 ) does not overlap with the enable period of the first operation clock signal HC(n).

Please refer to FIG. 5 and FIG. 6 to read the following description. As shown in FIG. 5 , assuming that n is equal to 2, the operation clock signal HC1 , the operation clock signal HC2 and the operation clock signal HC4 are sequentially enabled, and in this embodiment, the operation clock signal HC1 and the operation clock The working period of the pulse signal HC2 is substantially 50% overlapped, so the seventh transistor T58 can turn on the fifth transistor T55 and turn off the transistor T53 in advance, so that the pull-down control signal P(n) is in a floating state in advance, so as to ensure the voltage regulator module When receiving the operation clock signal HC2, 601 can instantly pull the pull-down control signal P(n) from the potential VH to VH' through the coupling capacitor Cc, and because the operation clock signal HC4 is immediately after the operation clock HC2 is enabled later, so the eighth transistor T59 can be turned off in time when the operation clock HC2 is disabled, and the pull-down control signal P(n) is not in a floating state.

FIG. 7 is a flowchart of a method for pulling down an output signal according to an embodiment of the present invention. As shown in FIG. 7 , the aforementioned pull-down operation of the output signal of the shift register can be summarized as a pull-down method of the output signal. This method is applicable to the aforementioned shift register, and the method includes steps S701~ S703. Step S701: Provide a pull-down clock signal to the main pull-down control circuit so that the main pull-down control circuit outputs the pull-down control signal. Step S702: Provide the first operating clock signal to the first auxiliary pull-down control circuit to control the pull-down control signal to be floating, and provide the pull-down clock signal and the first operating clock signal to the coupling control transistor to control the coupling capacitor, so as to The potential of the floating pull-down control signal is pulled up through the coupling action of the coupling capacitor. Step S703 : the pull-down circuit pulls down the output signal of the shift register to a reference potential according to the pull-down control signal after the potential is pulled up.

To sum up, the present invention realizes the shift register through the above-mentioned various circuit structures, and cooperates with the above-mentioned operation steps, firstly controls the pull-down control signal output by the main pull-down control circuit to float through the first auxiliary pull-down control circuit connected state, and then the potential of the pull-down control signal in the floating state is pulled up through the coupling capacitor in the second auxiliary pull-down control circuit, so that the potential of the pull-down control signal can be pulled up to exceed that received by the overall circuit. Therefore, it is not necessary to increase the size of the transistors in the pull-down circuit, and the signal pull-down capability of the pull-down circuit can also be improved, so that the pull-down circuit can pull down the output signal of the shift register to the reference potential more quickly to ensure the shift The output of the scratchpad is stable.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the invention shall be determined by the claims.

Claims (11)

1. A shift register, characterized in that, receiving and outputting an output signal according to an input signal and a first operating clock signal, the shift register comprising: a main pull-down control circuit for receiving the input signal, a pull-down clock signal and a reference potential, and for outputting a pull-down control signal; a first auxiliary pull-down control circuit, electrically connected to the main pull-down control circuit and used for receiving the reference potential, the first auxiliary pull-down control circuit is used for controlling the pull-down control signal to be floating; a second auxiliary pull-down control circuit for receiving the pull-down clock signal and the first operation clock signal, the second auxiliary pull-down control circuit for pulling up the potential of the floating pull-down control signal; as well as The pull-down circuit is used for receiving and pulling down the potential of the input signal and the output signal to the reference potential according to the pull-down control signal after the potential is pulled up. 2 . The shift register of claim 1 , wherein the second auxiliary pull-down control circuit comprises a coupling control transistor and a coupling capacitor, and a control terminal of the coupling control transistor receives the pull-down. 3 . a clock signal, a first end of the coupling control transistor receives the first operation clock signal, a first end of the coupling capacitor is electrically connected to a second end of the coupling control transistor, the coupling A second end of the capacitor receives the pull-down control signal, and when the pull-down clock signal and the first operation clock signal are enabled, the coupling control transistor controls the coupling capacitor to pass the coupling capacitor The potential of the first operating clock signal is coupled to the second end of the coupling capacitor to pull up the potential of the floating pull-down control signal. 3. The shift register of claim 1, wherein the main pull-down control circuit comprises a first transistor, a second transistor, a third transistor and a fourth transistor, the first transistor A control end of the transistor and a first end of the first transistor receive the pull-down clock signal, a control end of the second transistor receives the input signal, and a first end of the second transistor is powered is connected to a second terminal of the first transistor, a second terminal of the second transistor receives the reference potential, and a control terminal of the third transistor is electrically connected to the first terminal of the first transistor Two terminals, a first terminal of the third transistor receives the pull-down clock signal, a control terminal of the fourth transistor receives the input signal, and a first terminal of the fourth transistor is electrically connected to the A second end of the third transistor, a second end of the fourth transistor receives the reference potential, when the pull-down clock signal is enabled, the second end of the third transistor outputs the pull-down control signal. 4 . The shift register of claim 3 , wherein the first auxiliary pull-down control circuit comprises a fifth transistor, and a control terminal of the fifth transistor receives the first operating clock. 5 . signal, a first terminal of the fifth transistor is electrically connected to the control terminal of the third transistor, a second terminal of the fifth transistor receives the reference potential, and the fifth transistor is based on the The first operating clock signal turns off the third transistor so that the pull-down control signal is floating. 5 . The shift register of claim 4 , wherein the first auxiliary pull-down control circuit further comprises a sixth transistor, and a control terminal of the sixth transistor receives a second operating clock. 6 . signal, a first terminal of the sixth transistor is electrically connected to the first terminal of the fifth transistor, a second terminal of the sixth transistor receives the reference potential, and the second operating clock The signal is enabled earlier than the first operating clock signal, and the sixth transistor turns off the third transistor before the fifth transistor according to the second operating clock signal to enable the pull-down control The signal is floating. 6 . The shift register of claim 5 , wherein the enabling period of the second operating clock signal partially overlaps the enabling period of the first operating clock signal. 7 . 7. The shift register of claim 3, wherein the first auxiliary pull-down control circuit comprises a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, the A first end of the fifth transistor is electrically connected to the control end of the third transistor, a second end of the fifth transistor receives the reference potential, a control end of the sixth transistor and the A first end of the sixth transistor receives the first operating clock signal, a second end of the sixth transistor is electrically connected to a control end of the fifth transistor, and a control end of the seventh transistor and a first end of the seventh transistor receives a second operating clock signal, a second end of the seventh transistor is electrically connected to the control end of the fifth transistor, and a second end of the eighth transistor is electrically connected to the control end of the fifth transistor. The control terminal receives a third operating clock signal, a first terminal of the eighth transistor is electrically connected to the control terminal of the fifth transistor, and a second terminal of the eighth transistor receives the reference potential, the second operating clock signal is enabled earlier than the first operating clock signal, the third operating clock signal is enabled later than the first operating clock signal, the sixth transistor and The seventh transistor turns on the fifth transistor according to the first operating clock signal and the second operating clock signal respectively, thereby turning off the third transistor so that the pull-down control signal is floating catch. 8 . The shift register of claim 7 , wherein the enabling period of the second operating clock signal partially overlaps the enabling period of the first operating clock signal, and the first operating clock signal The enabling period of the third operating clock signal does not overlap with the enabling period of the first operating clock signal. 9 . The shift register of claim 1 , wherein the potential of the pull-down control signal after being pulled up is substantially twice that of the pull-down control signal when the pull-down control signal is not pulled up. 10 . 10. A method for pulling down an output signal of a shift register, wherein the shift register comprises a main pull-down control circuit, a first auxiliary pull-down control circuit, a second auxiliary pull-down control circuit, and a lower pull-down control circuit. a pull-down circuit, the second auxiliary pull-down control circuit includes a coupling control transistor and a coupling capacitor, the pull-down circuit is used for receiving the output signal of the shift register and a reference potential, and the pull-down method of the output signal includes : providing a pull-down clock signal to the main pull-down control circuit so that the main pull-down control circuit outputs a pull-down control signal; providing a first operating clock signal to the first auxiliary pull-down control circuit to control the pull-down control signal to be floating, and providing the pull-down clock signal and the first operating clock signal to the coupling controlling the transistor to control the coupling capacitor, so as to pull up the potential of the floating pull-down control signal through the coupling action of the coupling capacitor; and The pull-down circuit pulls down the output signal of the shift register to the reference potential according to the pull-down control signal after the potential is pulled up. 11 . The method for pulling down the output signal of the shift register as claimed in claim 10 , wherein the enable period of the pull-down clock signal is longer than the enable period of the first operation clock signal. 12 .