CN105141347B - Microminiature base station baseband processor chip set - Google Patents

Abstract

The invention provides a baseband processor chipset for an ultra-small base station, including: a receiving beamforming chipset, an antenna signal combining chipset, a user beam transmitting and receiving signal processing chipset, and a transmitting beamforming chipset; the receiving beamforming chipset passes the modulus The converter is connected to the receiving end of the L antennas of the ultra-small base station, the receiving beamforming chipset is connected to the antenna signal combining chipset, the user beam transmitting and receiving signal processing chipset is connected to the antenna signal combining chipset, and the transmitting beamforming chipset is respectively connected, The transmitting beamforming chipset is connected to the transmitting ends of the L antennas of the ultra-small base station through a digital-to-analog converter, where L is an integer greater than 1. The above-mentioned ultra-small base station baseband processor chipset can solve the problems of pin, power consumption, and area constraints caused by ultra-large antenna arrays and super-large calculations, and minimize the hardware overhead of the all-digital beamforming structure through slice optimization.

Description

Ultra-Small Base Station Baseband Processor Chipset

technical field

The invention relates to the technical field of wireless communication baseband processors, in particular to a baseband processor chipset for ultra-small base stations.

Background technique

The fifth-generation mobile communication technology (5-Generation, referred to as 5G) will bring various technological innovations to the currently widely used wireless communication, which is reflected in ultra-high transmission bandwidth, ultra-low communication delay, and higher spectrum utilization efficiency. Based on the requirements of 5G, ultra-large-scale antenna array and beamforming technology may become the key technology of 5G communication.

The ultra-small hotspot base station is a base station system suitable for 5G ultra-dense networking application scenarios. Its application scenarios cover indoor and outdoor situations such as offices, campuses, dense blocks, and slow vehicles, and usually cover a radius of less than 100 meters. Each 5G ultra-small base station will provide users within its coverage area with broadband data transmission services at a total rate of up to 10 gigabits per second. The forecast results show that the global annual output of 5G ultra-small base stations will dominate all types of 5G communication base stations.

Ultra-small base stations need to support their high-bandwidth data transmission requirements through ultra-large-scale antenna arrays. Generally, in order to satisfy the wireless transmission in the scenarios covered above, a two-dimensional antenna array with hundreds of antennas is required. At the same time, due to the limitation of the physical size of the antenna, the carrier wavelength needs to be short enough. The millimeter wave band is one of the hotspots of many wireless communication applications. Applying wireless transmission in this band, for example, using 60 GHz radio frequency can reduce the spacing of the antenna array to about 2.5mm, and the overall size of the antenna array is also greatly reduced.

Since the millimeter wave has a large transmission loss, it is necessary to use beamforming technology to provide directional high energy gain for the micro base station. Existing hardware implementation structural schemes for beamforming of base stations mainly include three types. First, RF analog beamforming. Second, full digital beamforming. Third, analog-digital hybrid beamforming. Among these structural schemes, RF analog beamforming has the lowest overhead, and all-digital beamforming has the best performance. Analog-digital hybrid beamforming is a compromise between the two.

For the above-mentioned hardware implementation structure scheme, there is no mature research on the hardware implementation of the system-on-chip. The hardware implementation of the SoC needs to consider various constraints, including algorithm-level constraints, pin constraints, power consumption constraints, and area constraints. For base stations based on very large-scale antenna array-based beamforming technology, the input and output signal throughput is very high. Processing chips can easily exceed the pin constraints dictated by the process. In addition, for baseband processing with a large amount of broadband computing, if you do not choose a suitable algorithm and structure, and perform reasonable sliced multi-core processing, it is difficult to meet the power consumption and area constraints of ultra-small base stations.

In view of this, how to provide an ultra-small base station baseband processor chip composition that can solve the pin, power consumption, and area constraints caused by ultra-large antenna arrays and ultra-large calculations has become a technical problem that needs to be solved at present.

Contents of the invention

The present invention provides a baseband processor chipset for an ultra-small base station, which is applied to an ultra-small hotspot base station for 5G wireless communication, can be flexibly configured, and can solve the problems of pins, power consumption, and area constraints caused by ultra-large antenna arrays and ultra-large calculations. , and minimize the hardware overhead of the all-digital beamforming structure through slice optimization.

In a first aspect, the present invention provides a baseband processor chipset for an ultra-small base station, including: a receiving beamforming chipset, an antenna signal combining chipset, a user beam transmitting and receiving signal processing chipset, and a transmitting beamforming chipset;

The receiving beamforming chipset is connected to the receiving end of the L antennas of the ultra-small base station through an analog-to-digital converter, the receiving beamforming chipset is connected to the antenna signal combining chipset, and the user beam transmitting and receiving signal processing chip The group is connected to the antenna signal combining chipset and the transmit beamforming chipset respectively, and the transmit beamforming chipset is connected to the transmitting ends of the L antennas of the ultra-small base station through a digital-to-analog converter, where L is greater than 1 integer.

Optionally, the receiving beamforming chipset includes: M receiving beamforming chips, where M is an integer greater than 1;

The receiving beamforming chip includes: a first multiplication module, an antenna combining module and an output buffer module;

The first complex multiplication module includes: K groups, U high-speed fixed-point complex multiplication units in each group, and K and U are integers greater than 1;

The complex multiplication unit is configured to perform beamforming weighting operations on signals received from K antennas;

The antenna combination module includes: U first addition units;

The first adding unit is an accumulator with U input and single output, and is used to combine the signals belonging to the same receiving area among the signals received from the K antennas after the beamforming weighted operation is performed by the complex multiplication unit ;

The output buffer module is a high-speed parallel random access memory RAM, which is used for temporarily storing the combined signals of the U first adding units and outputting them to the antenna signal combining chipset.

Optionally, the antenna signal combination chipset includes: a plurality of antenna signal combination chips arranged and connected in the form of dual-input and single-output, used to combine the output signals of the receiving beamforming chipset, and output the combined signal To the user beam transceiver signal processing chipset.

Optionally, the user beam transmitting and receiving signal processing chipset includes: N mutually parallel user beam transmitting and receiving signal processing chips, which are used to parallelly process received signals from at most U beamforming areas, and communicate with the macro base station, and at the same time Process the downlink data from the macro base station, modulate the downlink signals of U beamforming transmission areas at most, and output the modulated signals to the transmitting beamforming chipset, where N and U are both integers greater than 1.

Optionally, the user beam transceiving signal processing chip includes: an uplink signal processing part and a downlink signal processing part;

The uplink signal processing part includes: a filtering and fast Fourier transform module, a channel estimation module, a channel equalization module, a demapping module, a deinterleaving module, a forward error correction coding module and a first cyclic redundancy check module;

The filtering and fast Fourier transform module includes: a delay chain register group, a multi-channel parallel filter processor and a fast Fourier transform processor;

The filter processor includes a two-dimensional parallel multiplication-addition operation unit based on single instruction multiple data, which cooperates with the delay chain register group to complete multi-order filter operations within one clock cycle;

The fast Fourier transform processor includes: a complex butterfly unit, which is used to realize low-delay Fourier transforms of various lengths for sequences of integer powers of 2;

The channel estimation module is used to perform channel estimation on the Fourier transformed signal;

The channel equalization module is used for channel equalization after channel estimation;

The demapping module is used to perform a bit detection operation on the signal after channel equalization;

The deinterleaving module is used to deinterleave the signal after the bit detection operation;

The forward error correction coding module is used to perform forward error correction coding on the deinterleaved signal;

The first cyclic redundancy check module is configured to perform a cyclic redundancy check on the forward error correction coded signal;

The downlink signal processing part includes: a second cyclic redundancy check module, a channel coding module, a modulation module and an inverse fast Fourier transform module;

The second cyclic redundancy check module is configured to perform cyclic redundancy check on the input signal;

The channel encoding module is configured to encode the signal after the cyclic redundancy check;

The modulation module is used to modulate the encoded signal;

The inverse fast Fourier transform module is used to perform inverse fast Fourier transform on the modulated signal.

Optionally, the channel estimation module and the channel equalization module are fixed-point matrix-function processors;

The fixed-point matrix-function processor includes: a multi-layer multiplication addition and data rearrangement unit and a function operation acceleration unit;

The multi-layer multiplication addition and data rearrangement unit is used to perform basic vector operations including vector addition and subtraction, vector product, vector dot product, and transposition of real numbers and complex numbers;

The function operation acceleration unit is used to realize special function operations with preset accuracy within a maximum of preset clock cycles through a polynomial estimation algorithm;

and / or,

The demapping module is used to perform a bit detection operation on the signal after channel equalization by using a bit detection algorithm;

and / or,

The de-interleaving module adopts a dedicated processor for forward error correction encoding and decoding;

and / or,

The forward error correction encoding module adopts a special processor for forward error correction encoding and decoding;

and / or,

The first cyclic redundancy check module is used to use the bit processor to cooperate with the register, and the low-latency operation of the parallel cyclic redundancy check CRC algorithm based on the look-up method performs cyclic redundancy check on the signal after forward error correction coding;

and / or,

The channel coding module is a simple coding and modulation circuit with low overhead;

and / or,

The modulation module is a simple encoding and modulation circuit with low overhead.

Optionally, the transmit beamforming chipset includes: M pieces of transmit beamforming chips;

The transmit beamforming chip is used to sequentially perform beamforming, digital predistortion and shaping filter processing on the signal modulated and output by the user beam transmitting and receiving signal processing chipset, and output the processed signal to the K of the ultra-small base station antenna transmitter.

Optionally, the transmit beamforming chip includes: an input buffer module, a second multiplex module, a user signal combining module, a digital predistortion module and a shaping filter module;

The input buffer module is configured to temporarily store and process the signal modulated and output by the user beam transceiver signal processing chipset and output it to the second multiplex module;

The second multiplication module is configured to perform a transmit beamforming weighting operation on the output signal of the input buffer module;

The user signal combining module includes K second adding units;

The second addition unit is an accumulator with a U input and a single output, and is used to combine the U channel signals after the transmit beamforming weighting operation is performed by the second multiplex module;

The digital pre-distortion module is used to pre-compensate the transmission power of the signal combined by the user signal combination module through a digital circuit;

The shaping filter module is used to perform pulse shaping filtering on the precompensated signal, and output the pulse shaping filtering signal to the antenna transmitting end of the ultra-small base station, so that the antenna transmitting end can filter the pulse shaping After the signal is digital-to-analog converted, it is sent.

Optionally, the shaping filter module is a high-speed digital filter.

Optionally, the receiving beamforming chipset is connected to the receiving ends of the L antennas of the ultra-small base station through an analog-to-digital converter through a first differential port, and the transmitting beamforming chipset is connected through a digital-to-analog conversion through a first differential port The device is connected to the transmitting end of the L antennas of the ultra-small base station; the receiving beamforming chipset is connected to the antenna signal combining chipset using a second differential port, and the transmitting beamforming chipset is connected to the antenna signal combining chipset using a second differential port The user beam transmitting and receiving signal processing chipset is connected, and the antenna signal combining chipset is connected to the user beam transmitting and receiving signal processing chipset through a second differential port;

The first differential port matches the sampling rate of the analog-to-digital converter and the digital-to-analog converter, the analog-to-digital converter and the digital-to-analog converter adopt the same rate, and the second differential port and the intermediate The digital signal transmission rate is matched, and the rate of the first differential port is different from that of the second differential port.

It can be seen from the above technical solution that the ultra-small base station baseband processor chipset of the present invention is applied to 5G wireless communication ultra-small hotspot base stations, can be flexibly configured, and can solve the problem of pins and power consumption caused by ultra-large antenna arrays and ultra-large calculations. , area-constrained problems, and minimize the hardware overhead of an all-digital beamforming structure through slice optimization.

Description of drawings

FIG. 1 is a schematic structural diagram of a baseband processor chipset for an ultra-small base station provided by an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a receive beamforming chip in the ultra-small base station baseband processor chipset shown in FIG. 1;

3 is a schematic structural diagram of the uplink part of the user beam transceiver signal processing chip in the ultra-small base station baseband processor chipset shown in FIG. 1;

Fig. 4 is a structural schematic diagram of the downlink part of the user beam transceiving signal processing chip in the ultra-small base station baseband processor chipset shown in Fig. 1;

FIG. 5 is a schematic structural diagram of a transmit beamforming chip in the ultra-small base station baseband processor chipset shown in FIG. 1;

FIG. 6 is a schematic diagram of a connection mode of an antenna signal combining chipset in the ultra-small base station baseband processor chipset shown in FIG. 1 .

Detailed ways

The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

Fig. 1 shows a schematic structural diagram of an ultra-small base station baseband processor chipset provided by an embodiment of the present invention. As shown in Fig. 1, the ultra-small base station baseband processor chipset of this embodiment includes: a receiving beamforming chipset 11. Antenna signal combining chipset 12, user beam transmitting and receiving signal processing chipset 13 and transmitting beamforming chipset 14;

The receiving beamforming chipset 11 is connected to the receiving end of the L antennas of the ultra-small base station through an analog-to-digital converter 15, the receiving beamforming chipset 11 is connected to the antenna signal combining chipset 12, and the user beamforming The transceiver signal processing chipset 13 is connected to the antenna signal combining chipset 12 and the transmitting beamforming chipset 14 respectively, and the transmitting beamforming chipset 14 is connected to the L antennas of the ultra-small base station through a digital-to-analog converter 16. The sender is connected, and L is an integer greater than 1.

In a specific application, the receiving beamforming chipset 11 in this embodiment may include: M receiving beamforming chips, where M is an integer greater than 1;

The receiving beamforming chip, as shown in FIG. 2 , may include: a first multiplication module 11a, an antenna combining module 11b, and an output buffer module 11c;

The first complex multiplication module 11a may include: K groups, each group of U high-speed fixed-point complex multiplication units, K and U are integers greater than 1;

The complex multiplication unit is configured to perform beamforming weighting operations on signals received from K antennas;

The antenna combining module 11b may include: U first adding units;

The first adding unit is an accumulator with U input and single output, and is used to combine the signals belonging to the same receiving area among the signals received from the K antennas after the beamforming weighted operation is performed by the complex multiplication unit ;

The output buffer module 11c is a high-speed parallel random access memory RAM, which is used for temporarily storing the combined signals of the U first adding units and outputting them to the antenna signal combining chipset.

It can be understood that the number of antennas connected to each receiving beamforming chip is K, and there are M receiving beamforming chips, so the total number of antennas of the base station L=K×M.

In a specific application, the antenna signal combination chip set 12 in this embodiment may include: a plurality of antenna signal combination chips arranged and connected in the form of dual input and single output, for combining the output signals of the receiving beamforming chip set, Output the combined signal to the user beam transceiver signal processing chipset 13 .

Fig. 6 shows a schematic diagram of a connection mode of an antenna signal combining chipset in the ultra-small base station baseband processor chipset shown in Fig. 1, as shown in Fig. 6, and Fig. 6 takes the number of receiving beamforming chips as In the case of 12 as an example, a total of 10 antenna signal combining chips are interconnected in a dual-input-single-output basic connection mode, including 6 first-stage signal combining chips, 3 second-stage signal combining chips and 1 A third-stage signal combining chip; these chips are arranged and connected in the form of an inverted triangle, and each first-stage signal combining chip further combines the signals from two receiving beamforming chips; each second and third-stage signal Merge the chips to further merge the output signals of the merged chips in the previous stage. The signals combined in two or three stages are input to the processing chip of the user beam receiving and sending signals for the final stage of combining. After each stage of signal combining operation, the signal to be processed is additionally increased by 1 bit word length.

In a specific application, the user beam transmitting and receiving signal processing chipset 13 described in this embodiment may include: N mutually parallel user beam transmitting and receiving signal processing chips, which are used to parallelly process the received signals from at most U beamforming areas, and communicate with The macro base station communicates, processes the downlink data from the macro base station at the same time, modulates the downlink signals of U beamforming transmission areas at most, and outputs the modulated signal to the transmission beamforming chipset, and both N and U are greater than 1 an integer of . For example, U may be preferably 10.

Wherein, the user beam transmitting and receiving signal processing chip may include: an uplink signal processing part and a downlink signal processing part;

The uplink signal processing part, as shown in Figure 3, may include: a filtering and fast Fourier transform module, a channel estimation module, a channel equalization module, a demapping module, a deinterleaving module, a forward error correction coding module and a first Cyclic redundancy check module;

The filtering and fast Fourier transform module may include: a delay chain register group, a multi-channel parallel filter processor and a fast Fourier transform processor;

The filter processor includes a two-dimensional parallel multiplication-addition operation unit based on single instruction multiple data (equipped with a multiplication-add instruction set with optional length and precision), which cooperates with the delay chain register group to be used in one clock cycle (By programming) to complete multi-order filtering operations, the filter processor can realize various orders of finite impulse response filtering, infinite impulse response filtering, Algorithm functions such as signal autocorrelation and cross-correlation;

The fast Fourier transform processor includes: a complex butterfly unit, which is used (with the support of the instruction set) to realize low-delay Fourier transforms of various lengths for sequences of integer powers of 2 (with the support of the instruction set), that is, its data channel adopts The multiplication and addition structure of complex butterfly with high parallelism can complete multiple complex butterfly operations such as 8-way parallel base 2, 4-way parallel base 4, 2-way parallel base 8 and single-way base 16 within one clock cycle. Program to realize low-latency fast Fourier transform of various lengths;

The channel estimation module is used to perform channel estimation on the Fourier transformed signal;

The channel equalization module is used for channel equalization after channel estimation;

The demapping module is used to perform bit detection operations on the signal after channel equalization, that is, through theoretical formula simplification, complex arithmetic operations such as exponentials and logarithms are converted into approximate operations based on maximum and minimum values, and mapping To a simple look-up table circuit and numerical comparison circuit, the hardware complexity is greatly reduced;

The deinterleaving module is used to deinterleave the signal after the bit detection operation;

The forward error correction coding module is used to perform forward error correction coding on the deinterleaved signal;

The first cyclic redundancy check module is configured to perform cyclic redundancy check on the forward error correction coded signal.

Further, both the channel estimation module and the channel equalization module may be fixed-point matrix-function processors;

The fixed-point matrix-function processor may include: a multi-layer multiplication addition and data rearrangement unit and a function operation acceleration unit;

The multi-layer multiplication addition and data rearrangement unit is used to perform basic vector operations including vector addition and subtraction of real numbers and complex numbers, vector products, vector dot products, and transpositions;

The function operation acceleration unit is used to realize the special function operation with preset precision within at most preset clock cycles through polynomial estimation algorithm.

For example, the preset number of clock cycles may preferably be 10 clock cycles, and the preset precision may preferably be 16-bit precision.

The matrix-function processor can realize high-efficiency, conflict-free, and low-latency operations through data pre-allocation and programming for core operations such as matrix LU decomposition, QR decomposition, and inversion used in channel estimation and channel equalization algorithms.

In a specific application, the demapping module can be used to perform a bit detection operation on the channel-equalized signal by using a bit detection algorithm (that is, perform bit data demapping on the channel-equalized signal).

For example, preferably, the demapping module may be configured to perform bit detection operations on the channel-equalized signal by using a Maximum Logarithm MAP (Max-Log-Map for short) algorithm.

Preferably, both the de-interleaving module and the forward error correction encoding module can use a special processor for forward error correction codec, and the special processor for forward error correction codec is preferably a high-throughput, low-overhead front-end A dedicated processor for error correction codecs.

Preferably, the first cyclic redundancy check module is used to use a bit processor to cooperate with the register, and can perform forward correction based on the low-latency operation of the parallel cyclic redundancy check (Cyclic Redundancy Check, CRC) algorithm of the look-up method. Cyclic redundancy check is performed on the signal after wrong coding. The first cyclic redundancy check module adopts a parallel logical operation data channel, cooperates with a register file to perform a parallel CRC algorithm based on a table look-up method, and can realize low-cost cyclic redundancy check algorithms including CRC8, CRC16, CRC24, and CRC32. delayed operation.

Wherein, the downlink signal processing part, as shown in FIG. 3 , may include: a second cyclic redundancy check module, a channel coding module, a modulation module and an inverse fast Fourier transform module;

The second cyclic redundancy check module is configured to perform cyclic redundancy check on the input signal;

The channel encoding module is configured to encode the signal after the cyclic redundancy check;

The modulation module is used to modulate the encoded signal;

The inverse fast Fourier transform module is used to perform inverse fast Fourier transform on the modulated signal.

Preferably, both the channel coding module and the modulation module can be simple coding and modulation circuits with low overhead.

It can be understood that the second cyclic redundancy check module and the first cyclic redundancy check module of this embodiment may use the same processor hardware, but run different software codes; the inverse fast Fourier The transform module may employ the above-mentioned fast Fourier transform processor, on which the inverse fast Fourier transform is run.

In a specific application, the transmit beamforming chipset 14 described in this embodiment may include: M pieces of transmit beamforming chips;

The transmit beamforming chip is used to sequentially perform beamforming, digital predistortion and shaping filter processing on the signal modulated and output by the user beam transmitting and receiving signal processing chipset, and output the processed signal to the K of the ultra-small base station antenna transmitter.

Further, the transmit beamforming chip, as shown in FIG. 5 , may include: an input buffer module 14a, a second multiplex module 14b, a user signal combining module 14c, a digital predistortion module 14d and a shaping filter module 14e;

The input buffer module 14a is configured to temporarily store and process the signal modulated and output by the user beam transceiver signal processing chipset and output it to the second multiplex module;

The second multiplication module 14b is configured to perform transmit beamforming weighting operations on the output signal of the input buffer module;

The user signal combining module 14c includes K second adding units;

The second addition unit is an accumulator with a U input and a single output, and is used to combine the U channel signals after the transmit beamforming weighting operation is performed by the second multiplex module;

The digital pre-distortion module 14d is configured to pre-compensate the transmission power of the signals combined by the user signal combining module through a digital circuit;

The shaping filter module 14e is configured to perform pulse shaping filtering on the precompensated signal, and output the pulse shaping filtering signal to the antenna transmitting end of the ultra-small base station, so that the antenna transmitting end can shape the pulse The filtered signal is sent after digital-to-analog conversion.

Preferably, the shaping filter module 14e may be a high-speed digital filter.

In specific applications, the embodiment of the present invention can adopt two high-speed differential ports with different rates:

The receiving beamforming chipset 11 is connected to the receiving end of the L antennas of the ultra-small base station through the analog-to-digital converter 15 through the first differential port, and the transmitting beamforming chipset 14 is connected through the digital-to-analog converter through the first differential port. 16 is connected to the transmitting end of the L antennas of the ultra-small base station; the receiving beamforming chipset 11 is connected to the antenna signal combining chipset 12 using a second differential port, and the transmitting beamforming chipset 14 is connected to the second differential port The port is connected to the user beam transceiver signal processing chipset 13, and the antenna signal combining chipset 12 is connected to the user beam transceiver signal processing chipset 13 using a second differential port; the first differential port is connected to the module The digital-to-analog converter and the sampling rate of the digital-to-analog converter 16 are matched, the digital-to-analog converter 16 and the analog-to-digital converter 15 adopt the same rate, and the second differential port has the same transmission rate as the intermediate digital signal matching, the rates of the first differential port and the second differential port are different.

It should be noted that the first differential port includes the overall input and output ports of the system, that is, the input port of the receiving beamforming chipset 11 connected to the analog-to-digital converter 15, and the transmitting beamforming chipset connected to the digital-to-analog converter 16 14 output ports (the digital-to-analog converter 16 and the analog-to-digital converter 15 adopt the same rate); the second differential port includes the transmission ports of all intermediate digital signals of the system, that is, the output port of the receiving beamforming chipset 11, the transmitting beamforming The input port of the chipset 14, and all input and output ports of the antenna signal combination chipset 12 and the user beam transceiving signal processing chipset 13 (that is, the output end of the receiving beamforming chipset 11 and the antenna signal combination chip The connection of the group 12, the connection of the antenna signal combining chipset 12 and the user beam transmitting and receiving signal processing chipset 13, and the connection of the input end of the user beam transmitting and receiving signal processing chipset 13 and the transmitting beamforming chipset 14 all adopt the second differential port ). Wherein, the rate of the second differential port may preferably be twice that of the first differential port.

For example, using an example of an ultra-small hotspot base station in a 5G application scenario, the configuration parameters and configuration methods of the chipset structure are described. In this application scenario, the hotspot base station provides broadband data access for users in 10 beam areas within a radius of 50 meters through 128 antenna Multi-input Multi-output (MIMO). For this application scenario, in order to meet the minimum hardware overhead and meet design constraints such as pins, power consumption, and area, the number of chips in the chipset structure is configured as follows: chips included in the receive beamforming chipset and the transmit beamforming chipset Number M=12, each receiving and transmitting beamforming chip processes received data on up to 11 antennas; the antenna signal combining chip group is divided into three stages, each stage has 6, 3 and 1 signal combining chips respectively; The number of chips included in the user beam transmitting and receiving signal processing chipset is N=2, and each user beam transmitting and receiving signal processing chip processes signals of five independent beamforming areas. Under such a chip number configuration, according to software simulation calculations, the digital chips in the baseband system can simultaneously meet the chip pin number requirements (up to 1000 pins), area constraints (maximum chip area of 45 square millimeters) and low power consumption constraints ( Maximum power consumption chip 3.4 watts). The number of shared chips in this configuration is 36, which realizes the design goal of minimum hardware overhead of the baseband processor.

The ultra-small base station baseband processor chipset of this embodiment is applied to 5G wireless communication ultra-small hotspot base stations. The main modules in the chipset are designed based on software defined radios and can be programmed flexibly. The chipset structure itself can be flexibly configured to adapt to different The number of antennas, user rates, different frequency bands (6 to 40 GHz and above) and bandwidth, for each application, the lowest hardware cost can be obtained through configuration, which can solve the problems of pins and power consumption generated by very large antenna arrays and large calculations , area-constrained problems, and minimize the hardware overhead of an all-digital beamforming structure through slice optimization.

Those of ordinary skill in the art can understand that all or part of the steps for implementing the above method embodiments can be completed by program instructions and related hardware. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps including the above-mentioned method embodiments; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other various media that can store program codes.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions depart from the protection scope of the claims of the present invention .

Claims (8)

1. A baseband processor chipset for an ultra-small base station, comprising: a receiving beamforming chipset, an antenna signal combining chipset, a user beam transceiving signal processing chipset and a sending beamforming chipset; The receiving beamforming chipset is connected to the receiving end of the L antennas of the ultra-small base station through an analog-to-digital converter, the receiving beamforming chipset is connected to the antenna signal combining chipset, and the user beam transmitting and receiving signal processing chip The group is connected to the antenna signal combining chipset and the transmit beamforming chipset respectively, and the transmit beamforming chipset is connected to the transmitting ends of the L antennas of the ultra-small base station through a digital-to-analog converter, where L is greater than 1 integer; The receiving beamforming chipset uses the first differential port to connect to the receiving ends of the L antennas of the ultra-small base station through the analog-to-digital converter, and the transmitting beamforming chipset uses the first differential port to connect to the ultra-small antennas through the digital-to-analog converter. The transmitting ends of the L antennas of the base station are connected; the receiving beamforming chipset is connected to the antenna signal combining chipset through a second differential port, and the transmitting beamforming chipset is connected to the user beam through a second differential port The signal processing chipset is connected, and the antenna signal combining chipset is connected to the user beam sending and receiving signal processing chipset through a second differential port; The first differential port matches the sampling rate of the analog-to-digital converter and the digital-to-analog converter, the analog-to-digital converter and the digital-to-analog converter adopt the same rate, and the second differential port and the intermediate The digital signal transmission rate is matched, and the rate of the first differential port is different from that of the second differential port. 2. The baseband processor chipset according to claim 1, wherein the receiving beamforming chipset comprises: M receiving beamforming chips, where M is an integer greater than 1; The receiving beamforming chip includes: a first multiplication module, an antenna combining module and an output buffer module; The first complex multiplication module includes: K groups, U high-speed fixed-point complex multiplication units in each group, and K and U are integers greater than 1; The complex multiplication unit is configured to perform beamforming weighting operations on signals received from K antennas; The antenna combination module includes: U first addition units; The first adding unit is an accumulator with U input and single output, and is used to combine the signals belonging to the same receiving area among the signals received from the K antennas after the beamforming weighted operation is performed by the complex multiplication unit ; The output buffer module is a high-speed parallel random access memory RAM, which is used for temporarily storing the combined signals of the U first adding units and outputting them to the antenna signal combining chipset. 3. The baseband processor chipset according to claim 1, wherein the antenna signal combining chipset comprises: a plurality of antenna signal combining chips arranged and connected in a double-input and single-output form, for combining the receiving beam The output signals of the forming chipset are combined, and the combined signals are output to the user beam transmitting and receiving signal processing chipset. 4. The baseband processor chipset according to claim 1, wherein the user beam transceiver signal processing chipset comprises: N mutually parallel user beam transceiver signal processing chips for parallel processing from up to U Receive signals in the beamforming area, communicate with the macro base station, process downlink data from the macro base station at the same time, modulate the downlink signals of U beamforming transmission areas at most, and output the modulated signal to the transmitting beamforming chip group, N and U are both integers greater than 1. 5. The baseband processor chipset according to claim 4, wherein the user beam transceiver signal processing chip comprises: an uplink signal processing part and a downlink signal processing part; The uplink signal processing part includes: a filtering and fast Fourier transform module, a channel estimation module, a channel equalization module, a demapping module, a deinterleaving module, a forward error correction coding module and a first cyclic redundancy check module; The filtering and fast Fourier transform module includes: a delay chain register group, a multi-channel parallel filter processor and a fast Fourier transform processor; The filter processor includes a two-dimensional parallel multiplication-addition operation unit based on single instruction multiple data, which cooperates with the delay chain register group to complete multi-order filter operations within one clock cycle; The fast Fourier transform processor includes: a complex butterfly unit, which is used to realize low-delay Fourier transforms of various lengths for sequences of integer powers of 2; The channel estimation module is used to perform channel estimation on the Fourier transformed signal; The channel equalization module is used for channel equalization after channel estimation; The demapping module is used to perform a bit detection operation on the signal after channel equalization; The deinterleaving module is used to deinterleave the signal after the bit detection operation; The forward error correction coding module is used to perform forward error correction coding on the deinterleaved signal; The first cyclic redundancy check module is configured to perform a cyclic redundancy check on the forward error correction coded signal; The downlink signal processing part includes: a second cyclic redundancy check module, a channel coding module, a modulation module and an inverse fast Fourier transform module; The second cyclic redundancy check module is configured to perform cyclic redundancy check on the input signal; The channel encoding module is configured to encode the signal after the cyclic redundancy check; The modulation module is used to modulate the encoded signal; The inverse fast Fourier transform module is used to perform inverse fast Fourier transform on the modulated signal. 6. The baseband processor chipset according to claim 1, wherein the sending beamforming chipset comprises: M slices sending beamforming chips; The transmit beamforming chip is used to sequentially perform beamforming, digital predistortion and shaping filter processing on the signal modulated and output by the user beam transmitting and receiving signal processing chipset, and output the processed signal to the K of the ultra-small base station antenna transmitter. 7. The baseband processor chipset according to claim 6, wherein the transmitting beamforming chip comprises: an input buffer module, a second multiplex module, a user signal combining module, a digital predistortion module and a shaping filter module ; The input buffer module is configured to temporarily store and process the signal modulated and output by the user beam transceiver signal processing chipset and output it to the second multiplex module; The second multiplication module is configured to perform a transmit beamforming weighting operation on the output signal of the input buffer module; The user signal combining module includes K second adding units; The second addition unit is an accumulator with a U input and a single output, and is used to combine the U channel signals after the transmit beamforming weighting operation is performed by the second multiplex module; The digital pre-distortion module is used to pre-compensate the transmission power of the signal combined by the user signal combination module through a digital circuit; The shaping filter module is used to perform pulse shaping filtering on the precompensated signal, and output the pulse shaping filtering signal to the antenna transmitting end of the ultra-small base station, so that the antenna transmitting end can filter the pulse shaping After the signal is digital-to-analog converted, it is sent. 8. The baseband processor chipset according to claim 7, wherein the shaping filter module is a high-speed digital filter.