CN105099475A - Improved radio receiver - Google Patents

Abstract

A baseband signal conditioning architecture for radio receivers that uses switched capacitor technology to provide high performance signal conditioning in low voltage, deep submicron processes such as 65nm and smaller. In this architecture, a first mixer is coupled to an antenna that receives a signal and outputs a first mixer output signal based on a signal received by the antenna. A buffer coupled to the first mixer output outputs a buffer signal based on the first mixer output signal. A first charge pump is coupled to the output of the buffer and generates a first charge pump output signal based on the buffer signal. In some embodiments, a second charge pump is coupled to the output of the first mixer and generates a second charge pump output signal based on the first mixer output signal, and the buffer input is coupled to the output of the second charge pump. output.

Description

Improved radio receiver

Cross References to Related Applications

This application claims priority to US Provisional Patent Application No. 61/994,671 filed in the US Patent and Trademark Office on May 16, 2014, the entire disclosure of which is hereby incorporated by reference.

Background technique

Designing radio receivers using conventional architectures in integrated circuit fabrication technologies with feature sizes of 65 nanometers (nm) or less presents significant challenges. These challenges include limited dynamic range caused by low supply voltages, low intrinsic voltage gain from transistors, high flicker noise corners, difficulties in cascaded transistors caused by headroom issues, and field-effect transistors (FETs) ) in general weird behavior in these processes.

Therefore, there is a need for an improved radio receiver architecture that can provide high performance even in small feature size manufacturing technologies.

Contents of the invention

The present teachings alleviate one or more of the above-mentioned problems with built-in radio receivers.

According to an exemplary embodiment, a radio receiver includes: an antenna configured to receive a signal, a first mixer, a buffer, a first charge pump. A first mixer is coupled to the antenna and configured to output a first mixer output signal based on a signal received by the antenna. The buffer has a buffer input coupled to the first mixer output and is configured to output a buffer signal at the buffer output based on the first mixer output signal. A first charge pump is coupled to the buffer output and configured to generate a first charge pump output signal based on the buffer signal.

The radio receiver may further include a second charge pump coupled to the output of the first mixer and configured to generate a second charge based on the first mixer output signal pump output signal. The buffer input may be coupled to the output of the second charge pump, and the buffer may be configured to output the buffer signal at the buffer output based on the second charge pump output signal , the second charge pump output signal itself is based on the first mixer output signal.

The first and second charge pumps may be switched capacitor charge pumps each having a plurality of sampling capacitors.

The second charge pump may be configured to periodically sample the first mixer output signal on each of the plurality of sampling capacitors of the second charge pump during a sampling interval, and during an output interval, The plurality of sampling capacitors are periodically reconfigured in series at the output end of the second charge pump.

The first mixer, the first charge pump and the second charge pump may each receive a differential signal at their input and output a differential signal at their output.

The radio receiver may also include a chopper stabilization circuit coupled between the output of the second charge pump and the input of the first charge pump, the chopper tor stabilization circuit including the buffer.

The first charge pump may further include a capacitance circuit having an adjustable capacitance coupled between a plurality of sampling capacitors of the first charge pump and an output terminal of the first charge pump between. The adjustable capacitor may be configured to be adjusted to adjust the bandwidth of the first charge pump.

The radio receiver may also include a third charge pump coupled to the output of the first charge pump and configured to generate a third charge pump output based on the first charge pump output signal Signal. At least one of the first charge pump, the second charge pump and the third charge pump may have an adjustable gain.

The third charge pump may have the adjustable gain, the third charge pump may have a plurality of sampling capacitors, and the third charge pump may be configured to, at the selected An optional subset of the plurality of sampling capacitors is used to upsample the first charge pump output signal, and all of the plurality of sampling capacitors are connected in series at the output of the third charge pump during an output time interval.

The radio receiver may also include a second mixer coupled to the antenna and configured to output a second mixer output signal based on a signal received by the antenna. The first mixer output signal may be an in-phase component of a signal received by the antenna, and the second mixer output signal may be a quadrature-phase component of a signal received by the antenna. The radio receiver may further include a fourth charge pump coupled to the output of the second mixer and configured to generate a fourth charge based on the second mixer output signal Pump output signal.

According to another aspect of the disclosure, a method is provided in which a wireless signal is received in an antenna. A signal received by the antenna is mixed to produce a first mixer output signal in a first mixer coupled to the antenna. A signal based on the first mixer output signal is buffered in a buffer coupled to the output of the first mixer. The buffered signal is processed in a first charge pump coupled to the output of the buffer to generate a first charge pump output signal based on the buffered signal.

The method may further include processing the first mixer output signal in a second charge pump coupled to an output of the first mixer to generate a second charge based on the first mixer output signal Pump output signal. Buffering a signal based on the first mixer output signal may include buffering the second charge pump output signal, itself based on the first mixer output signal.

Processing the first mixer output signal may include processing the first mixer output signal in a second switched capacitor charge pump having a plurality of sampling capacitors, and processing the buffered signal may include processing the buffered signal in a second switched capacitor charge pump having a plurality of sampling capacitors. The buffered second charge pump output signal is processed in the first switched capacitor charge pump with sampling capacitors.

Processing the first mixer output signal in the second switched capacitor charge pump may include periodically sampling the The first mixer outputs signals, and periodically reconfigures the plurality of sampling capacitors in series at the output terminal of the second charge pump during an output time interval.

Mixing the signal received by the antenna may include generating a first mixer output signal from the signal received by the antenna, the first mixer output signal being a differential signal and the signal received by the antenna being a single-ended signal.

Buffering the second charge pump output signal in the buffer may also include processing the second charge pump output signal using a chopper stabilization circuit, the chopper stabilization circuit including the buffer.

Processing the mixer output signal in the second charge pump may further include adjusting the bandwidth of the second charge pump by adjusting a capacitance of a capacitance circuit of the second charge pump, the capacitance circuit having a and the adjustable capacitance is coupled between the plurality of sampling capacitors of the second charge pump and the output terminal of the second charge pump.

The method may further include processing the first charge pump output signal in a third charge pump coupled to an output of the first charge pump to generate a third charge pump output based on the first charge pump output signal Signal. Processing the first charge pump output signal in the third charge pump may include adjusting an adjustable gain of the third charge pump.

The third charge pump may have a plurality of sampling capacitors. Processing the first charge pump output signal in the third charge pump may include sampling the first charge pump on a selectable subset of the plurality of sampling capacitors selected according to the value of the adjustable gain outputting a signal, and connecting all of the plurality of sampling capacitors in series at an output terminal of the third charge pump during an output time interval.

The method may also include mixing a signal received by the antenna to produce a second mixer output signal in a second mixer coupled to the antenna. The first mixer output signal may be an in-phase component of a signal received by the antenna, and the second mixer output signal may be a quadrature-phase component of a signal received by the antenna. The method may also include processing a second mixer output signal in a fourth charge pump coupled to an output of the second mixer to generate a fourth charge pump output signal.

Additional advantages and novel features will be set forth in the following part of the description, which will become apparent to those skilled in the art on the basis of the following examples and drawings. , or can be obtained by generation or manipulation of examples. The advantages of the present teachings may be realized or obtained by the practice or use of various aspects of the method, instrumentalities, and combinations thereof set forth in the detailed examples discussed below.

Description of drawings

By way of example only, and not by way of limitation, the drawings depict one or more embodiments consistent with the present teachings. In the drawings, the same reference numerals refer to the same or similar elements.

FIG. 1A is a high-level circuit diagram of an example of a radio receiver architecture.

FIG. 1B is a detailed circuit diagram of an exemplary mixer architecture that may be used in a radio receiver as shown in FIG. 1A .

FIG. 2 is a detailed circuit diagram of an exemplary buffer that may be used in the radio receiver shown in FIG. 1A.

3A-3C are high level circuit diagrams of the improved radio receiver architecture.

4A-4E are detailed circuit diagrams of exemplary charge pumps that may be used in the radio receiver shown in FIGS. 3A-3C.

5A-5C are detailed circuit diagrams of another exemplary charge pump that may be used in the radio receiver shown in FIGS. 3A-3C.

Figures 6 and 8A-8H are plots showing experimental measurements obtained from the radio receiver shown in Figures 3A-3C.

7A-7C are detailed circuit diagrams of capacitor circuits used in the charge pumps shown in FIGS. 3A-3C, 4A-4E, and 5A-5C.

Detailed ways

In the following detailed description, numerous specific details are set forth by way of example in order to provide a thorough understanding of the related teachings. It should be apparent, however, to one skilled in the art that the present teachings may be practiced without these details. In other embodiments, well-known methods, procedures, components and/or circuits have been described at a relatively high level and without details in order to avoid unnecessarily obscuring aspects of the present teachings.

The radio receivers disclosed herein use unconventional architectures to provide high performance in small feature size (eg, 65nm or less) integrated circuit fabrication technologies. Specifically, transistors are both tiny and highly conductive in 65nm or smaller fabrication technologies. The combination of good electrical conductivity and low gate capacitance enables new approaches to signal processing of radio frequency (RF) signals. As an example, a 100 micron (um)/0.055 micron N-channel field effect transistor (FET) (NFET) driven as a switch with a gate-source voltage ( _VGS ) of 1.2 volts (V) exhibits approximately 5 ohms ( Ohms) drain-source on-resistance R _DS -on, and the total gate capacitance is only 75 femtofarads (fF). Degradation of the noise figure (NF) of a radio receiver is caused by excess thermal noise from energy dissipating elements of the front end, such as resistors. In this radio architecture, the extremely low on-resistance of the extremely narrow FETs reduces NF. As a result, switches can be moved closer to the front end, improving receiver performance.

In one example architecture shown in FIG. 1A , a radio receiver 100 has a signal path that begins with a passive matching network 101 connected directly to an antenna 102 . Inductor (L)-matching is exemplarily shown in this figure, but any other suitable matching network 101 may be used. Passive matching network 101 provides voltage gain, thereby increasing the required voltage at the input of low noise buffer (LNB) 103 . Low noise buffer 103 typically has a voltage gain of 1 and provides impedance buffering. As a result, the impedance at the output of the LNB103 is greatly reduced compared to conventional radio receiver circuits, where the LNB103 is replaced by a low-noise amplifier (LNA) that provides voltage gain from the input. At the input of the LNB, the input port noise (RMS) has been boosted by the voltage gain of the resonant tank (neglecting the noise from the matched inductor L). Thus the equivalent noise resistance at the input of the LNB increases by the square of the voltage gain. Thus, increasing the voltage of the desired signal through passive matching relaxes the requirements for equivalent noise resistance and associated power in the subsequent LNB 103 .

Referring again to FIG. 1A , LNB 103 has an output that is capacitively coupled to two single balanced passive mixers 110 , 112 via capacitor Cc 114 . Mixers 110, 112 are driven in quadrature by respective local oscillator signals LO _I and LO _Q. The differential output terminals of the passive mixers 110, 112 are coupled to ground via a capacitor Cmix. In order for the conversion to occur properly, each output of the passive mixers 110, 112 is provided with a different common-mode capacitor Cmix, since each single-balanced mixer converts the voltage with respect to ground to have a common-mode component differential signal. Differential capacitors (eg, coupled between the two differential outputs of the same passive mixer 110, 112) are also optionally included. For signals at local oscillator (LO) frequencies, the inputs to the mixers 110, 112 appear largely as open circuits (e.g., have very high impedance), and for frequencies far from the center frequency, due to mixing The output capacitance of the converter makes the impedance seen at the input terminal become lower. This frequency-translated capacitive effect provides first-order filtering of the down-converted RF signal at the output of the mixers 110, 112 such that the gain (different from that provided by the passive matching network 101) Far-out interference is attenuated immediately before being applied to the signal. The result is increased blocking performance and attenuated aliasing into the sampling bandwidth of the subsequent first gain stage.

An exemplary architecture for implementing the mixers 110, 112 is shown in FIG. 1B. As shown in FIG. 1B, each mixer 110 or 112 can be implemented using a pair of complementary FET devices 150, 152 having drain nodes connected together and to the input of the mixer. , and have source nodes respectively connected to the differential output nodes of the mixers. complementary local oscillator signals LO and The gate terminals of devices 150 and 152 are controlled respectively. Other mixer architectures may also be used.

Typically, power consumption may be traded off for dynamic range in the front end. Specifically, as exemplarily shown in the LNB103 circuit of FIG. pole followers, with sources pointing toward each other) can be stacked on top of each other to re-use current. This architecture halves the bias current required to drive the LNB 103 while maintaining a constant NF, and the output swing of each buffer in the architecture is reduced. In many applications, however, the reduced output swing does not matter because the input signal amplitude to the front end is small, even in the presence of the blocker.

Receiver 100 is ideal for direct conversion architectures because of their inherently low flicker noise and offset due to the use of passive, switched capacitor operation techniques. Furthermore, in addition to addressing the image rejection problem, the direct conversion architecture provides increased 3 decibel (dB) noise figure. This reduced noise bandwidth translates into additional performance that can be traded off between power and required sensitivity.

The low impedance output from LNB 103 is coupled to high conductivity passive mixer switches 150, 152 which provide high drive capability at the passive mixer output. As shown in FIG. 3A , a charge pump may be coupled to the outputs (eg, differential outputs) of the mixers 110 , 112 . By coupling a charge pump (such as 301) to the output of the mixer 110, the voltage at the mixer output can be passively increased by the operation of the charge pump 301, thereby eliminating the need to operate a low noise amplifier (LNA) at baseband frequency . In this way, the power, linearity and noise requirements imposed on such LNAs are eliminated. Alternatively, the passive amplification provided by the charge pumps (eg 301-305) does not add additional noise other than the thermal noise of the capacitors in the charge pump (eg kT/C noise). The charge pump also has the ability to linearly amplify the signal using rail-to-rail (or higher) output voltages, increasing the receiver's 100/300 dynamic range.

3A-3C, 4A-4E, and 5A-5C show the configuration of another circuit coupled to the output of the passive mixers 110,112. In particular, FIG. 3A shows a radio receiver 300 roughly similar to the radio receiver 100 shown in FIG. 1A , which also includes charge pumps (301- 305). In the radio receiver 300, the output terminals of each differential mixer 110, 112 are respectively directly coupled to a series combination of charge pumps (for example, three charge pumps in series combination are shown in FIG. 3A , however in other embodiments , different numbers of charge pumps can be used). Additionally, in some embodiments, a first buffer may be coupled between the output of mixer 110 and the input of charge pump 301, a second buffer may be coupled to the output of mixer 112, and another A charge pump can be coupled to the output of the second buffer. The first charge pump 301 may be a switched capacitor charge pump (SC-CP), which is directly coupled to the output of the differential mixer 110 or coupled to the output of the differential mixer 110 via a buffer. FIG. 4A shows a detailed circuit diagram of an SC-CP that can be used as charge pump 301 . SC-CP 310a in FIG. 4A is operable to differentially sample a mixer output capacitance (eg, capacitor _Cmix of FIG. 3A ) onto eight 5 picofarad (pF) sampling capacitors CS. Four of sampling capacitors _CS (eg, capacitors 401, 403, 405, and 407) are configured for positive sampling, and the other four sampling capacitors _CS (eg, capacitors 409, 411, 413, and 415) are configured for negative sampling. Thus, a total of 40 pF of sampling capacitors is presented to the capacitor Cmix at the output of the mixer. Sampling is controlled by signal _phiSample , which controls the gate terminals of sampling switches that connect each sampling capacitor CS 401-415 to the differential input nodes in _m and in _p of charge pump 310a. After sampling is complete, signal phiPresent causes capacitors 401-415 to be reconfigured in series as two banks of four capacitors: the first bank includes capacitors 401-407 coupled in series with each other, the second bank includes capacitors 401-407 coupled in series with each other 409-415. The central node common to both groups is connected to the common-mode level (vss in Figure 4A). The reconfiguration of the capacitors provides a voltage gain of 8 at the output. Eight capacitors 401-415 having an equivalent series capacitance of approximately 5pF/8=0.625pF are then provided to the filter capacitor _CFILT at the output of the charge pump 310a. Capacitor C _FILT consists of two capacitors connected in series with their center terminals (eg vss) connected to ground. This filter capacitor configuration provides reasonable common-mode impedance, as well as differential-mode filtering.

In the embodiment of FIG. 4A , the magnitude of the filter capacitor C _FILT is user selectable via signal BW_n. Specifically, the filter capacitor C _FILT is implemented as a capacitive circuit with an adjustable capacitance that can be adjusted to vary the analog bandwidth of the receiver (i.e. pre-analog-to-digital converter (ADC) conversion and sampling and aliasing through subsequent stages Before). For this receiver, two settings are provided: 1) a low bandwidth setting, which can be used to operate in an 802.15.4-standard compliant mode with a 3dB bandwidth of about 1.5 MHz, and 2) a high bandwidth setting, which A high bandwidth setting for a turbo mode data rate of approximately 2.8MHz for high speed operation. In the low bandwidth setting, signal BW_n selects to add additional capacitors 420, 422 in parallel with C _FILT to increase the total capacitance at the output node of the charge pump. In a high bandwidth setting, capacitors 420 and 422 are not connected to C _FILT by holding signal BW_n low.

As shown in FIG. 3B, a charge pump circuit (eg, 301) may include a charge pump circuit 310 in series with a subsequent chopper stabilization circuit 312, and a chopper stabilization circuit 312 with a filter capacitor C _FILT coupled to the charge pump Node between circuit 310 and chopper stabilization circuit 312 . In some embodiments, noise and bias reduction techniques are used instead of chopper stabilization techniques, such as by using an associated double sampling circuit (including a buffer) instead of chopper stabilization circuit 312 . The charge pump circuit 310a is an example of the charge pump circuit 310 shown in FIG. 3B. Additionally, chopper stabilization circuit 312 is shown diagrammatically in FIG. 3C , and specific circuit embodiments of chopper stabilization circuit 312 are shown in detail in FIGS. 4B-4D . As shown in FIG. 3C, chopper stabilization circuit 312 includes two buffers 321 and 322, each buffer coupled to a different one of the differential signal paths between the differential input and differential output of circuit 312. middle. Optionally, the chopper stabilization circuit may include a differential buffer comprising two buffer channels, each buffer channel coupled to a different in a differential signal path. Additionally, switches 324 and 325 are operable to selectively route the input signal to one of the buffers 321 , 322 . For example, in a first operating state, switches 324 and 325 may be operable to route signals received at node 326 to buffer 321 and output 328, and to route signals received at node 327 to buffer 322 and output 329 . In the second operating state, switches 324 and 325 are operated to route the signal received at node 326 to buffer 322 and output 328, and to route the signal received at node 327 to buffer 321 and output 329 . By alternating between the first operating state and the second operating state, chopper stabilization circuit 312 may minimize the effects of differences in buffers 321 and 322 at outputs 328 and 329 resulting in signal distortion.

4B-4D show detailed circuit diagrams of components of the chopper stabilization circuit. FIG. 4B shows an embodiment of a switch 324 that can be selectively coupled to different nodes i1 and i2 of the input nodes according to the state of the complementary control signals chop and chopN. FIG. 4C shows an embodiment of switch 325, which can be selectively coupled to different input nodes outp and node outm of input nodes o1 and o2 according to the state of complementary control signals chop and chopN. The A input node depends on the state of the complementary control signals Chop and Chop N. FIG. 4C also shows sampling capacitors 430 and 432, which are used to store charge from the output of the charge pump between different charge pump stages (eg, charge pump stages 301, 303, etc.). Finally, FIG. 4D shows an embodiment of buffers 321 and 322 coupled between outputs i1 and i2 of switch 324 and inputs o1 and o2 of switch 325, respectively.

5A-5C show detailed circuit schematic diagrams of a second exemplary SC-CP 310b. The charge pump 310b of FIGS. 5A-5C has variable gain and may be used in particular to implement a variable gain SC-CP as the last charge pump stage 305 of the radio receiver 300 . In other embodiments, the SC-CP 310b may be used to implement any other charge pump stage (eg 301 or 303 ), or any combination of charge pump stages of the radio receiver 300 .

Charge pump 310b generally has a structure similar to charge pump 310a of FIG. 4A. For example, charge pump 310b includes sampling capacitors 501-515 that operate substantially similarly to capacitors 401-415 of charge pump 310a. When the signal phiSample is high, the input signals inm and inp are sampled onto sampling capacitors 501-515, and when the signal phiPresent is high, the capacitors 501-515 are connected in series in two groups. Capacitors C _filt 520 and 522 shown in FIG. 5C operate substantially similarly to capacitors C _filt 420 and 422 of FIG. 4A .

Additionally, the charge pump 310b includes a gain selection circuit 519 operable to selectively adjust the gain of the charge pump 310b. Specifically, as described above in relation to FIG. 4A , charge pump 310a has a gain of eight (8) by sampling the input signal on eight capacitors 401-415 and coupling the series capacitors used for sampling to capacitor Obtained on C _filt . In charge pump 310b, gain selection circuit 519 selectively determines which of capacitors 501-515 receive samples of the input signal when signal phiSample is high. Thus, instead of sampling the input signal on all eight capacitors 501-515, the input signal may be sampled on only a subset of the eight capacitors. Specifically, when signal gain BO and signal gain B1 are high (and complementary signal gain BO_n and complementary signal gain B1_n are low), the input signal is sampled on all eight capacitors 501-515. However, if signal gain BO is low (and complementary signal gain BO_n is high), capacitors 503 and 511 do not receive input signal samples, but instead clear their charges when phiSample is asserted. Similarly, if signal gain B1 is low (and complementary signal gain B1_n is high), capacitors 505, 507, 513, and 515 do not receive input signal samples, but similarly remove their charges. The gain provided by charge pump 310b is therefore correspondingly reduced.

FIG. 4E shows a detailed circuit schematic of clock generator 330 that is operable to generate a clock signal for charge pump 310a of FIG. 4A.

Charge Pump Noise Considerations:

The larger the charge pump sampling capacitors (e.g., capacitors 401-415 and 501-515) are made (e.g., capacitors 401-415 and 501-515), the more power may be required from the radio receiver to drive (i.e., charge or discharge) these capacitors, and drive the switches for a fixed desired signal bandwidth. Therefore larger capacitors can be combined with larger switches to achieve the desired setting accuracy. The minimum sampling capacitance is set by thermal noise (eg, kT/C noise) on the differential output capacitor comprising C _FILT (eg, the sampling capacitor in FIG. 4A comprises two capacitors C _FILT in series with each other). Since thermal noise is usually white, it is evenly distributed throughout the sampling bandwidth. Therefore, the voltage noise from thermal noise at the output of the first charge pump 301 from thermal noise is equal to:

$\frac{{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{\mathrm{<span\; class="notranslate">\; Hz</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; kT</span>}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; FILT</span>}}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; \&times;</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; f</span>}}_{\mathrm{<span\; class="notranslate">\; sample</span>}}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; ,</span>$

Wherein, Fsample is the sampling rate of the first charge pump 301 . If we assume that the first stage charge pump 301 is sampled at the channel center frequency divided by 4, the sampling rate will be 2.45 gigahertz (GHz)/4 = 612.5 megahertz (MHz). Typically, the first stage sampling rate can be set by anti-aliasing requirements and filtering requirements. Then, we find that the noise density in a sampling bandwidth of 306.25MHz is:

$\frac{{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{\mathrm{<span\; class="notranslate">\; Hz</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; 4.111</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; twenty\; one</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; FILT</span>}}<span\; class="notranslate">\; \&times;</span>{\mathrm{<span\; class="notranslate">\; 612.5</span>}}^{\mathrm{<span\; class="notranslate">\; 6</span>}}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; 2.69</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 29</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; FILT</span>}}}<span\; class="notranslate">\; .</span>$

We may wish to ensure that the thermal noise (eg kT/C noise) in the first charge pump 301 is lower than the thermal noise from the front end by a suitable margin. To calculate the thermal noise density from the antenna at the output of the first charge pump 301, we assume a gain of about 10 dB in the front-end matching, and a charge pump gain of 8. So, the front-end noise of the 50 ohm resistor, or 0.9nV/rtHz, multiplied by a factor of about 24: the port noise at the output of the first charge pump is about 25nV/rtHz. For the above equation, this is the equivalent of a C _FILT of 51fF (ie, the noise from the front end is equal to the kT/C noise on the 51fF capacitor (cap)). To ensure that kT/C noise does not degrade NF by more than the arbitrary target of 0.2dB, we may need the capacitance of the output node to contribute 10% or less of the noise power at the output of the first charge pump. Therefore, C _FILT may need to be at least 20 times the size of the equivalent capacitance from the front end or at least 1.0pF. Note that the minimum capacitance of the second stage is approximately the square of the gain (eg 64×). Depending on the sampling rate of the second and subsequent stages (and thus the bandwidth of the kT/C noise distribution), other considerations, such as matching, wiring sensitivity, and other parasitic elements, can affect the selection of the minimum size of C _FILT .

Charge Pump Frequency Response:

As previously described, the charge pumps 301, 303, 305 provide filtering of out-of-band signals. The analysis of the charge pump can be approximated as follows. For an ideal, single-stage, switched-capacitor charge pump driven by an ideal voltage source with a gain of N, the bandwidth characteristic is set by the following discrete-time transfer function:

$\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; FILT</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; FILT</span>}}{\mathrm{<span\; class="notranslate">\; z</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; ,</span>$

where C is the series combination _of sampling capacitors (eg Cs/N, where N is the number of sampling capacitors in series during the current mode), and C _FILT is the total differential output capacitance, which includes the filter capacitance at the output of the charge pump.

The above equation relates the output voltage Vout to the input voltage Vin when the input of the switched capacitor charge pump (SC-CP) is driven by an ideal voltage source. However, the input of the charge pump is driven by a non-zero impedance (eg, the mixer output of the first stage 301, the buffer outputs of subsequent stages 303, 305 as described below). The SC-CP input impedance reflects the output capacitance of the charge pump as the square of the SC-CP voltage gain, and the SC-CP input impedance combines with the priority output impedance to produce a pole-zero combination that The frequency of the combination may be lower than the value shown in the above formula. Additionally, in some embodiments, the buffer shifts the output voltage from a ground offset to approximately 0.6V. Therefore, the switch at the input of the charge pump has only 0.6VV _GS drive. The increased impedance due to this common mode offset conversion can be considered as simply adding an additional series resistance to the output impedance of the buffer, thus reducing the bandwidth.

Since the input of the charge pump is driven by a non-ideal voltage source, the circuit can be modeled as a discrete-time charge pump to eliminate the frequency response as a discrete-time charge pump driven with a Thevenin equivalent source SC-CP input. This simplification assumes that the two poles are decoupled and independent. However, the ideal SC-CP gain drops at higher frequencies, resulting in less input-referred loading due to reduced high-frequency gain. This reduced load adds zeros in the transfer function from input to output. Figure 6 shows the simulated and calculated frequency responses for the ideal switched capacitor component, the finite output impedance component, and the combination of both. Even if the ideal SC-CP and output impedance sensing electrodes deviate from the approximation, the errors tend to cancel out so that the overall approximation is relatively good, as shown by the asterisk (simulated) and dotted (calculated) trace data.

Since the charge pump acts as a transformer, the capacitance in the charge pump is the square of the voltage gain of the charge pump multiplied by the output capacitance. Therefore, there is a limit to the amount of gain that can reasonably be obtained in a single stage, and is chosen here to be equal to 8. However, by buffering the filter capacitor output (e.g., with a source follower with a voltage gain less than 1, equal to 1, or greater than 1, a feedback op amp, a feedback transconductance amplifier, or any other suitable buffer), the SC-CP stage output impedance can be is lowered enough to adequately drive the additional stage of the charge pump. Additional charge pumps can be configured to provide additional gain and filtering to further condition the signal. Each gain stage approximates a second order filter (as described above), such that a cascade of three gain stages (eg, the three charge pump stages shown in Figure 3A) provides sixth order filtering. When combined with the inherent, first-order low-pass filtering of passive mixers, excellent rejection of out-of-band (OOB) blockers is obtained. Simulations show an OOB attenuation of about 100 dB away from the center of the channel at 100 MHz, although un-modeled parasitic coupling mechanisms can reduce the above numbers in practice. When the front-end mixer is running at the channel center frequency (eg, 2.5GHz), the subsequent gain stages can be run at a reduced rate to minimize power consumption driving the switches. For example, in a receiver, the first stage 301 after the mixer is selected to operate at the LO frequency divided by 8 (625 MHz), the second gain stage 303 and the third gain stage 305 at a rate of this value 1/4 of that or approximately 156.25 MHz (the exact frequency in this embodiment will depend on the channel since the LO frequency varies with the channel). Care should be taken to ensure that aliased components are either handled appropriately (eg by using decimation filters between stages where the downsampling operation takes place), or that they are below the level of concern.

To provide impedance buffering between charge pump gain stages in the radio receiver 300, each charge pump stage prior to the last charge pump state (e.g., each of the first two stages 301, 303 in the receiver 300) includes buffer to buffer the output voltage on C _FILT . For example, in the exemplary charge pump of FIG. 3B , chopper stabilization circuit 312 includes buffer 321 and buffer 322 that are operable to buffer the output voltage on C _FILT . In other embodiments, chopper stabilization circuit 312 may be replaced by a buffer stage without including chopper stabilization switches 324 and 325 .

In the detailed circuit embodiment shown in FIG. 4D, the buffers (eg, 321, 322) are implemented using a pseudo-differential buffer 450 to buffer the output voltage on C _FILT . In one embodiment, buffer 321 is made of complementary source follower transistors 452, 453 that buffer the signal at the output node of switch 324 and provide the buffered signal to the input node of switch 325 o1. In some embodiments, the buffer is driven by a step-down, capacitive DC-DC converter due to the small dynamic range required at the buffer input compared to the supply rails , and the use of a DC-DC converter improves the power metric (eg efficiency) of the buffer. Since each baseband path (eg I-path and Q-path) includes a differential buffer at the output of the first two stages (eg 301 and 303 ), in this embodiment the overall receiver includes four differential buffers.

As detailed above, to mitigate the effects of flicker noise and offset in the interstage buffer, a chopper stabilization circuit is used between the filter capacitor and the buffer input. The reduction of flicker noise is provided by the chopper stabilization circuits of Figures 3B and 3C. An exemplary embodiment of a chopper stabilization circuit is shown in detail in the circuit diagrams of FIGS. 4B and 4C , where switch 324 is implemented using switches T252, T253, T254, T255 and is used to unchop (unchop) after the buffer. ) signal switch 325 using switches T5, T8, T9, T10 and T201, T123, T124, T125 to achieve, the above-mentioned switches T5, T8, T9, T10 and T201, T123, T124, T125 form a transmission gate, the transmission gate can handle Good sampling of mid-rail common-mode voltage. In addition to chopping, or alternatively, instead of chopping, correlated double sampling can be used to handle offset and 1/f noise attenuation. Note that a small amount of residual charge is left on the follower gate capacitance when the chopping polarity is reversed. This charge is eliminated by the opposite polarity configuration. The process of charge removal/redistribution implements the switched capacitor resistor, resulting in the apparent resistance of the output node of the charge pump. While the capacitance at the buffer input and the chopper switch node can be made smaller, when it comes to the input, the equivalent resistance is amplified by the inverse of the square of the gain, essentially lowering the impedance. Increased loading on the output of the previous stage has the effect of reducing the gain from the priority follower, as well as reducing the intrinsic gain of the stage. To reduce charge cancellation at the buffer input, the switch and buffer can be optimized to trade off settling time drive capability with the resistive loss mechanism caused by chopping. Another way to reduce loss gain is to lower the chopping frequency, since charge is only lost at chopping polarity inversions: halving the chopping rate causes a doubling of the equivalent input impedance presented by the chopping buffer. The chopping can be reduced to a lower rate with the following considerations: a) the chopping frequency should be greater than the 1/f noise corner of the buffer, and b) sampling is done on the ADC following the analog front end before each conversion The + and - chopping signals are equal in magnitude, (otherwise the flicker noise + offset will not be filtered and will appear as a square wave in the digital domain after the ADC conversion).

When using two mixers 110 and 112 (eg, for quadrature outputs), the load on LNB 103 is further increased by first gain stage 301 as opposed to a single mixer. In some designs, separate LNBs for the I and Q channels may be used, or cascaded LNBs may be preferred (e.g., one LNB with its input coupled to an antenna with an output, the first LNB's output coupled to to the two LNB inputs, the outputs of these second and third LNBs are configured to drive the I-channel and Q-channel respectively) to reduce this loading effect.

Since the buffers 321, 322 are continuously biased in this exemplary embodiment, a storage capacitor _CR is included to collect charge from the buffers for the portion of the period during which the charge pump provides the sampled values to its filter capacitor. The charge collected on _CR is transferred to the subsequent charge pump in the next sampling interval. For example, a storage capacitor _CR is exemplarily shown in FIG. 4C showing an embodiment of switch 325 . Storage capacitor _CR may include common-mode capacitance (eg, 430), differential capacitance (432), or a combination thereof. In some embodiments, the buffers operate periodically such that they only run for a portion of the cycle, such as when a sampling operation is taking place.

In an integrated circuit embodiment of the SC-CP, the sampling capacitor may be implemented using a metal-insulator-metal capacitor (MIMCAP). MIMCAP advantageously provides low bottom plate capacitance (-0.5%). However, since the capacitance voltage division effect occurs when the sampling capacitors are arranged in series, the lower plate capacitance causes the gain attenuation of the SC-CP. Alternatively, metal-oxide-metal capacitors (MOMCAPs) may also be used instead of MIMCAPs. However, unless addressed, the much larger bottom plate parasitic capacitance of the MOMCAP to the substrate can cause gain reduction and increased NF.

To alleviate some of the problems arising from parasitic capacitance to the substrate, the bottom plate of the MOMCAP can be shielded, as shown in Figure 7A. Specifically, as shown in FIG. 7A , an integrated circuit capacitor 700 includes an upper plate 701 and a lower plate 702 that may exhibit parasitic connections to the substrate. To reduce the effect of parasitic connections to the substrate, a shield 703 may be formed between the lower plate 702 and the integrated circuit substrate. Shield 703 may be formed as doped wells or other regions, metallization, polysilicon, or using another suitable integrated circuit structure. Shield 703 is driven by unity gain buffer 704 connected to lower plate 702 such that shield 703 stores a voltage potential that follows the voltage of the lower plate. A unity gain buffer 704 is used to direct the parasitic capacitance to the point where the shield 703 tracks the lower plate voltage 702 . Figure 7A shows one embodiment of a capacitor 700 during the sampling phase. Figure 7B shows a number of capacitors 711, 713, 715 in the current stage. Buffer 704 has a gain of approximately 1 (eg, buffer 704 is implemented as a feedback source follower or a feedback operational amplifier). Figure 7C shows another embodiment of a capacitor bootstrap circuit. In another embodiment, the shield of each of capacitors 721-725 is coupled to the lower plate voltage during the sampling phase, eg, using a switch or a buffer coupled to the switch. After sampling, the sampling capacitors are arranged into a second series configuration 770 shown in FIG. 7C to provide gain. In configuration 770, the output of the series connected capacitors 721-725 of the charge pump is buffered by buffer 750, and the buffer output is ratio-metrically divided by a resistor divider similar to the series capacitors. In some embodiments, a switched capacitor equivalent to a resistor may be used. Resistor taps (such as at 753) are connected to the shield to provide bootstrapping. In some embodiments, node 753 includes a decoupling capacitor. The end result with a bootstrapped-MOMCAP scheme typically has increased power consumption and slightly worse noise performance; however, this is an acceptable trade-off for some price-sensitive or in applications or technologies that do not often provide MIMCAP .

Charge pump to the analog-to-digital converter (ADC) interface stage:

The final output of each path (ie I-path and Q-path) is a capacitor at the output of the last charge pump 305 . The aforementioned capacitors may realize filter capacitors and be connected to the ADC at the output of the radio receiver 300 . In some embodiments, the successive approximation register (SAR) based image anti-aliasing ADC (AA-ADC) described in U.S. Patent Application No. 13/717,377 filed 12/17/12 is used , which application is hereby incorporated by reference in its entirety. The AA-ADC samples at the sampling rate of the last gain stage (eg SC-CP305) of the first ADC array (156.25MHz). When the first array has sampled all of its sampling capacitors (for example, 8 samples, each sampled on 1/8 of the total array capacitance), the conversion process starts on the first array and the second array on the next SC- CP starts sampling on the current clock edge. Alternate sampling and conversion of two AA-ADC arrays provides the inherent decimation filter plus the decimator. For an 8x oversampling rate, the AA-ADC outputs digital decimated words at a rate of 156.25MHz/8=19.53MHz. In this way, out-of-band (OOB) signals are efficiently removed without aliasing, and the conversion rate is minimized to a value that is required to properly process the desired in-band signal as well as to deal with closed-channel rejection (eg, anti- adjacent/alternate channels), closed channel rejection requirements may require any suitable type of digital filter: including finite impulse response (FIR), infinite impulse response (IIR), or a matched filter for the received signal. Depending on specific signal processing requirements, a 2-tap sinc1 filter (with optional additional down-sample-by-two operation) can be placed at the AA-ADC digital output and used for the AA- Compensation for ADC array mismatch (e.g. gain mismatch, offset mismatch): In this case, each filtered (or filtered and decimated) AA-ADC sample is the average output of two arrays that are in Nulls are set in the frequency spectrum (ie 19.53/2 = 9.77MHz in this example) where the mismatch produces tint.

In addition to being used in the conversion process, the SAR-ADC array capacitance can also be used to implement the final stage filter capacitor. Alternatively, different capacitors than the SAR array capacitors may be used, or a combination of SAR-ADC capacitors and different filter capacitors may be used. Since the ADC input is directly coupled to the output of the final gain stage, no ADC input buffer is required in some embodiments. In this case, the last analog buffer in the signal chain is at the input of the last gain stage whose signal is 1/8 the magnitude of the signal at the ADC input. Therefore, the only components required to handle the full-scale range of the baseband signal are capacitors and switches, which readily provide the necessary linearity and dynamic range in a 65nm process. Note that having a lower gain for the final stage moderates the buffer drive requirements for driving the capacitors due to the quadratic relationship between the input reference capacitor and the charge pump gain. Thus, the gain can be partitioned between stages (or additional stages added or removed) to optimize for any particular design requirement.

In some embodiments, an additional amplifier may be coupled between the last SC-CP stage and the ADC input.

In one embodiment, the target ADC resolution is selected to be 12 bits. Extensive charge-pump filtering and the use of an anti-aliasing ADC that samples the terminal charge-pump means that the ADC only has to deal with the dynamic range of the desired signal and blocking interference (e.g., interference within the ADC sampling bandwidth (fs/2), at interference in the bandwidth 2x of the sampling rate of the ADC, because at the ADC sampling bandwidth, aliasing begins to fold the signal back onto itself, and does not reach the center of the channel until the sampling frequency); farther-away signals decays before the ADC conversion process begins. For 1.2V and 12-bit differential input supplies, converts to approximately 500 microvolts (uV) differential (2.4V input differential, V _PP /2 ¹² ) least significant bit (LSB). Because the quantization level is relatively large, the total capacitance of the ADC array is such that kT/C noise <<1LSB is easily achievable. By choosing 1pF x 2 (series combination) = 0.5pF, the differential sampling capacitor kT/C will be about 90uVRMS, which is a suitable value to meet a) thermal noise requirements, and b) prevent overloading of the final charge pump. To ensure that the thermal noise floor from the receiver is the limiting factor for sensitivity (for example, not the quantization noise floor of the ADC), there should be enough gain in the forward path of the receiver to ensure that front-end noise dominates at the ADC. In one embodiment, with three gain stages as described above, the thermal noise density at 1 MHz is approximately 500 nV/rtHz at the output of the receiver, with a combined noise power of approximately 800 uVRMS from 100 kilohertz (kHz) to 10 MHz . This is substantially higher than the quantization noise floor, which is ((500uV) ² /12) square root (sqrt), or about 150uVRMS; therefore, we should be limited by the radio's front-end thermal noise as expected.

In some embodiments, a high resolution ADC with low gain may be used between the passive mixer and the ADC. In this case, higher bit counts can be used to extend the dynamic range at the bottom end, absorbing the "gain" into the ADC; being able to resolve smaller signals allows the ADC to be set up closer to a passive mixer, or even Couple directly to the mixer output. A high dynamic range (for example, 18bits-20bits) anti-aliasing ADC directly connected to the output of the mixer will have significant advantages in terms of linearity and dynamic range. The excellent capacitive drive capability of the LNB/passive mixer architecture makes this type of receiver efficient and architecturally suitable for current and future deep sub-micron processes.

In some embodiments, another type of ADC is used (eg, delta-sigma, flash, pipeline, integrated, etc.).

Automatic Gain (AGC) Control:

Gain adjustment in the forward path (e.g., automatic gain control or AGC) may be required because the radio's input dynamic range should extend from thermal noise (approximately -110dBm at 1MHz bandwidth (BW)) to 0dBm and the ADC is only 12 bits (~70dB). Therefore, an additional dynamic range of at least 4OdB may be required. can be achieved without detrimentally affecting the ideal filtering characteristics of the signal path by sampling the input to the gain stage on only a subset of the sampling capacitors during the "sampling" phase of operation, and then connecting all eight in series during the "current" phase of operation capacitor for gain adjustment. For example, if all eight capacitors were sampled in parallel and then set up in series, the gain of the SC-CP would be 8. However, if only four capacitors sample the input signal and the other four capacitors remove their charge (for example, the other capacitors are shorted during the sampling phase), then in the "current" phase of operation, when all eight capacitors are set in series, the SC-CP The gain has been reduced to 4. Since all eight capacitors are still connected in series during the "current" phase of operation, the bandwidth of the SC-CP will remain constant even when the gain is varied. As detailed above, FIG. 5A shows an embodiment of a variable gain SC-CP in which signal gain B0 and signal gain B1 provide two-bit control over the variable gain of the charge pump. Note, however, that in configurations where only four capacitors are used in the sampling stage, the input impedance of the gain stage increases since only four capacitors are presented to the priority buffer instead of all eight capacitors (compared to when the gain is set to 8 multiples compared to). A variable load at the output of the priority buffer can lead to a functional dependence of the bandwidth at the AGC level. To reduce this load variation, the short capacitor used for sampling in the gain stage can be replaced with a dummy capacitor to keep the load presented to the priority constant regardless of how many capacitors are sampled in the gain stage. During the sampling phase, dummy capacitors are presented to the follower output (eg, in parallel with the four selected charge pump capacitors). However, at the current stage, the dummy capacitor is then shorted to ground. Alternatively, the drive strength of the buffer may be adjusted (eg, reduced in response to low gain) to maintain a more constant bandwidth.

Each gain stage can have logic to select from one to eight sampling capacitors, thus allowing each gain stage to be arbitrarily set to any integer multiple of capacitors. By sequentially cascading the three stages 301-305, the dynamic range can be controlled from a gain of 1 to a gain of 8x8x8=512 by choosing the number of capacitors to be sampled in each stage; this adds about 54dB dynamic range. Furthermore, charge pump gain stability via process, voltage, temperature and mismatch effects should be exceptional since the gain is set by the capacitance ratio. Variations in the front-end matching network (eg, center frequency, insertion loss, etc.) and LNB performance characteristics will add additional variation to the overall signal chain.

The mixers (110, 112) and first two gain stages (301, 303) may be configured to be grounded together with their common mode voltage settings. By choosing a common-mode ground, low on-resistance may require only single-flavored switches (eg, only NMOS, only PMOS, only E-mode transistors (pHEMT), etc.). The use of single-way switches reduces the power required to drive the switches. The common mode of ground also has the advantage that the reference voltage (ground) is stable and inherent. The main concern with common mode around ground is that a large input signal can cause the diode node in the switch to be forward biased (due to the tiny switch size, there is less concern about node non-linearity as the capacitance of the node/switch is larger than in some embodiments Much smaller capacitance is expected for the charge pump in ). The full-scale swing of the ADC is between 0 and 1.2v, with 1.2V appearing only at the output of the last gain stage. Therefore, the final stage can be operated at a common-mode voltage of 0.6V to maximize swing; therefore, V _GS across the switches is nominally 0.6V. This small gate drive essentially causes high impedance switching, especially at low temperatures. This effect can be mitigated by choosing a low-V _T switch or a charge-boost clock signal. The input of the final stage (e.g., the last buffer of the charge-pump chain) has a maximum swing of approximately 1/8 of the full-scale output, or 150mV _0-p , when the body-junction diode is forward-biased. 150mV _0-p is well below level. To avoid forward biasing nodes under high input conditions, first the AGC algorithm reduces the front-end gain, then moves backwards, only after the two earlier stages have reduced their gains to 1 or less, the gain of the final stage decline.

For alternative front-end receivers:

Although the above discussion has focused on an exemplary radio receiver including the LNB 103 of the front end, a wireless receiver need not include the LNB of the front end. More generally, in some embodiments, a radio receiver may more generally include an antenna, a buffer, and a passive mixer, as described herein. The radio receiver may also include one or more of the following:

A low noise amplifier (LNA) at the front end, such as a low noise amplifier coupled between the antenna 102 and the mixers 110, 112;

Connecting transconductors as part of a passive mixer architecture;

a purely passive architecture; and/or

• Any other suitable frequency conversion element.

In these cases, the output of the mixer can be directly coupled to the input of the first SC-CP, or it can be buffered by an amplifier with a gain less than 1, equal to 1, or greater than 1, depending on the design requirements of the receiver and mixer output impedance, the output capacitance of the buffer is lower than the input capacitance of the buffer.

Furthermore, the rules and circuits described above can also be used in the following architectures: using active mixers, diode mixers, passive mixers, single balanced mixers, double balanced mixers, unbalanced mixers mixer or any other suitable mixer or front-end architecture or frequency conversion of the input signal.

Example simulation results:

Simulations were performed for the radio receivers described above in relation to Figures 3A-3C, 4A-4E and 5A-5C, and the results of the simulations are presented here.

8A and 8B illustrate the clock signals generated by the clock generator module 330 .

Figure 8C shows the periodic alternating current (AC) response (PAC) at various points along the receiver chain from the antenna input to the I-channel output (final stage output). Figure 8D shows the PAC response of the receiver at a wider bandwidth at the aliasing frequency with a scan frequency selected for improved resolution.

Figure 8E shows a double sideband (DSB) NF at the I channel output at a point at the end of the signal chain at which point the ADC will sample the receiver output.

FIG. 8F is a table of top noise contributors to noise factor and shows various noise contributors to NF at 1 MHz.

Figure 8G shows the 1 dB compression point of the blocker at a 100 MHz offset from the center of the channel.

Figure 8H shows the fractional current consumed by the LNB (3.53 milliamps (mA)), the fractional current consumed by the clock generator and quadrature mixer driver (3.12 mA), and the fractional current consumed by a single differential buffer The fractional current (171uA). The entire receiver consumes 7.35mA1.2V from the antenna input to the quadrature output presented to the ADC for conversion, equivalent to 8.8mW.

Unless otherwise stated, all measurements, values, classes, positions, magnitudes, dimensions, and other specifications set forth in this specification, including those in the claims that follow, are approximate and not exact. Their purpose is to have a reasonable range consistent with the function which is relevant to them and which is customary in the field to which they belong.

The scope of protection of the present invention is limited only by the following claims. This scope is intended and should be interpreted as broadly as possible consistent with the ordinary meaning of interpreted language in the claims including all structural and functional equivalents in accordance with this specification and archival file. Nonetheless, none of the claims are intended to cover subject matter that fails to satisfy the requirements of sections 101, 102, or 103 of the Patent Act, nor should they be construed in such a manner. Any unintentional coverage of these topics is clarified here.

Except as stated above, nothing that has been stated or illustrated is intended or should be construed as creating a contribution to any component step, feature, object, interest, advantage, or equivalent to the public, whether it is in the claims or not narrative.

It should be understood that the terms and expressions used herein have their ordinary meanings, as are the meanings accorded to the respective fields of study and study concerned, unless specifically stated otherwise herein. Relative terms such as first and second, and similar terms, may be used only to distinguish one entity or function from another, without necessarily requiring or implying any such actual relationship or order between these entities or functions. The terms "comprising", "comprising", or any other variation thereof are intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus of a list of included elements does not include only those elements, but may include such processes, methods, An element not expressly listed or inherent in an article or device. An element proceeded by "a" or "an" shall, without further limitation, not exclude other additional the presence of the same elements.

The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in reducing all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.

While the foregoing has described what is considered to be the best mode implementation and/or other examples, it should be understood that various changes could be made therein and that the subject matter disclosed herein may be embodied in various forms and examples and that the teachings may be applied to Of many applications, only some of these many are described herein. The following claims are intended to claim any and all applications, modifications and variations that fall within the true scope of the teachings.

Claims (20)

1. A radio receiver, characterized in that it comprises: an antenna configured to receive a signal; a first mixer coupled to the antenna and configured to output a first mixer output signal based on a signal received by the antenna; a buffer having a buffer input coupled to the output of the first mixer and configured to output a buffered output at the buffer output based on the first mixer output signal signal; and A first charge pump coupled to the buffer output and configured to generate a first charge pump output signal based on the buffer signal. 2. The radio receiver of claim 1, further comprising: a second charge pump coupled to the output of the first mixer and configured to generate a second charge pump output signal based on the first mixer output signal, Wherein, the buffer input terminal is coupled to the output terminal of the second charge pump, and the buffer is configured to output the buffer signal at the buffer output terminal based on the second charge pump output signal , the second charge pump output signal itself is based on the first mixer output signal. 3. The radio receiver of claim 2, wherein the first and second charge pumps are switched capacitor charge pumps, each of the switched capacitor charge pumps comprising a plurality of sampling capacitors. 4. The radio receiver of claim 3, wherein the second charge pump is configured such that, during a sampling interval, each of the plurality of sampling capacitors of the second charge pump The output signal of the first mixer is periodically sampled, and the plurality of sampling capacitors are periodically re-configured in series at the output end of the second charge pump within an output time interval. 5. The radio receiver of claim 2 , wherein the first mixer, the first charge pump, and the second charge pump each receive a differential signal at their inputs and operate at Their outputs output differential signals. 6. The radio receiver of claim 5, further comprising: a chopper stabilization circuit coupled between the output of the second charge pump and the input of the first charge pump, the chopper stabilization circuit comprising the buffer . 7. The radio receiver according to claim 1, wherein the first charge pump further comprises a capacitance circuit, the capacitance circuit has an adjustable capacitance, and the adjustable capacitance is coupled to the first charge pump Between the plurality of sampling capacitors and the output terminal of the first charge pump, wherein the adjustable capacitor is configured to be adjusted to adjust the bandwidth of the first charge pump. 8. The radio receiver of claim 2, further comprising: a third charge pump coupled to the output of the first charge pump and configured to generate a third charge pump output signal based on the first charge pump output signal, Wherein at least one of the first charge pump, the second charge pump and the third charge pump has an adjustable gain. 9. The radio receiver of claim 8, wherein said third charge pump has said adjustable gain, the third charge pump has a plurality of sampling capacitors, and The third charge pump is configured to sample the first charge pump output signal on a selectable subset of the plurality of sampling capacitors selected according to the value of the adjustable gain, and during an output time interval at the The output terminal of the third charge pump is connected in series with all the plurality of sampling capacitors. 10. The radio receiver of claim 1, further comprising: a second mixer coupled to the antenna and configured to output a second mixer output signal based on a signal received by the antenna, Wherein, the first mixer output signal is the in-phase component of the signal received by the antenna, and the second mixer output signal is the quadrature phase component of the signal received by the antenna; and A fourth charge pump coupled to the output of the second mixer and configured to generate a fourth charge pump output signal based on the second mixer output signal. 11. A method, comprising: Receive wireless signals in the antenna; mixing a signal received by the antenna to produce a first mixer output signal in a first mixer coupled to the antenna; buffering a signal based on the first mixer output signal in a buffer coupled to the output of the first mixer; and The buffered signal is processed in a first charge pump coupled to an output of the buffer to generate a first charge pump output signal based on the buffered signal. 12. The method of claim 11, further comprising: processing the first mixer output signal in a second charge pump coupled to an output of the first mixer to generate a second charge pump output signal based on the first mixer output signal, Wherein, buffering the signal based on the first mixer output signal comprises: buffering the second charge pump output signal, the second charge pump output signal itself being based on the first mixer output signal. 13. The method of claim 12, wherein processing the first mixer output signal comprises processing the first mixer output signal in a second switched capacitor charge pump comprising a plurality of sampling capacitors signal, and Processing the buffered signal includes processing the buffered second charge pump output signal in a first switched capacitor charge pump including a plurality of sampling capacitors. 14. The method of claim 13, wherein processing the first mixer output signal in the second switched capacitor charge pump comprises: periodically sampling the first mixer output signal on each of the plurality of sampling capacitors of the second charge pump during a sampling interval, and During the output time interval, the plurality of sampling capacitors are periodically reconfigured in series at the output terminal of the second charge pump. 15. The method of claim 12, wherein mixing the signal received by the antenna comprises generating a first mixer output signal from the signal received by the antenna, the first mixer output signal being A differential signal, the signal received by the antenna is a single-ended signal. 16. The method of claim 15, wherein buffering the second charge pump output signal in the buffer further comprises: processing the second charge pump output signal using a chopper stabilization circuit, the The chopper stabilization circuit includes the buffer. 17. The method according to claim 12, wherein processing the mixer output signal in the second charge pump further comprises: adjusting the capacitance of the capacitor circuit of the second charge pump to adjust the The bandwidth of the second charge pump, the capacitance circuit has an adjustable capacitance, and the adjustable capacitance is coupled between a plurality of sampling capacitors of the second charge pump and an output terminal of the second charge pump. 18. The method of claim 12, further comprising: processing the first charge pump output signal in a third charge pump coupled to an output of the first charge pump to generate a third charge pump output signal based on the first charge pump output signal, Wherein, processing the output signal of the first charge pump in the third charge pump includes adjusting an adjustable gain of the third charge pump. 19. The method of claim 18, wherein the third charge pump has a plurality of sampling capacitors; and Wherein, processing the output signal of the first charge pump in the third charge pump includes: sampling the first charge pump output signal on a selectable subset of the plurality of sampling capacitors selected according to the value of the adjustable gain, and All of the plurality of sampling capacitors are connected in series at an output terminal of the third charge pump during an output time interval. 20. The method of claim 11, further comprising: mixing a signal received by the antenna to produce a second mixer output signal in a second mixer coupled to the antenna, Wherein, the first mixer output signal is the in-phase component of the signal received by the antenna, and the second mixer output signal is the quadrature phase component of the signal received by the antenna; and The second mixer output signal is processed in a fourth charge pump coupled to the output of the second mixer to generate a fourth charge pump output signal.