CN105098067B - Semiconductor structure, resistive memory cell structure and manufacturing method of semiconductor structure - Google Patents

Abstract

The present invention discloses a semiconductor structure, a resistive memory cell structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes an insulating structure, a stop layer, a metal oxide layer, a resistance structure and an electrode material layer. The insulating structure has a via, and the stop layer is formed in the via. The metal oxide layer is formed on the stop layer. The resistance structure is formed at a bottom of an outer wall of the metal oxide layer. The electrode material layer is formed on the metal oxide layer.

Description

Semiconductor structure, resistive memory cell structure and method for manufacturing the semiconductor structure

technical field

The present invention relates to a semiconductor structure, a resistive memory unit structure and a manufacturing method of the semiconductor structure, and in particular to a semiconductor structure with good characteristics, a resistive memory unit structure and a manufacturing method of the semiconductor structure.

Background technique

With the development of semiconductor technology, various semiconductor components are constantly being introduced. For example, components such as memories, transistors, and diodes have been widely used in various electronic devices.

In the development of memory technology, researchers continue to carry out various types of R&D and improvement, among which resistive memory is one type. Therefore, researchers are devoting themselves to studying how to control the resistance value of the resistive memory to achieve good characteristics.

Contents of the invention

The invention relates to a semiconductor structure, a resistive memory unit structure and a manufacturing method of the semiconductor structure. In an embodiment, the blocking layer of the semiconductor structure can block excessive oxidation of the oxidation process, thereby enabling the semiconductor structure to have better characteristics.

According to an embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure includes an insulating structure, a stop layer, a metal oxide layer, a resistance structure and an electrode material layer. The insulating structure has a via, and the blocking layer is formed in the via. A metal oxide layer is formed on the barrier layer. The resistance structure is formed on a bottom of an outer wall of the metal oxide layer. The electrode material layer is formed on the metal oxide layer.

According to another embodiment of the present invention, a resistive memory cell structure is proposed. The resistive memory cell structure includes an insulating structure, a barrier layer, a memory element, a resistive structure, and a top electrode layer. The insulating structure has a through hole, and the barrier layer is formed in the through hole. The memory element is formed on the blocking layer. The resistance structure is formed on a bottom of an outer wall of the memory element. A top electrode layer is formed on the memory element.

According to yet another embodiment of the present invention, a method for manufacturing a semiconductor structure is provided. The manufacturing method of the semiconductor structure includes the following steps: forming an insulating structure with a through hole (via); forming a barrier layer in the through hole and on a side wall of the through hole; forming a metal layer on the barrier layer; removing a part of the barrier layer on the inner wall of the through hole; performing an oxidation process to oxidize the metal layer to form a metal oxide layer on the barrier layer and form a resistance structure on the metal oxide layer a bottom of an outer wall; and forming an electrode material layer on the metal oxide layer.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the preferred embodiments are specifically cited below, together with the attached drawings, and are described in detail as follows:

Description of drawings

FIG. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view of a semiconductor structure according to yet another embodiment of the present invention.

4A-4D are flowcharts of a method for manufacturing a semiconductor structure according to an embodiment of the present invention.

5A-5F are flow charts illustrating a method for manufacturing a semiconductor structure according to another embodiment of the present invention.

6A-6G are flow charts illustrating a method for manufacturing a semiconductor structure according to another embodiment of the present invention.

FIG. 7 shows resistance-voltage curves of semiconductor structures according to an embodiment of the present invention and a comparative example.

【Symbol Description】

100, 200, 300: Semiconductor Structures

110, 210: insulation structure

110a, 130a, 130a', 140a, 150a-1, 150b-1, 210a, 340a, 440a: top surface

110r: upper part

110s: side wall

110v, 210v: through hole

120, 220: conductive structure

220a: layer of conductive material

130, 130': barrier layer

140: metal oxide layer

140s: outer wall

150: Resistance structure

150a: Metal oxide structure

150b: void

160: electrode material layer

210s: inner wall

211: gap wall

213: interlayer dielectric layer

213r: perforated

340, 340’, 440: metal layer

413: interlayer dielectric material layer

D1: Depth

H1: Height

I, II: curve

T1, T2: Thickness

W1, W2: Width

detailed description

In the embodiment of the invention, a semiconductor structure, a resistive memory cell structure and a method for manufacturing the semiconductor structure are provided. In an embodiment, the blocking layer of the semiconductor structure can block excessive oxidation of the oxidation process, thereby enabling the semiconductor structure to have better characteristics. However, the embodiments are only used for illustration and shall not limit the scope of protection of the present invention. In addition, the drawings in the embodiments omit some important components to clearly show the technical characteristics of the present invention.

FIG. 1 is a schematic cross-sectional view of a semiconductor structure 100 according to an embodiment of the present invention. The semiconductor structure 100 includes an insulating structure 110 , a stop layer 130 , a metal oxide layer 140 , a resistance structure 150 and an electrode material layer 160 . The insulating structure 110 has a via 110v, and the barrier layer 130 is formed in the via 110v. A metal oxide layer 140 is formed on the barrier layer 130 . The resistance structure 150 is formed on the bottom of the outer wall 140 s of the metal oxide layer 140 , and the electrode material layer 160 is formed on the metal oxide layer 140 .

In an embodiment, the material of the insulating structure 110 may include an insulating material, such as silicon nitride (SiN) and/or silicon oxide. However, the material of the aforementioned insulating structure 110 can be properly selected according to practical applications, and is not limited to the aforementioned examples.

In an embodiment, the barrier layer 130 has high conductivity and is difficult to be oxidized, and can be used to prevent excessive oxidation of the oxidation process used to form the metal oxide layer 140, for example, to prevent the oxidation process from oxidizing other elements of the semiconductor structure 100, Furthermore, the semiconductor structure 100 can have better characteristics.

In an embodiment, the barrier layer 130 may include at least one of metal nitride or inert metal. For example, the material of the barrier layer 130 may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), gold (Au) and platinum (Pt). However, the selection of the aforementioned materials can be properly selected according to practical applications, and is not limited to the aforementioned examples.

In an embodiment, the thickness T1 of the barrier layer 130 is, for example, about The thickness T2 of the metal oxide layer 140 is, for example, about

In an embodiment, the material of the metal oxide layer 140 may include at least one of tungsten oxide (WO _x ), titanium nitride (TiN), tantalum nitride (TaN) and hafnium oxide (HfO 2 ).

In an embodiment, the semiconductor structure 100 may further include a conductive structure 120 . As shown in FIG. 1 , the conductive structure 120 is formed between the barrier layer 130 and the metal oxide layer 140 . The material of the conductive structure 120 may include a conductive material, such as tungsten metal (W). However, the material of the aforementioned conductive structure 120 can be properly selected according to practical applications, and is not limited to the aforementioned examples.

According to an embodiment of the present invention, as shown in FIG. 1 , the resistive structure 150 is formed at the bottom of the outer wall 140s of the metal oxide layer 140 , in other words, the top surface of the resistive structure 150 is lower than the top surface 140a of the metal oxide layer 140 . Furthermore, the resistance structure 150 with a high resistance value can be formed between the outer wall 140s of the metal oxide layer 140 and the side wall 110s of the through hole 110v. In this way, the electrode material layer 160 and other resistance structures located The conductive elements under 150 have better insulation, further preventing short circuit between the electrode material layer 160 and other conductive elements. For example, the resistance structure 150 with a high resistance value can provide better insulation between the conductive structure 120 and the electrode material layer 160 , further preventing short circuit between the conductive structure 120 and the electrode material layer 160 .

As shown in FIG. 1 , the resistance structure 150 may include at least one of a metal oxide structure 150a or a void 150b. In other words, the resistance structure 150 may include the metal oxide structure 150a, or the void 150b, or both the metal oxide structure 150a and the void 150b. In an embodiment, the top surface 150 a - 1 of the metal oxide structure 150 a and the top surface 150 b - 1 of the void 150 b are lower than the top surface 140 a of the metal oxide layer 140 .

In an embodiment, the metal oxide structure 150a may be any metal oxide with high resistance, such as titanium oxynitride (TiON); the gap 150b is, for example, an air gap, which also has high resistance. However, the type of the aforementioned resistive structure 150 can be properly selected according to practical applications, and is not limited to the aforementioned examples.

In an embodiment, the material of the electrode material layer 160 includes a conductive material, such as at least one of tungsten (W), platinum (Pt), tantalum nitride (TaN) and nickel (Ni). However, the material of the aforementioned electrode material layer 160 can be appropriately selected according to actual applications, as long as it can be applied to electrodes, and is not limited to the aforementioned examples.

FIG. 2 is a schematic cross-sectional view of a semiconductor structure 200 according to another embodiment of the present invention. The elements in this embodiment that are the same as those in the previous embodiments use the same element numbers, and for related descriptions of the same elements, please refer to the above, and details will not be repeated here.

As shown in FIG. 2 , the semiconductor structure 200 includes an insulating structure 110 , a conductive structure 220 , a barrier layer 130 , a metal oxide layer 140 , a resistive structure 150 and an electrode material layer 160 . The insulating structure 110 has a through hole 110v, and the conductive structure 220 is formed in the through hole 110v. The barrier layer 130 is formed on the conductive structure 220 , and the metal oxide layer 140 is formed on the barrier layer 130 . The resistance structure 150 is formed on the bottom of the outer wall 140 s of the metal oxide layer 140 , and the electrode material layer 160 is formed on the metal oxide layer 140 .

In an embodiment, the material of the conductive structure 220 may include a conductive material, such as tungsten metal (W). However, the material of the aforementioned conductive structure 220 can be appropriately selected according to practical applications, and is not limited to the aforementioned examples.

In an embodiment, the barrier layer 130 has high conductivity and is difficult to be oxidized, and can be used to block excessive oxidation of the oxidation process used to form the metal oxide layer 140, for example, to prevent the oxidation process of the conductive structure 220 from oxidation, and can be used in The thickness of the metal oxide layer 140 is preferably controlled during the process, so that the thickness of the metal oxide layer 140 has better uniformity, and thus the semiconductor structure 100 can have better characteristics. Moreover, the barrier layer 130 can also increase the adhesion between the metal oxide layer 140 and the conductive structure 220 .

In one embodiment, the barrier layer 130 is made of titanium nitride, which can increase the adhesion between the conductive structure 220 made of tungsten and the metal oxide layer 140 made of tungsten oxide.

According to an embodiment of the present invention, as shown in FIG. 2 , the resistive structure 150 is formed at the bottom of the outer wall 140s of the metal oxide layer 140 . Furthermore, the resistance structure 150 with a high resistance value can be formed between the outer wall 140s of the metal oxide layer 140 and the sidewall 110s of the through hole 110v, so that the conductive structure 220 and the electrode material layer 160 can be formed There is better insulation between them, further preventing short circuit between the conductive structure 220 and the electrode material layer 160 .

In an embodiment, the semiconductor structure 200 may further include a liner layer (not shown in the drawing), and the liner layer is formed between the conductive structure 220 and the insulating structure 110 . In an embodiment, the material of the liner layer may include titanium nitride.

FIG. 3 is a schematic cross-sectional view of a semiconductor structure 300 according to yet another embodiment of the present invention. The components in this embodiment that are the same as those in the preceding embodiments use the same component numbers, and for related descriptions of the same components, please refer to the above, and details will not be repeated here.

As shown in FIG. 3 , the semiconductor structure 300 includes an insulating structure 210 , a conductive structure 220 , a barrier layer 130 , a metal oxide layer 140 , a resistive structure 150 and an electrode material layer 160 . The insulating structure 210 has a via 210v, and the conductive structure 220 is formed in the via 210v. The barrier layer 130 is formed on the conductive structure 220 , and the metal oxide layer 140 is formed on the barrier layer 130 . The resistance structure 150 is formed on the bottom of the outer wall 140 s of the metal oxide layer 140 , and the electrode material layer 160 is formed on the metal oxide layer 140 . As shown in FIG. 3 , the resistance structure 150 may include at least one of a metal oxide structure 150 a or a void 150 b.

In an embodiment, as shown in FIG. 3 , the insulating structure 210 may include a spacer 211 and an interlayer dielectric layer 213 . The spacer 211 surrounds the conductive structure 220 , the interlayer dielectric layer 213 is formed on the spacer 211 , and the spacer 211 and the interlayer dielectric 213 together form a via hole 210v.

The through hole 210 v has a first width W1 corresponding to the spacer 211 , and the through hole 210 v has a second width W2 corresponding to the interlayer dielectric layer 213 , and the first width W1 and the second width W2 may be the same or different. In one embodiment, as shown in FIG. 2 , the first width W1 is greater than the second width W2 . In other embodiments, the first width W1 may also be equal to or smaller than the second width W2.

In an embodiment, the semiconductor structure 300 may further include a liner layer (not shown in the drawing), and the liner layer is formed between the conductive structure 220 and the insulating structure 210 , such as between the conductive structure 220 and the spacer 211 . In an embodiment, the material of the liner layer may include titanium nitride.

According to an embodiment of the present invention, the semiconductor structure 100/200/300 is, for example, a contact-type resistive random access memory unit structure, and the conductive structure 120/220 is, for example, a contact structure. The metal oxide layer 140 is, for example, a memory element, and the electrode material layer 160 is, for example, a top electrode layer. For example, the contact structure, the storage element and the top electrode layer can constitute a metal/insulator/metal multilayer memory cell structure, and its resistance value can be changed by applying a bias voltage, so that the memory element can have high resistance and low resistance The two states are used to express the "0" and "1" of the digital signal, and perform the functions of writing and erasing the memory cell structure. In detail, when an external bias voltage is applied, a filamentary conduction path is formed in the insulating layer of the metal/insulating layer/metal multilayer memory cell structure, so that the memory element turns into a low-resistance state. When the current passes, the filamentary conduction path is broken, which makes the storage element change to a high resistance state.

When the thickness of the metal oxide layer 140 has good uniformity, in other words, the thickness of the insulating layer of the memory element has high uniformity, the resistance value of the memory element can be better controlled, and then the contact resistive memory cell structure Has better characteristics.

Please refer to FIG. 4A to FIG. 4D , which illustrate a flow chart of a manufacturing method of the semiconductor structure 100 according to an embodiment of the present invention.

As shown in FIG. 4A , an insulating structure 110 having a via hole 110v is formed, a barrier layer 130 is formed in the via hole 110v , and a metal layer 440 is formed on the barrier layer 130 . In an embodiment, the barrier layer 130 is formed on the sidewall 110s of the via hole 110V. In an embodiment, the barrier layer 130 and the metal layer 440 are formed in and fill up the via hole 110v, for example.

In an embodiment, a planarization process may be further performed on the barrier layer 130 and the metal layer 440 to planarize the surfaces of the barrier layer 130 and the metal layer 440 . In an embodiment, the planarization process is, for example, a chemical mechanical polishing process (CMP process). After planarization, as shown in FIG. 4A , the top surface 130a of the barrier layer 130 and the top surface 440a of the metal layer 440 are flush and equiplanar. After planarization, the top surface 130a of the barrier layer 130 and the top surface 440a of the metal layer 440 may be flush and equiplanar or non-equalplanar with the top surface 110a of the insulating structure 110 . In an embodiment, as shown in FIG. 4A , the top surface 130a and the top surface 440a are not equiplanar to the top surface 110a of the insulating structure 110 .

As shown in FIG. 4B , a portion of the barrier layer 130 on the inner wall 110 s of the via hole 110 v is removed. After this step, the top surface 130a' of the barrier layer 130 and the top surface 440a of the metal layer 440 are not equiplanar. In an embodiment, for example, the part of the barrier layer 130 located on the inner wall of the through hole 110v 110s is removed through an etching process, and etching is performed using an etchant having a high selectivity to the barrier layer 130 and the metal layer 440, Only part of the barrier layer 130 is etched away, and the structure of the metal layer 440 is not substantially damaged by the etching.

As shown in FIG. 4C , an oxidation process is performed to oxidize the metal layer 440 to form the metal oxide layer 140 on the barrier layer 130 and the resistive structure 150 at the bottom of the outer wall 140 s of the metal oxide layer 140 . In an embodiment, a part of the metal layer 440 is oxidized to form the metal oxide layer 140 , and the non-oxidized part forms the conductive structure 120 .

As shown in FIG. 4D , an electrode material layer 160 is formed on the metal oxide layer 140 . So far, the semiconductor structure 100 shown in FIG. 4D ( FIG. 1 ) is formed.

In the oxidation process, the metal layer 440 is oxidized and its volume expands, thus forming the metal oxide layer 140 as shown in FIG. . In addition, the resistive structure 150, such as the void 150b, may be formed between the outer wall 140s of the metal oxide layer 140 and the sidewall 110s of the via 110v. In an embodiment, the void 150b is formed, for example, at the bottom of the outer wall 140s of the metal oxide layer 140 . In this step, since the top surface 130 a ′ of the barrier layer 130 is lower than the top surface 440 a of the metal layer 440 , the top surface 150 b - 1 of the formed void 150 b is also lower than the top surface 140 a of the metal oxide layer 140 .

In an embodiment, the oxidation process may be, for example, a plasma oxidation process, a rapid thermal oxidation process or a photo-chemical oxidation process. However, the type of the aforementioned oxidation process can be properly selected according to practical applications, and is not limited to the aforementioned examples.

Furthermore, during the oxidation process, an exposed portion of the barrier layer 130 may also be oxidized to form a resistive structure 150, such as a metal oxide structure 150a. For example, a portion of the surface of the barrier layer 130 exposed to the metal layer 440 may be oxidized in an oxidation process to form the metal oxide structure 150a. In an embodiment, the material of the metal oxide structure 150 a includes, for example, the oxide of the barrier layer 130 . For example, when the material of the barrier layer 130 is titanium nitride, the material of the metal oxide structure 150a may include titanium oxynitride. In this step, since the top surface 130a' of the barrier layer 130 is lower than the top surface 440a of the metal layer 440, the top surface 150a-1 of the formed metal oxide structure 150a is also lower than the top surface 140a of the metal oxide layer 140. .

Please refer to FIG. 5A to FIG. 5F , which illustrate a flowchart of a manufacturing method of the semiconductor structure 200 according to another embodiment of the present invention.

As shown in FIGS. 5A-5B , an insulating structure 110 having a through hole 110v is formed, and a conductive structure 220 is formed in the through hole 110v. The manufacturing method of forming the conductive structure 220 in the through hole 110v includes the following steps, for example.

As shown in FIG. 5A , a conductive material layer 220 a is filled in the through hole 110 v. Next, as shown in FIG. 5B , a part of the conductive material layer 220a is removed to form a conductive structure 220 in the via hole 110v, and an upper portion 110r of the via hole 110v is exposed. In other words, the conductive structure 220 does not fill up to the upper portion 110r of the via hole 110v.

In an embodiment, a liner layer (not shown in the drawing) can be optionally formed between the conductive material layer 220 a and the insulating structure 110 . For example, a liner layer is firstly formed on the inner wall of the insulating structure 110, and then the conductive material layer 220a is formed on the liner layer. In this embodiment, when part of the conductive material layer 220 a is removed, part of the liner layer is also removed, so that the remaining liner layer is only located between the conductive structure 220 and the insulating structure 110 .

In an embodiment, for example, a portion of the conductive material layer 220a is removed through an etching process, and after removal, the conductive structure 220 and the upper portion 110r of the conductive structure 220 are left unfilled. As shown in FIG. 5B, the upper portion 110r is presented as a depression. In an embodiment, the depth D1 of the depression formed by the upper portion 110r is approximately the sum of the thickness of the subsequently formed barrier layer and the thickness of the metal oxide layer, for example, However, the depth D1 can be properly selected according to practical applications, such as the requirements of characteristics such as the resistance of the element, and is not limited to the aforementioned range.

As shown in FIG. 5C, a barrier layer 130' is formed on the conductive structure 220 and the sidewall 110s of the via 110v, and a metal layer 340' is formed on the barrier layer 130'. In an embodiment, the barrier layer 130' and the metal layer 340' are, for example, formed in and fill up the recess formed by the upper portion 110r of the via hole 110v.

As shown in FIG. 5D, a planarization process is performed on the barrier layer 130' and the metal layer 340' to planarize the surfaces of the barrier layer 130' and the metal layer 340' to form the barrier layer 130 and the metal layer 340. In an embodiment, the planarization process is, for example, a chemical mechanical polishing process (CMP process). After planarization, as shown in FIG. 5D , the top surface 130a of the barrier layer 130 and the top surface 340a of the metal layer 340 are flush and equiplanar. After planarization, the top surface 130a of the barrier layer 130 and the top surface 340a of the metal layer 340 may be flush and equiplanar or non-equalplanar with the top surface 110a of the insulating structure 110 . In an embodiment, as shown in FIG. 5D , the top surface 130a and the top surface 340a are not equiplanar to the top surface 110a of the insulating structure 110 .

As shown in FIG. 5E , a portion of the barrier layer 130 on the inner wall 110 s of the via hole 110 v is removed. After this step, the top surface 130a' of the barrier layer 130 and the top surface 340a of the metal layer 340 are not equiplanar. In an embodiment, for example, this part of the barrier layer 130 is removed through an etching process, and etching is performed with an etchant having a high selectivity ratio to the barrier layer 130 and the metal layer 340, so that only part of the barrier layer 130 is etched and removed. However, the structure of the metal layer 340 is not substantially damaged by etching.

As shown in FIG. 5F, an oxidation process is performed to oxidize the metal layer 340 to form a metal oxide layer 140 on the barrier layer 130, and to form a resistance structure 150 at the bottom of the outer wall 140s of the metal oxide layer 140, and to form an electrode material layer. 160 on the metal oxide layer 140 . In the embodiment, since the barrier layer 130 can prevent the penetration of oxygen, the oxidation of the metal layer 340 by the oxidation process will be blocked on the barrier layer 130, so the depth of oxidation will not diffuse down to the conductive structure 220, so that The thickness of the metal oxide layer 140 can be better controlled, and the thickness of the metal oxide layer 140 can also be relatively uniform.

In an embodiment, as shown in FIG. 5F , the electrode material layer 160 is also formed on the top surface 110 a of the insulating structure 110 .

In the oxidation process, the metal layer 340 is oxidized and its volume expands, thus forming the metal oxide layer 140 as shown in FIG. . In addition, the resistive structure 150, such as the void 150b, may be formed between the outer wall 140s of the metal oxide layer 140 and the sidewall 110s of the via 110v. In an embodiment, the void 150b is formed, for example, at the bottom of the outer wall 140s of the metal oxide layer 140 . In this step, since the top surface 130 a ′ of the barrier layer 130 is lower than the top surface 340 a of the metal layer 340 , the top surface 150 b - 1 of the formed void 150 b is also lower than the top surface 140 a of the metal oxide layer 140 .

Furthermore, during the oxidation process, an exposed portion of the barrier layer 130 may also be oxidized to form a resistive structure 150, such as a metal oxide structure 150a. For example, a portion of the surface of the barrier layer 130 exposed to the metal layer 340 may be oxidized in an oxidation process to form the metal oxide structure 150a. In an embodiment, the material of the metal oxide structure 150 a includes, for example, the oxide of the barrier layer 130 . For example, when the material of the barrier layer 130 is titanium nitride, the material of the metal oxide structure 150a may include titanium oxynitride. In this step, since the top surface 130a' of the barrier layer 130 is lower than the top surface 340a of the metal layer 340, the top surface 150a-1 of the formed metal oxide structure 150a is also lower than the top surface 140a of the metal oxide layer 140. .

So far, the semiconductor structure 200 shown in FIG. 5F ( FIG. 2 ) is formed. To sum up, in this embodiment, the thickness T2 of the metal oxide layer 140 can be controlled by adjusting the depth D1 of the depression formed by the upper part 110r of the through hole 110v, the thickness T1 of the barrier layer 130 and the planarization process of the metal layer 340' to control well. Moreover, the above-mentioned process has the advantage of being compatible with existing complementary metal-oxide-semiconductor (CMOS) processes.

Please refer to FIGS. 6A-6G , which illustrate a flow chart of a manufacturing method of the semiconductor structure 300 according to another embodiment of the present invention.

As shown in FIGS. 6A-6C , an insulating structure 210 having a through hole 210v is formed, and a conductive structure 220 is formed in the through hole 210v. The manufacturing method for forming the insulating structure 210 includes the following steps, for example.

As shown in FIG. 6A , a spacer 211 is formed, wherein the conductive structure 220 is filled in the spacer 211 such that the spacer 211 surrounds the conductive structure 220 .

In an embodiment, a liner layer (not shown in the drawing) can be optionally formed between the conductive structure 220 and the insulating structure 210 . For example, a liner layer is formed on the inner wall of the insulating structure 210 first, and then the conductive structure 220 is formed on the liner layer.

Next, as shown in FIG. 6B , an interlayer dielectric material layer 413 is formed on the spacer 211 and the conductive structure 220 .

Then, as shown in FIG. 6C , a portion of the interlayer dielectric material layer 413 located on the conductive structure 220 is removed to form an interlayer dielectric layer 213 on the spacer 211 , wherein the spacer 211 and the interlayer dielectric layer 213 are in common A via hole 210v is formed. In an embodiment, for example, a part of the interlayer dielectric material layer 413 on the conductive structure 220 is removed by a mask etching process to form the through hole 213r, and the through hole 213r penetrates the interlayer dielectric layer 213 and is connected to the conductive structure 220. In the embodiment, for example, an etchant having a high selectivity ratio to the interlayer dielectric material layer 413 and the conductive structure 220 is used for etching, so that only part of the interlayer dielectric material layer 413 is etched and removed, while the conductive structure The structure of 220 is not substantially damaged by etching. As shown in FIG. 6C , the through hole 213 r corresponding to the interlayer dielectric layer 213 and the space corresponding to the spacer 211 for accommodating the conductive structure 220 together form a via hole 210 v of the insulating structure 210 . In an embodiment, the height H1 of the interlayer dielectric layer 213 (the through hole 213r) is approximately the sum of the thickness of the subsequently formed barrier layer and the thickness of the metal oxide layer, for example, However, the height H1 can be properly selected according to practical applications, such as the requirements of characteristics such as the resistance of the element, and is not limited to the aforementioned range.

In this embodiment, the through hole 213r is further formed by depositing the interlayer dielectric layer 213. Since the thin film deposition process has a high control force on the uniformity of the film thickness, the height H1 of the through hole 213r has a high uniformity, which in turn makes the subsequent formation The thickness of the metal oxide layer 140 therein has high uniformity. According to an embodiment of the present invention, taking the semiconductor structure 300 as an example of a contact resistive memory cell structure, the thickness of the insulating layer of the memory element has high uniformity, and the resistance value of the memory element can be better controlled, thereby making the resistance The memory cell structure has better characteristics.

As shown in FIG. 6D, a barrier layer 130' is formed on the conductive structure 220 and the sidewall 110s of the via 110v, and a metal layer 340' is formed on the barrier layer 130'. In an embodiment, the barrier layer 130' and the metal layer 340' are formed and filled in the through hole 213r, for example.

As shown in FIG. 6E, a planarization process is performed on the barrier layer 130' and the metal layer 340' to planarize the surfaces of the barrier layer 130' and the metal layer 340' to form the barrier layer 130 and the metal layer 340. In an embodiment, the planarization process is, for example, a chemical mechanical polishing process. After planarization, as shown in FIG. 6E , the top surface 130 a of the barrier layer 130 and the top surface 340 a of the metal layer 340 are flush and equiplanar. After planarization, the top surface 130a of the barrier layer 130 and the top surface 340a of the metal layer 340 may be flush and equiplanar or non-equalplanar with the top surface 210a of the insulating structure 210 . In an embodiment, as shown in FIG. 6E , the top surface 130 a and the top surface 340 a are equiplanar with the top surface 210 a of the insulating structure 210 .

As shown in FIG. 6F , a portion of the barrier layer 130 on the inner wall 210 s of the via hole 210 v is removed. After this step, the top surface 130a' of the barrier layer 130 and the top surface 340a of the metal layer 340 are not equiplanar. In an embodiment, for example, this part of the barrier layer 130 is removed through an etching process, and etching is performed with an etchant having a high selectivity ratio to the barrier layer 130 and the metal layer 340, so that only part of the barrier layer 130 is etched and removed. However, the structure of the metal layer 340 is not substantially damaged by etching.

As shown in FIG. 6G, an oxidation process is performed to oxidize the metal layer 340 to form a metal oxide layer 140 on the barrier layer 130, and to form a resistance structure 150 at the bottom of the outer wall 140s of the metal oxide layer 140, and to form an electrode material layer. 160 on the metal oxide layer 140 . In the embodiment, since the barrier layer 130 can prevent the penetration of oxygen, the oxidation of the metal layer 340 by the oxidation process will be blocked on the barrier layer 130, so the depth of oxidation will not diffuse down to the conductive structure 220, so that The thickness of the metal oxide layer 140 can be better controlled, and the thickness of the metal oxide layer 140 can also be relatively uniform.

In an embodiment, as shown in FIG. 6G , the electrode material layer 160 is also formed on the top surface 210 a of the insulating structure 210 .

In the oxidation process, the metal layer 340 is oxidized and its volume expands, thus forming the metal oxide layer 140 as shown in FIG. . In addition, the resistive structure 150, such as the void 150b, may be formed between the outer wall 140s of the metal oxide layer 140 and the sidewall 210s of the via 210v. In an embodiment, the void 150b is formed, for example, at the bottom of the outer wall 140s of the metal oxide layer 140 .

Furthermore, during the oxidation process, an exposed portion of the barrier layer 130 may also be oxidized to form a resistive structure 150, such as a metal oxide structure 150a. For example, a portion of the surface of the barrier layer 130 exposed to the metal layer 340 may be oxidized in an oxidation process to form the metal oxide structure 150a. In an embodiment, the material of the metal oxide structure 150 a includes, for example, the oxide of the barrier layer 130 . For example, when the material of the barrier layer 130 is titanium nitride, the material of the metal oxide structure 150a may include titanium oxynitride.

So far, the semiconductor structure 300 shown in FIG. 6G ( FIG. 3 ) is formed. In summary, in this embodiment, the thickness T2 of the metal oxide layer 140 can be well regulated by adjusting the height H1 of the interlayer dielectric layer 213, the thickness T1 of the barrier layer 130 and the planarization process of the metal layer 340' . Moreover, the above process has the advantage of being compatible with the existing CMOS process.

FIG. 7 shows resistance-voltage curves of semiconductor structures according to an embodiment of the present invention and a comparative example. In the embodiment, taking the semiconductor structure 100 as an example, after removing a part of the barrier layer 130 on the inner wall 110s of the via hole 110v, the subsequent oxidation process can form the resistance structure 150 (such as the metal oxide structure 150a and the void 150b ) at the bottom of the outer wall 140s of the metal oxide layer 140 . In contrast, the semiconductor structure of the comparative example does not perform the process of removing a part of the barrier layer 130 on the inner wall 110s of the via hole 110v, so the oxidation process only oxidizes the top surface of the barrier layer 130, and the oxidized top surface It is co-surfaced with the top surface of the metal oxide layer 140 , so in the semiconductor structure of the comparative example, it is impossible to form the resistance structure 150 at the bottom of the outer wall 140 s of the metal oxide layer 140 . Compared with the semiconductor structure of the comparative example, which only has a thin oxide layer on the top surface of the barrier layer 130, the resistance structure 150 in the semiconductor structure 100 of the embodiment has a larger depth, so the electrode material layer 160 can be isolated more effectively. and the conductive structure 120 , reducing electrical interference between the electrode material layer 160 and the conductive structure 120 , thereby increasing the breakdown voltage of the semiconductor structure 100 of the embodiment.

As shown in FIG. 7 , curve I represents the resistance-voltage curve of the semiconductor structure of the comparative example, and curve II represents the resistance-voltage curve of the semiconductor structure 100 of the embodiment. As shown in FIG. 7 , the breakdown voltage of the semiconductor structure of the comparative example is about 5.5-6V, while the semiconductor structure 100 of the embodiment may have a breakdown voltage of at least 8V, which is much higher than the breakdown voltage of the semiconductor structure of the comparative example.

To sum up, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (10)

1. A semiconductor structure comprising: The insulating structure has a through hole (via); a stop layer formed in the through hole; a metal oxide layer formed on the barrier layer; a resistance structure formed at a bottom of an outer wall of the metal oxide layer; and an electrode material layer formed on the metal oxide layer; Wherein, the resistance structure includes at least one of a metal oxide structure or a void. 2. The semiconductor structure according to claim 1, further comprising: A conductive structure is formed in the through hole, wherein the barrier layer is formed on the conductive structure. 3. The semiconductor structure according to claim 1, wherein the barrier layer has a thickness of The thickness of the metal oxide layer is 4. The semiconductor structure of claim 1, wherein the barrier layer comprises at least one of a metal nitride or an inert metal. 5. A resistive random access memory unit (Resistive random access memory unit) structure, comprising: The insulating structure has a through hole (via); a barrier layer formed in the through hole; a storage element (memory element), formed on the barrier layer; a resistive structure formed at a bottom of an outer wall of the memory element; and a top electrode layer formed on the memory element; Wherein, the resistance structure includes at least one of a metal oxide structure or a void. 6. The resistive memory cell structure according to claim 5, further comprising: A contact structure is formed in the through hole, wherein the barrier layer is formed on the contact structure. 7. The resistive memory cell structure according to claim 5, wherein the barrier layer comprises titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), gold (Au) and platinum (Pt) at least one of the . 8. A method of fabricating a semiconductor structure, comprising: forming an insulating structure with a through hole (via); forming a barrier layer in the through hole and on a side wall of the through hole; forming a metal layer on the barrier layer; removing a portion of the barrier layer on an inner wall of the through hole; performing an oxidation process to oxidize the metal layer to form a metal oxide layer on the barrier layer and to form a resistance structure at a bottom of an outer wall of the metal oxide layer; and forming an electrode material layer on the metal oxide layer; Wherein, the oxidation process is performed to further oxidize an exposed portion of the barrier layer to form the resistance structure. 9. The method for manufacturing a semiconductor structure according to claim 8, further comprising: A conductive structure is formed in the through hole, wherein the blocking layer is further formed on the conductive structure. 10. The manufacturing method of the semiconductor structure according to claim 8, wherein the part of the barrier layer on the inner wall of the through hole is removed through an etching process.