CN105097703A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- CN105097703A CN105097703A CN201410175156.3A CN201410175156A CN105097703A CN 105097703 A CN105097703 A CN 105097703A CN 201410175156 A CN201410175156 A CN 201410175156A CN 105097703 A CN105097703 A CN 105097703A
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Abstract
The invention discloses a semiconductor device manufacturing method. A semiconductor substrate is provided, and a first gate electrode material layer, a gate dielectric layer, a second gate electrode material layer and a patterned hard mask film layer are formed on the semiconductor substrate in turn; the second gate electrode material layer and the gate dielectric layer are etched in turn according to the patterned hard mask film layer so that trenches are formed; a third gate electrode material layer is formed in the trenches so that the trenches are filled; a polishing technology is performed so that the third gate electrode material layer arranged on the patterned hard mask film layer is removed; and the patterned hard mask film layer is removed so that the second gate electrode material layer is exposed. A control gate electrode polysilicon layer manufactured according to the method has no interface, and the side wall of a second polysilicon layer is not damaged.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly relate to a kind of method making semiconductor device.
Background technology
Along with the development of semiconductor technology, the raising of performance of integrated circuits is mainly realized with the speed improving it by the size constantly reducing integrated circuit (IC)-components.In nand flash memory technique also, along with self-aligned double patterning case (selfaligneddoublepatterning, SaDP) development of control gate lithographic technique, regulates the side wall profile of the first polysilicon layer (P1) for the formation of floating grid and the second polysilicon layer (P2) for the formation of control gate to be that industry needs one of significant challenge faced.
In nand flash memory, the manufacture craft of grid is in the prior art, first deposition forms ONO polysilicon layer 100, then ONO polysilicon layer 100 (as Figure 1A) is etched, then depositional control gate polysilicon layer 101 (as Figure 1B), finally etch control gate polysilicon layer, to form final grid structure.Wherein, ONO polysilicon layer is used for the critical size of reduction of device, and the ONO polysilicon layer of taper is for reducing the critical size of ONO.Result is 70nm to the ADI (checking after development) of existing ONO layer, if its critical size reduces further, subsequent technique will not have process window.Meanwhile, if not this ONO polysilicon layer, etching deviation will more than 30nm, and the final semiconductor device made is difficult to the requirement (as Figure 1A) reaching AEI (checking after etching) 80nm.Therefore, existing the second polysilicon layer for the formation of control gate is made up of ONO polysilicon layer and control gate polysilicon layer, but can form obvious interface between in the process that deposition forms described ONO polysilicon layer and control gate polysilicon layer, it can cause the control gate sidewall bottom described second polysilicon layer often to sustain damage.
Therefore, need a kind of method of making semiconductor device newly, there is no boundary layer to make the control gate polysilicon layer of formation.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
In order to solve problems of the prior art, the present invention proposes one and Semiconductor substrate is provided, form the hard mask layer of first grid material layer, gate dielectric layer, second grid material layer and patterning on the semiconductor substrate successively; Described second grid material layer and described gate dielectric layer is etched successively, to form groove according to the hard mask layer of described patterning; Form the 3rd gate material layers in the trench, to fill described groove; Perform flatening process, with remove be positioned at described patterning hard mask layer on described 3rd gate material layers; Remove the hard mask layer of described patterning, to expose described second grid material layer.
Preferably, the hard mask layer of described patterning is single layer structure or sandwich construction.
Preferably, the material of described gate dielectric layer is ONO.
Preferably, epitaxial growth technology is adopted to form described 3rd gate material layers.
Preferably, dry etching or wet etching is adopted to remove the hard mask layer of described patterning.
Preferably, dry etch process is adopted to perform described etch step.
Preferably, described dry etching stops at described first grid material layer.
Preferably, described second grid material layer is identical with the constituent material of described 3rd gate material layers.
Preferably, the constituent material of described second grid material layer and described 3rd gate material layers is polysilicon.
Preferably, the sidewall of described groove has the gradient.
In sum, the control gate polysilicon layer that method according to the present invention makes does not have interface, and the sidewall of the second polysilicon layer does not sustain damage.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A-1B is the cross-sectional view of correlation step of the semiconductor device made according to prior art;
The cross-sectional view of the device that Fig. 2 A-2E obtains for the correlation step making semiconductor device structure according to one embodiment of the present invention;
Fig. 3 is the process chart making semiconductor device structure according to one embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it will be apparent to one skilled in the art that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to illustrate how the present invention solves the problems of the prior art.Detailed being described below of obvious preferred embodiment of the present invention, but remove outside these detailed descriptions, the present invention can also have other execution modes.
Should give it is noted that term used here is only to describe specific embodiment, and be not intended to restricted root according to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative be also intended to comprise plural form.In addition, it is to be further understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.Should be understood that, providing these embodiments to be of the present inventionly disclose thorough and complete to make, and the design of these exemplary embodiments fully being conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, exaggerate the thickness in layer and region, and use the element that identical Reference numeral represents identical, thus will omit description of them.
Be described in detail the manufacture method of grid of the present invention below in conjunction with Fig. 2 A-2E, Fig. 2 A-2E is the structural section figure making device architecture in the process of grid according to the present embodiment.
As shown in Figure 2 A, Semiconductor substrate (not shown) is provided, Semiconductor substrate can comprise any semi-conducting material, this semi-conducting material can include but not limited to: Si, SiC, SiGe, SiGeC, Ge alloy, GeAs, InAs, InP, and other III-V or group Ⅱ-Ⅵ compound semiconductor.Described Semiconductor substrate comprises core device region and peripheral devices district, and described core device region comprises selects transistor and memory cell.
Form first grid material layer 200 on the semiconductor substrate, the material of first grid material layer is preferably polysilicon.The formation method of polysilicon can select low-pressure chemical vapor phase deposition (LPCVD) technique.The process conditions forming described polysilicon comprise: reacting gas is silane (SiH
4), the range of flow of described silane can be 100 ~ 200 cc/min (sccm), as 150sccm; In reaction chamber, temperature range can be 700 ~ 750 degrees Celsius; Reaction chamber internal pressure can be 250 ~ 350 millis millimetres of mercury (mTorr), as 300mTorr; Also can comprise buffer gas in described reacting gas, described buffer gas can be helium or nitrogen, and the range of flow of described helium and nitrogen can be 5 ~ 20 liters/min (slm), as 8
sl
m, 10
sl
mor 15
sl
m.
The method that it should be noted that above-mentioned formation first grid material layer is only exemplary, does not limit to and the method, and those skilled in the art can also select other conventional methods.Described first polysilicon layer is for the formation of the floating grid of memory cell being positioned at described core device region.
Described first grid material layer 200 forms gate dielectric layer 201.Concrete, gate dielectric layer 201 can be oxide, nitride, oxide three layers of ONO sandwich structure altogether, those skilled in the art should be understood that, gate dielectric layer 201 also can for one deck nitride or one deck oxide or one deck nitride form the gate dielectric layer structures such as one deck oxide.Can use and include but not limited to: the method for chemical vapor deposition and/or physical vapor deposition forms gate dielectric layer 201.In of the present invention one particularly execution mode, gate dielectric layer structure is the sandwich structure of oxide, nitride, oxide three layers (ONO) altogether.
Gate dielectric layer 201 is formed second grid material layer 202, second grid material layer 202 can comprise the polysilicon of doping and polysilicon-Ge alloy material and polycide (polycide) material, wherein, the preferred polysilicon of the material of second grid material layer.Described second grid material layer is for the formation of the control gate of described memory cell.
The formation process of described second grid material layer can adopt any prior art well known to those skilled in the art, comparative optimization be chemical vapour deposition technique, such as low-voltage plasma body chemical vapor phase growing or plasma enhanced chemical vapor deposition technique.
Second grid material layer 202 is formed the hard mask layer 203 of patterning, wherein, the hard mask layer 203 of described patterning can be individual layer or multilayer, the material of the hard mask layer 203 of individual layer can be the such as similar material such as silicon nitride, oxide, and the material of the hard mask layer 203 of multilayer can comprise a-C (amorphous carbon) and silicon oxynitride layer, ODL (organic distribution layer) and Si-BARC (bottom antireflective coating), NFC (having negative fixed charge) and LTO (low temperature oxide).Hard mask layer can use and include but not limited to: the method for process for chemical vapor deposition of materials with via and physical vapor deposition methods is formed.
Wherein, the step forming the hard mask layer 203 of described patterning is: the photoresist layer 204 forming patterning on hard mask layer 203, and the photoresist layer 204 of described patterning has opening 205.Described patterns of openings is positioned at the transistor in described selection transistor and/or peripheral devices district, such as, on high voltage transistor.Then, etch described hard mask layer 203 according to the photoresist layer 204 of patterning, to form the hard mask layer 203 of patterning.
Other substrate materials can comprise the Other substrate materials be selected from the group comprising positive-tone photo glue material, negative photo glue material and mixing Other substrate materials.In the present invention one specific embodiment, between described hard mask layer 203 and the photoresist layer 204 of described patterning, there is bottom antireflective coating.
As shown in Figure 2 B, described second grid material layer 202 is etched according to the hard mask layer 203 of patterning and gate dielectric layer 201 stops at described first grid material layer 200, to form groove 206.Dry etch process can be adopted, such as the combination in any of reactive ion etching, ion beam etching, plasma etching, laser ablation or these methods.Single lithographic method can be used, or also can use more than one lithographic method.Etching gas comprises HBr, Cl
2, CH
2f
2, O
2one or several gases, and some add gases as nitrogen, argon gas.The range of flow of described etching gas can be 0 ~ 150 cc/min (sccm), and reative cell internal pressure can be 3 ~ 50 millitorrs (mTorr), is to carry out plasma etching under the condition of 600W ~ 1500W at radio-frequency power.
Exemplarily, by controlling the etching speed of second grid material layer 202, controlling the profile of described groove and then controlling the critical size of bottom gate dielectric layer 202.The sidewall of described groove preferably has the gradient, to reduce the opening size of above-mentioned gate dielectric layer.
As shown in Figure 2 C, adopt epitaxial growth technology to form the 3rd gate material layers 207 in described groove 206, described 3rd gate material layers is preferably polysilicon.Described polysilicon layer 207 is filling groove 206 completely, and higher than hard mask layer 203.Described second grid material layer is electrically connected with described first grid material layer by described 3rd gate material layers, thus forms the grid of described selection transistor and/or high voltage transistor.
In an embodiment of the present invention, the epitaxial growth method of described polysilicon layer 207 is: by hydrogen (H
2) gas carries silicon tetrachloride (SiCl
4) or trichlorosilane (SiHCl
3), silane (SiH
4) or dichloro hydrogen silicon (SiH
2cl
2) etc. enter the reative cell being equipped with silicon substrate, carry out high-temperature chemical reaction at reative cell, make siliceous reacting gas reduce or thermal decomposition, the silicon atom produced is at substrate silicon surface Epitaxial growth.The highly diluted ratio of 98.5% can be selected in this step, the temperature of reaction is 1500-1800 DEG C, and to control air pressure be about 1pa, the substrate Epitaxial growth that can be 200 DEG C in temperature obtains the silicon thin film of 200nm or more, can also regulate temperature in this step, the time controls silicon thin film.
As shown in Figure 2 D, flatening process is performed to remove the polysilicon layer 207 be positioned on hard mask layer 203.
Flattening method conventional in field of semiconductor manufacture can be used to realize the planarization on surface.The limiting examples of this flattening method comprises mechanical planarization method and chemico-mechanical polishing (CMP) flattening method.Chemico-mechanical polishing flattening method is more conventional.In the present invention one specific embodiment, preferably adopt chemico-mechanical polishing flattening method slightly, to avoid the damage to described second grid material layer and described 3rd gate material layers.
Exemplarily, polysilicon layer 207, after flatening process process, eliminates the polysilicon layer be positioned on hard mask layer 203, flushes to make remaining polysilicon layer 207 and second grid material layer 202.
Then, as shown in Figure 2 E, etching removes the hard mask layer 203 be positioned on second grid material layer 202.
Etching removes the hard mask layer 203 be positioned on second grid material layer 202 can adopt selectivity dry etching or wet etching in the same way.
Alternatively, the combination in any of dry etching such as reactive ion etching, ion beam etching, plasma etching, laser ablation or these methods.Single lithographic method can be used, or also can use more than one lithographic method.Such as using plasma etching, etching gas can adopt based on fluorine-containing gas.Concrete, adopt lower radio-frequency (RF) energy also can produce low pressure and highdensity plasma gas to realize dry etching.As an example, the range of flow of the etching gas of using plasma etching can be 50 cc/min (sccm) ~ 150 cc/min (sccm), and reative cell internal pressure can be 5 millitorrs (mTorr) ~ 20 millitorr (mTorr).Wherein, the etching gas of dry etching can be bromize hydrogen gas, carbon tetrafluoride gas or gas of nitrogen trifluoride, can also pass into some and add gas, as nitrogen, helium or oxygen etc.
Alternatively, wet etch method can adopt hydrofluoric acid solution, such as buffer oxide etch agent or hydrofluoric acid cushioning liquid.
It should be noted that, the method that above-mentioned etching removes hard mask layer 203 is exemplary, is not limited to described method, as long as this area additive method can realize described object, all can be applied to the present invention, repeat them here.
With reference to Fig. 3, illustrated therein is the process chart into making semiconductor device according to one embodiment of the present invention.For schematically illustrating the flow process of whole manufacturing process.
In step 301, provide Semiconductor substrate, form the hard mask layer of first grid material layer, gate dielectric layer, second grid material layer and patterning on the semiconductor substrate successively;
In step 302, described second grid material layer and described gate dielectric layer is etched to form groove according to the hard mask layer of patterning;
In step 303, epitaxial growth polysilicon layer in the trench;
In step 304, flatening process is adopted to remove the polysilicon layer be positioned on hard mask layer;
In step 305, described hard mask layer is removed.
In sum, the control gate polysilicon layer that method according to the present invention makes does not have interface, and the edge of the second polysilicon does not sustain damage.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to the present invention, within these variants and modifications all drop on the present invention's scope required for protection.
Claims (10)
1. make a method for semiconductor device, comprising:
Semiconductor substrate is provided,
Form the hard mask layer of first grid material layer, gate dielectric layer, second grid material layer and patterning on the semiconductor substrate successively;
Described second grid material layer and described gate dielectric layer is etched successively, to form groove according to the hard mask layer of described patterning;
Form the 3rd gate material layers in the trench, to fill described groove;
Perform flatening process, with remove be positioned at described patterning hard mask layer on described 3rd gate material layers;
Remove the hard mask layer of described patterning, to expose described second grid material layer.
2. the method for claim 1, is characterized in that, the hard mask layer of described patterning is single layer structure or sandwich construction.
3. the method for claim 1, is characterized in that, the material of described gate dielectric layer is ONO.
4. the method for claim 1, is characterized in that, adopts epitaxial growth technology to form described 3rd gate material layers.
5. the method for claim 1, is characterized in that, adopts dry etching or wet etching to remove the hard mask layer of described patterning.
6. the method for claim 1, is characterized in that, adopts dry etch process to perform described etch step.
7. method as claimed in claim 6, it is characterized in that, described dry etching stops at described first grid material layer.
8. the method for claim 1, is characterized in that, described second grid material layer is identical with the constituent material of described 3rd gate material layers.
9. method as claimed in claim 8, it is characterized in that, the constituent material of described second grid material layer and described 3rd gate material layers is polysilicon.
10. the method for claim 1, is characterized in that, the sidewall of described groove has the gradient.
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| CN201410175156.3A CN105097703B (en) | 2014-04-28 | 2014-04-28 | A method of making semiconductor devices |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115132734A (en) * | 2021-03-25 | 2022-09-30 | 中芯北方集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
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| CN1354521A (en) * | 2000-09-26 | 2002-06-19 | 株式会社东芝 | Semiconductor device and manufacturing mehtod thereof |
| US20040238849A1 (en) * | 2003-05-30 | 2004-12-02 | Tadashi Miwa | Semiconductor device and manufacturing method thereof |
| US20050082602A1 (en) * | 2003-10-20 | 2005-04-21 | Mutsumi Okajima | Semiconductor device and method of manufacturing the same |
| US20090011558A1 (en) * | 2006-11-30 | 2009-01-08 | Mutsumi Okajima | Method of manufacturing nonvolatile semiconductor memory |
| CN102088001A (en) * | 2009-12-04 | 2011-06-08 | 中芯国际集成电路制造(上海)有限公司 | Flash memory and manufacturing method thereof |
| US20120025289A1 (en) * | 2010-07-28 | 2012-02-02 | Jarrett Jun Liang | Metal control gate formation in non-volatile storage |
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2014
- 2014-04-28 CN CN201410175156.3A patent/CN105097703B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1354521A (en) * | 2000-09-26 | 2002-06-19 | 株式会社东芝 | Semiconductor device and manufacturing mehtod thereof |
| US20040238849A1 (en) * | 2003-05-30 | 2004-12-02 | Tadashi Miwa | Semiconductor device and manufacturing method thereof |
| US20050082602A1 (en) * | 2003-10-20 | 2005-04-21 | Mutsumi Okajima | Semiconductor device and method of manufacturing the same |
| US20090011558A1 (en) * | 2006-11-30 | 2009-01-08 | Mutsumi Okajima | Method of manufacturing nonvolatile semiconductor memory |
| CN102088001A (en) * | 2009-12-04 | 2011-06-08 | 中芯国际集成电路制造(上海)有限公司 | Flash memory and manufacturing method thereof |
| US20120025289A1 (en) * | 2010-07-28 | 2012-02-02 | Jarrett Jun Liang | Metal control gate formation in non-volatile storage |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115132734A (en) * | 2021-03-25 | 2022-09-30 | 中芯北方集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
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