CN105097694B

CN105097694B - Preparation method of semiconductor device

Info

Publication number: CN105097694B
Application number: CN201410217871.9A
Authority: CN
Inventors: 涂火金
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2014-05-21
Filing date: 2014-05-21
Publication date: 2020-06-09
Anticipated expiration: 2034-05-21
Also published as: CN105097694A

Abstract

The invention relates to a preparation method of a semiconductor device, which comprises the following steps: providing a semiconductor substrate, wherein a grid structure is formed on the semiconductor substrate; performing ion implantation on two sides of the gate structure; carrying out pre-cleaning treatment on the surface of the semiconductor substrate to remove amorphous substances formed on the surface of the semiconductor substrate in the ion implantation step; and epitaxially growing a first semiconductor material layer on the semiconductor substrate on the two sides of the processed gate structure. According to the invention, the Si layer is formed in the PMOS region, then HCl is selected to process the surface of the source drain region of the NMOS region, a groove is formed on the source drain of the NMOS region while the Si layer on the PMOS region is removed, and then the Si layer is epitaxially grown again to form epitaxial Si layers on the source drain of the NMOS region and the source drain of the PMOS region, so that the stress design on the source drain of the NMOS region and the source drain of the PMOS region is realized, and the performance and the yield of a semiconductor device are improved.

Description

Preparation method of semiconductor device

Technical Field

The invention relates to the field of semiconductors, in particular to a preparation method of a semiconductor device.

Background

As integrated circuit technology continues to advance, more devices will be integrated on a chip, and the chip will also adopt faster speeds. With these demands, the geometric size of the device will be reduced, and new materials, new technologies and new manufacturing processes are adopted in the chip manufacturing process. At present, the preparation of semiconductor devices has been developed to the nanometer level, and meanwhile, the preparation process of the conventional devices is gradually mature.

In the prior art, a recess is generally formed on a PMOS source and a drain, then SiGe is epitaxially grown, a Si layer is generally grown on the source and the drain of the PMOS/NMOS in the PMOS/NMOS device, and then NiSi with high quality is further formed; in the NMOS device, a step of performing heavy ion implantation (Implantation implantation) is further included before the Si layer is epitaxially grown in order to further improve the performance.

Specifically, in the prior art, as shown in fig. 1a-1b, a semiconductor substrate 11 is provided, and an NMOS region and a PMOS region are formed in the semiconductor substrate to form a PMOS device and an NMOS device, respectively, and then an NMOS gate structure 12' and a PMOS gate structure 12 are formed in the NMOS region, a recess is formed in the PMOS region at two sides of the PMOS gate structure 12, and a SiGe layer 14 and a second semiconductor material layer 13 are epitaxially grown, after the SiGe layer 14 is formed, heavy ion implantation (implantation height) may be performed in the NMOS region to form a source drain region (not shown in the figure), and then referring to fig. 1b, a Si layer is epitaxially grown on the source drain region of the NMOS region and the PMOS region, however, since heavy ion implantation (implantation) is performed in the NMOS region, an amorphous material (amorphous) is formed on the surface of the NMOS region, and thus an Si layer cannot be epitaxially grown on the NMOS region, which causes difficulty in manufacturing.

Therefore, although the PMOS region can be designed with stress in the prior art, the NMOS region has a surface morphology that changes in the middle of the heavy ion implantation (implantation) process, and the Si layer cannot be epitaxially grown on the surface of the NMOS region, which is a problem that is difficult to overcome in device fabrication.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In order to solve the above problems, the present invention provides a method for manufacturing a semiconductor device, comprising:

providing a semiconductor substrate, wherein a grid structure is formed on the semiconductor substrate;

performing ion implantation on two sides of the gate structure;

carrying out pre-cleaning treatment on the surface of the semiconductor substrate to remove amorphous substances formed on the surface of the semiconductor substrate in the ion implantation step;

and epitaxially growing a first semiconductor material layer on the semiconductor substrate on the two sides of the gate structure after the pre-cleaning treatment.

Preferably, the method comprises:

providing a semiconductor substrate, wherein an NMOS region and a PMOS region are formed on the semiconductor substrate, and an NMOS gate structure and a PMOS gate structure are respectively formed on the NMOS region and the PMOS region;

performing ion implantation on two sides of the NMOS gate structure and the PMOS gate structure;

forming grooves in the semiconductor substrate on two sides of the PMOS gate structure, and epitaxially growing a stress layer and a second semiconductor material layer in the grooves;

carrying out pre-cleaning treatment on the surface of the semiconductor substrate to remove the amorphous substances formed in the ion implantation step and remove the second semiconductor material layer at the same time;

and epitaxially growing the first semiconductor material layer on the semiconductor substrate on two sides of the NMOS gate structure and the stress layer on two sides of the PMOS gate structure.

Preferably, the stress layer is a SiGe layer, the first semiconductor material layer is a Si layer, and the second semiconductor material layer is Si.

Preferably, the method further comprises, after forming the first layer of semiconductor material, the step of further processing the first layer of semiconductor material to form NiSi.

Preferably, the height of the first semiconductor material layer is greater than the height of the semiconductor substrate to form an elevated first semiconductor material layer.

Preferably, HCl gas is selected to perform a pre-cleaning process on the surface of the semiconductor substrate to remove the amorphous material.

Preferably, the first layer of semiconductor material is epitaxially grown at a temperature of 500-800 deg.C and a pressure of 1-100 torr.

Preferably, the reaction gas for epitaxially growing the first semiconductor material layer is SiH₄Or SiH₂Cl₂、HCl、B₂H₆Mixed gas of Si and SiH₄Or SiH₂Cl₂、B₂H₆The gas flow rate of HCl is 1sccm-1000 sccm.

Preferably, H is selected₂As a reaction carrier gas, the H₂The gas flow rate of (a) is 0.1slm to 50 slm.

In order to solve the problem that a Si layer cannot grow on the surface of the NMOS region after source and drain injection in the prior art, HCl is selected to pre-clean the surface of the source and drain region of the NMOS region after the Si layer is formed in the PMOS region, a groove is formed on the source and drain of the NMOS region while the Si layer on the PMOS region is removed, and then the Si layer is epitaxially grown again to form epitaxial Si layers on the source and drain of the NMOS region and the PMOS region, so that the stress design on the source and drain of the NMOS and PMOS regions is realized, and the performance and the yield of a semiconductor device are improved.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. There are shown in the drawings, embodiments and descriptions thereof, which are used to explain the principles and apparatus of the invention. In the drawings, there is shown in the drawings,

FIGS. 1a-1b are schematic diagrams of prior art semiconductor device fabrication;

FIGS. 2a-2c are schematic structural diagrams illustrating the fabrication of a semiconductor device in accordance with one embodiment of the present invention;

fig. 3 is a process flow diagram for fabricating a semiconductor device in accordance with an embodiment of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

In order to thoroughly understand the present invention, a detailed description will be given in the following description to illustrate a method of manufacturing a semiconductor device according to the present invention. It will be apparent that the invention may be practiced without limitation to specific details that are within the skill of one of ordinary skill in the semiconductor arts. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention. As used herein, the singular is intended to include the plural unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Exemplary embodiments according to the present invention will now be described in more detail with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity, and the same elements are denoted by the same reference numerals, and thus the description thereof will be omitted.

In order to solve the problem that a Si layer cannot grow on the surface of the NMOS region after source and drain injection in the prior art, HCl is selected to pre-clean the surface of the source and drain region of the NMOS region after the Si layer is formed in the PMOS region, the Si layer on the PMOS region is removed, the surface of the NMOS region is removed at the same time, so that amorphous substances generated in heavy ion injection are removed, a groove is formed on the source and drain of the NMOS region, then the Si layer is epitaxially grown again, so that epitaxial Si layers are formed on the source and drain of the NMOS region and the PMOS region, and the problems in the prior art are well solved, and the method is further described with reference to the attached drawings 1a-1 b.

First, step 201 is executed to provide a semiconductor substrate 101, wherein an NMOS region and a PMOS region are formed on the semiconductor substrate 101, and an NMOS gate structure 102' and a PMOS gate structure 102 are formed in both the NMOS region and the PMOS region.

Specifically, referring to fig. 2a, first, a semiconductor substrate 101 is provided, the semiconductor substrate 101 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. In the present invention, silicon-on-insulator (SOI) is preferable, and the silicon-on-insulator (SOI) includes a support substrate, an oxide insulating layer, and a semiconductor material layer in this order from bottom to top, but is not limited to the above example.

An isolation structure is formed in the semiconductor substrate 101, and the isolation structure is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure. Various well structures and channel layers on the surface of the substrate are also formed in the semiconductor substrate. Generally, the ion doping conductivity type of the well (well) structure is the same as that of the channel layer, but the concentration of the well (well) structure is lower than that of the gate channel layer, the ion implantation depth is wider, and the depth of the well (well) structure is required to be larger than that of the isolation structure.

An NMOS region and a PMOS region are respectively formed in the semiconductor substrate, an NMOS gate structure 102' is formed on the NMOS region, and a PMOS gate structure 102 is formed on the PMOS region.

Wherein the number of the NMOS gate structures 102 'and the number of the PMOS gate structures 102 are not limited to a certain range of values, in a specific embodiment of the present invention, the number of the NMOS gate structures 102' is 3, and the number of the PMOS gate structures 102 is 1.

Specifically, a gate dielectric layer (not shown) is formed on the semiconductor substrate 101, and the gate dielectric layer may be silicon oxide (SiO)₂) Or silicon oxynitride (SiON). Oxidation processes known to those skilled in the art may be employedSuch as furnace oxidation, rapid thermal annealing oxidation (RTO), in-situ steam oxidation (ISSG), etc., to form a gate dielectric layer of silicon oxide. A layer of gate material is then deposited, comprising a multi-layer structure of semiconductor material, such as silicon, germanium, metal, or combinations thereof. And etching the grid dielectric layer and the grid material layer to form a grid structure.

Preferably, spacers (not shown in the figure) may be further formed on both sides of the gate structure in this step, and the spacers may be made of one or a combination of silicon oxide, silicon nitride and silicon oxynitride. As an optimized implementation manner of this embodiment, the spacer is composed of silicon oxide and silicon nitride, and the specific process includes: a first silicon oxide layer, a first silicon nitride layer and a second silicon oxide layer are formed on a semiconductor substrate, and then a spacer is formed by an etching method.

Further, a step of forming offset sidewalls may be further included between the forming of the spacers, wherein the shallow trench and the gate structure, the ion implantation, and the like are exemplary and not limited to this embodiment, and those skilled in the art may select other methods commonly used in the art or form other active devices in the substrate according to the requirement of device fabrication.

Step 202 is executed to perform ion implantation on two sides of the NMOS gate structure 102' and the PMOS gate structure 102.

Specifically, the implantation is performed at two sides of the NMOS gate structure 102' and the PMOS gate structure 102 with an ion energy of 1kev to 10kev and an ion dose of 5 × 10¹⁴-5×10¹⁶Atom/cm². In the step, a layer of amorphous substance is formed on the surface of the NMOS region after the NMOS region is heavily ion-implanted, and the growth of the Si material layer on the surface of the Si material layer is hindered in the subsequent step.

Step 203 is executed, a groove is formed in the semiconductor substrate 101 at two sides of the PMOS gate structure 102, and the stress layer 104 and the second semiconductor material layer 103 are epitaxially grown in the groove.

Specifically, with continued reference to FIG. 2a, recesses are etched into the PMOS region on both sides of the PMOS gate 102. in the present invention, it is preferred to form a "sigma" shaped recess, as shown in FIG. 2a, and then epitaxially grow a SiGe layer in the recess.

The deposition of the SiGe layer may be one of Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD) and Selective Epitaxial Growth (SEG) formed by selective Chemical Vapor Deposition (CVD), non-selective Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD). Chemical Vapor Deposition (CVD) is preferred in the present invention.

Specifically, a source gas, such as GeH gas containing Ge, is introduced during the deposition of the SiGe layer₄And select H₂As a carrier gas, wherein the flow ratio of the reaction gas and the carrier gas is 0.01, SiH is selected₂Cl₂As the reaction gas, H is selected₂As the carrier gas, wherein the flow ratio of the reaction gas and the carrier gas is 0.01, the deposition temperature is 500-950 ℃, preferably 650-750 ℃, and the gas pressure is 10-100Torr, preferably 20-40 Torr.

Preferably, the step of planarization is further included after the SiGe layer is formed, and the planarization of the surface can be achieved by using a planarization method which is conventional in the field of semiconductor manufacturing. Non-limiting examples of the planarization method include a mechanical planarization method and a chemical mechanical polishing planarization method. Chemical mechanical polishing planarization methods are more commonly used.

In this step, a step of epitaxially growing a second semiconductor material layer 103 is further included, and specifically, in an embodiment of the present invention, in order to epitaxially grow the first semiconductor material layer 105 on the NMOS region, HCl is selected to perform a pre-cleaning process on the NMOS region and the PMOS region, but the HCl has a larger etching capability for the SiGe layer, so that the second semiconductor material layer 103 needs to be formed on the SiGe layer to protect the SiGe layer from being etched.

Preferably, the second semiconductor material layer 103 is preferably Si, and specifically, the reaction gas may include hydrogen (H)₂) Entrained silicon tetrachloride (SiCl)₄) Or trichlorosilane (SiHCl)₃) Silane (SiH)₄) And dichlorosilane (SiH)₂Cl₂) And the like, into a reaction chamber in which the silicon substrate is placed, and a high-temperature chemical reaction is performed in the reaction chamber to reduce or thermally decompose a silicon-containing reaction gas, and the resulting silicon atoms are epitaxially grown on the surface of the SiGe layer.

Step 204 is executed to perform a pre-cleaning process on the surface of the semiconductor substrate 101 to remove the amorphous material formed in the ion implantation step and to remove the second semiconductor material layer 103 at the same time.

Specifically, referring to fig. 2b, the surface of the NMOS is pre-cleaned to remove the amorphous material on the surface of the NMOS area to form the recess 20 and simultaneously remove the second semiconductor material layer 103, in the present invention, the semiconductor substrate on both sides of the NMOS gate is pre-cleaned to remove the amorphous material formed during the ion implantation process and to perform pre-cleaning for the deposition of the first semiconductor material layer 105, preferably, the etching gas selected for etching in this step is HCl, and the carrier gas of the etching gas is H₂。

In an embodiment of the invention, the etching gas is HCl, wherein the etching temperature is 500-850 ℃, more preferably 600-700 ℃, the HCl gas flow is 20-500 sccm, and the H gas flow is₂The gas flow of (a) is 15-45 slm, the gas flow of HCl and H₂The gas flow rate ratio of (2-5X 10)^-3In the present invention, it is preferably 3.5 to 4X 10^-3The etching effect is better in the preferable range.

And forming a groove 20 on the source and drain of the NMOS after the pre-cleaning treatment, wherein the depth of the groove 20 is not limited to a certain numerical range, and the groove can be designed according to requirements, wherein the second semiconductor material layer 103 is completely removed in the step, and the etching is stopped until the second semiconductor material layer 103 is just removed, so that the SiGe layer is prevented from being damaged.

And step 205 is executed, and the first semiconductor material layer 105 is epitaxially grown on the semiconductor substrate on two sides of the NMOS gate structure and on the stress layer 104 on two sides of the PMOS gate structure.

Specifically, referring to fig. 2c, the first semiconductor material layer 105 is formed by using an epitaxial growth method, and the selective epitaxial growth method may be one of Low Pressure Chemical Vapor Deposition (LPCVD), ultra low pressure chemical vapor deposition (VLPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Ultra High Vacuum Chemical Vapor Deposition (UHVCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Atmospheric Pressure Chemical Vapor Deposition (APCVD), and Molecular Beam Epitaxy (MBE). The selective epitaxial growth can be performed in a reaction chamber of UHV/CVD process, for example, and the process temperature is approximately in the range of 550-880 ℃.

The reaction gas for epitaxial growth is SiH₄Or SiH₂Cl₂Mixed gas of (3), HCl, B₂H₆And H₂The mixed gas of (4), wherein the SiH4 and the SiH₂Cl₂、B₂H₆HCl gas flow rate is 1sccm-1000sccm, wherein H₂As a reaction carrier gas, H₂The gas flow rate of (a) is 0.1slm to 50 slm.

Preferably, the epitaxy temperature of the first layer of semiconductor material 105 in this step is 500-800 ℃ and the epitaxy pressure is 1-100 torr.

Preferably, the method may further include a step of performing source and drain implantation, and In a specific embodiment of the present invention, the source and drain implantation is performed on the NMOS region and the PMOS region, wherein heavy ion implantation is selected In the present invention, and In this step, the ion is one or more of B, BFx, BHx, P, As, In, C, and Ge, and the ion implantation dose is 10E16-10E13 atoms/cm³The ion implantation energy is 1KeV-500KeV, and a lower implantation temperature is selected in the step.

Preferably, an annealing step may be further performed after the source-drain implantation, and specifically, after the thermal annealing step is performed, damage on the silicon wafer may be eliminated, the minority carrier lifetime and the mobility may be recovered to different degrees, and impurities may also be activated to a certain ratio, so that the device efficiency may be improved.

The annealing step is generally to heat the substrate to a certain temperature under the protection of high vacuum or high purity gas, wherein the high purity gas is preferably nitrogen or inert gas, the temperature of the thermal annealing step is 800-.

As a further preference, rapid thermal annealing may be selected in the present invention, and specifically, one of the following modes may be selected: pulsed laser rapid annealing, pulsed electron beam rapid annealing, ion beam rapid annealing, continuous wave laser rapid annealing, and incoherent broadband light source (e.g., halogen lamp, arc lamp, graphite heating) rapid annealing, etc. The person skilled in the art can select it as desired and is not limited to the examples given.

Further steps of forming NiSi and other conventional processes are included after forming the first semiconductor material layer 105, and the NiSi can be formed by methods commonly used in the art, which are not described herein again.

In order to solve the problem that a Si layer cannot grow on the surface of the NMOS region after source and drain injection in the prior art, HCl is selected to process the surface of the source and drain region of the NMOS region after the Si layer is formed in the PMOS region, a groove is formed on the source and drain of the NMOS region while the Si layer on the PMOS region is removed, and then the Si layer is epitaxially grown again so as to form epitaxial Si layers on the source and drain of the NMOS region and the PMOS region, so that the stress design on the source and drain of the NMOS and PMOS regions is realized, and the performance and the yield of a semiconductor device are improved.

Fig. 3 is a process flow diagram for fabricating a semiconductor device in an embodiment of the invention, which specifically includes the steps of:

step 201, providing a semiconductor substrate, wherein an NMOS region and a PMOS region are formed on the semiconductor substrate, and an NMOS gate structure and a PMOS gate structure are respectively formed on the NMOS region and the PMOS region;

step 202, performing ion implantation on two sides of the NMOS gate structure and the PMOS gate structure;

step 203, forming grooves in the semiconductor substrate on two sides of the PMOS gate structure, and epitaxially growing a stress layer and a second semiconductor material layer in the grooves;

step 204 of performing a pre-cleaning treatment on the surface of the semiconductor substrate to remove the amorphous substance formed in the ion implantation step and simultaneously remove the second semiconductor material layer;

step 205 is to epitaxially grow the first semiconductor material layer on the semiconductor substrate on both sides of the NMOS gate structure and on the stress layer on both sides of the PMOS gate structure.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A method of making a semiconductor device, comprising:

performing source-drain ion implantation on two sides of the NMOS gate structure and the PMOS gate structure;

2. The method of claim 1, wherein the stress layer is a SiGe layer, the first semiconductor material layer is a Si layer, and the second semiconductor material layer is Si.

3. The method of claim 2, further comprising the step of further processing the first layer of semiconductor material to form NiSi after forming the first layer of semiconductor material.

4. The method of claim 1, wherein the first layer of semiconductor material has a height greater than a height of the semiconductor substrate to form a raised first layer of semiconductor material.

5. The method of claim 1, wherein the surface of the semiconductor substrate is pre-cleaned with HCl gas to remove the amorphous material.

6. The method of claim 1, wherein the first layer of semiconductor material is epitaxially grown at a temperature of 500-800 ℃ and a pressure of 1-100 torr.

7. The method of claim 1, wherein the reactant gas for epitaxially growing the first layer of semiconductor material is SiH₄Or SiH₂Cl₂、HCl、B₂H₆Mixed gas of SiH₄Or SiH₂Cl₂、B₂H₆The gas flow rate of HCl is 1sccm-1000 sccm.

8. The method of claim 7, wherein H is selected₂As a reaction carrier gas, the H₂The gas flow rate of (a) is 0.1slm to 50 slm.