CN105097649B - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN105097649B CN105097649B CN201410184867.7A CN201410184867A CN105097649B CN 105097649 B CN105097649 B CN 105097649B CN 201410184867 A CN201410184867 A CN 201410184867A CN 105097649 B CN105097649 B CN 105097649B
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Abstract
A kind of forming method of semiconductor structure, including：There is provided to be formed with Semiconductor substrate, Semiconductor substrate between some grid structures, neighboring gate structures and there is the first opening, grid structure both sides, which are formed with source/drain region, the surface of grid structure, has etching stop layer；First medium layer is formed in the first opening, the surface of first medium layer is less than the top surface of grid structure；Form the size regulation material layer on covering first medium layer and grid structure surface；Material layer is adjusted without mask etching technique etching size, size regulation side wall is formed on the surface of etching stop layer side wall；Form the second dielectric layer that covering grid structure and size adjust side wall；Second dielectric layer is etched, second is formed in second dielectric layer and is open, the second opening exposes size regulation side wall；First medium layer and etching stop layer in the opening of etching first, form the 3rd and are open.Side wall is adjusted by forming size, the process window of photoetching is increased, prevents from bridging the generation of phenomenon.
Description
Technical field
The present invention relates to field of semiconductor fabrication, more particularly to a kind of forming method of semiconductor structure.
Background technology
Metal-oxide-semicondutor (MOS) transistor is the most basic device in semiconductor manufacturing, and it is widely used in
It is different according to doping type when principal carrier and manufacture in various integrated circuits, it is divided into NMOS and PMOS transistor.
Prior art provides a kind of preparation method of MOS transistor, including：Semiconductor substrate is provided, partly led described
Grid structure is formed on body substrate, the grid structure includes gate dielectric layer and the gate electrode on gate dielectric layer；Described
The both sides sidewall surfaces formation offset side wall of grid structure；Using the grid structure and offset side wall as mask, shallow doping is carried out
Ion implanting, forms shallow doped region in the Semiconductor substrate of grid structure both sides；Master is formed on the surface of the offset side wall
Side wall；Using the grid structure and master wall as mask, source and drain ion implanting is carried out, half in grid structure and master wall both sides
Deep doped region is formed in conductor substrate, deep doped region and shallow doped region constitute the source/drain region of MOS transistor；Carry out metal silication
Thing technique, the first metal silicide region is formed on source/drain region surface, in surface gate electrode the second Metal-silicides Contact of formation
Area；Form the first medium layer on the covering Semiconductor substrate and grid structure surface；In the formation photoetching of first medium layer surface
There is the opening of exposure first medium layer in glue-line, the photoresist layer；The first medium layer is etched along opening, exposure is formed
Go out the etched hole on the first metal silicide region surface, full metal is filled in etched hole, metal plug is formed.
But the performance of the MOS transistor of prior art formation still has much room for improvement.
The content of the invention
The problem of present invention is solved is to prevent from bridging in the forming process to form metal plug, improves the property of transistor
Energy.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：Semiconductor lining is provided
Being formed with bottom, the Semiconductor substrate between some grid structures, neighboring gate structures has the first opening, grid structure two
The Semiconductor substrate of source/drain region, the side wall of the grid structure and the first bottom being open is formed with the Semiconductor substrate of side
There is etching stop layer on surface；First medium layer is formed on etching stop layer in the described first opening, described first is situated between
The surface of matter layer is less than the top surface of grid structure；Form the covering first medium layer and grid structure surface and etching
The size regulation material layer of stop-layer part surface；The size regulation material layer is etched using without mask etching technique, in institute
State and size regulation side wall is formed on the surface of etching stop layer side wall, and size regulation side wall is located on first medium layer；
Form the second dielectric layer that the covering etching stop layer, grid structure, size adjust side wall；The second dielectric layer is etched,
Form second in the second dielectric layer to be open, the second opening exposes size regulation side wall；Along the second opening, with the chi
Very little regulation side wall is the first medium layer and etching stop layer in mask, the opening of etching first, forms the 3rd and is open, the described 3rd
Opening exposes source/drain region surface；Fill metal in the second opening and the 3rd opening, form metal plug, metal plug with
Source/drain region is electrically connected.
Optionally, the material of the size regulation side wall and the material of second dielectric layer are differed.
Optionally, when etching the second dielectric layer, second dielectric layer is selected relative to the etching selection that size adjusts side wall
Select than more than or equal to 20:1.
Optionally, the material of the size regulation side wall is silicon nitride, silicon oxynitride or carbonitride of silicium, the second medium
The material of layer is silica, low-k materials or ultralow-k material film.
Optionally, described is plasma etch process without mask etching technique, and the plasma etch process is used
Etching gas be CH3F or CH2F2, etching gas flow is 10-300sccm, and source power is 500-3000W, and bias power is
200-2000W, the pressure of chamber is 10-300mtorr.
Optionally, the size regulation material layer, the thickness of size regulation side wall are less than the 1/2 of the first A/F.
Optionally, the size regulation material layer, the thickness of size regulation side wall are 200~500 angstroms.
Optionally, the grid structure includes the gate dielectric layer and the grid on gate dielectric layer being located in Semiconductor substrate
Electrode.
Optionally, the material of the gate dielectric layer is silica, and the material of the gate electrode is polysilicon.
Optionally, the material of the gate dielectric layer is high-k dielectric material, and the material of the gate electrode is metal.
Optionally, the forming process of etching stop layer and the first medium layer is：The grid structure side wall and
Etching stopping material layer is formed on top surface and the semiconductor substrate surface of the first open bottom；In etching stopping material layer
Upper formation first medium material layer, full first opening of first medium material layer filling；Planarize the first medium material
Layer and etching stopping material layer, using the surface of grid structure as stop-layer, are open in the side wall of the grid structure and first
Etching stop layer is formed on the semiconductor substrate surface of bottom；It is etched back to remove the first medium of the segment thickness in the first opening
Material layer, forms first medium layer on etching stop layer, and the surface of the first medium layer is less than the top table of grid structure
Face.
Optionally, the forming process of the grid structure, etching stop layer and first medium layer is：On a semiconductor substrate
Formed to be formed with some discrete pseudo- grid, the side wall of the pseudo- grid between side wall, adjacent pseudo- grid and there is the first opening；In pseudo- grid
Source/drain region is formed with the Semiconductor substrate of side wall both sides；Remove the side wall；The pseudo- grid side wall and top surface with
And first open bottom semiconductor substrate surface on formed etching stopping material layer；Formed in the etching stopping material layer
First medium material layer, full first opening of first medium material layer filling；Planarize the first medium material layer and quarter
Erosion stops material layer, using the surface of pseudo- grid as stop-layer, the semiconductor lining in the side wall of the pseudo- grid and the first bottom being open
Etching stop layer is formed on basal surface；The pseudo- grid are removed, groove is formed；In bottom portion of groove formation high-K gate dielectric layer；In high K
Metal gate electrode, the full groove of metal gate electrode filling are formed on gate dielectric layer；It is etched back to remove the part in the first opening
The first medium material layer of thickness, forms first medium layer on etching stop layer, and the surface of the first medium layer is less than grid
The top surface of pole structure.
Optionally, the thickness of the first medium material layer for being etched back to remove is the in the first opening after planarization
The 1/3~2/3 of one layer of dielectric material gross thickness.
Optionally, the high-k dielectric material is HfO2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、
SrTiO3Or BaSrTiO, the metal is W, Al, Cu, Ti, Ag, Au, Pt or Ni.
Optionally, the thickness of the etching stopping material layer is 80~400 angstroms.
Optionally, size described in no mask etching adjusts material layer, and while forming size regulation side wall, etching removes the
The etching stop layer of part first medium layer and segment thickness in one opening.
Optionally, the thickness of the etching stop layer of the removal is the 1/2~2/3 of etching stop layer original thickness.
Optionally, the thickness of the etching stop layer of removal is 50~200 angstroms.
Optionally, in addition to：Formed to have in photoresist layer, the photoresist layer in the second dielectric layer and exposed
4th opening of second medium layer surface；The second dielectric layer is etched along the 4th opening, second is formed in second dielectric layer
Opening.
Optionally, the width of the 4th opening is more than the spacing between adjacent size regulation side wall
Compared with prior art, technical scheme has advantages below：
First is formed on the forming method of the semiconductor structure of the present invention, the etching stop layer in the described first opening to be situated between
Matter layer, after the surface of first medium layer is less than the top surface of grid structure, formed the covering first medium layer and
The size regulation material layer of grid structure surface and etching stop layer part surface, then using without mask etching technique etching
The size adjusts material layer, and size regulation side wall is formed on the surface of etching stop layer side wall, and the size is adjusted
Save side wall to be located on first medium layer, by forming size on etching stop layer between grid structure without mask etching technique
The width adjusted between side wall, thus adjacent size regulation side wall can be made small, the width between adjacent size regulation side wall
Degree will not be limited by photoetching process, and the second of side wall is adjusted forming the covering etching stop layer, grid structure, size
Dielectric layer, etches the second dielectric layer, the photoetching and etching technics when formation second is open in the second dielectric layer
Window increases, and method of the invention prevents from bridging the generation of phenomenon while the integrated level of device is improved in addition.
Further, the thickness of the first medium material layer of removal is etched back to for first in the first opening after planarization to be situated between
The 1/3~2/3 of material bed of material gross thickness, in favor of follow-up using the size formed without mask etching technique on first medium layer
Adjust the control of spacing between side wall and adjacent size regulation side wall.
Further, described is plasma etch process without mask etching technique, and the plasma etch process is used
Etching gas be CH3F or CH2F2, etching gas flow is 10-300sccm, and source power is 500-3000W, and bias power is
200-2000W, the pressure of chamber is 10-300mtorr, the size to be formed is adjusted the bottom width and top width of side wall
Gap is smaller, and makes the spacing accuracy between adjacent size regulation side wall 209 higher.
Brief description of the drawings
Fig. 1~Figure 13 is the structural representation of the forming process of semiconductor structure of the embodiment of the present invention.
Embodiment
Prior art is during the metal plug of connection source/drain region is formed, it is necessary to the after first medium layer is formed
The photoresist layer with opening is formed on one dielectric layer, then using the photoresist layer as mask, the first medium layer is etched,
Etched hole is formed in first medium layer, but is improved constantly with the integrated level of device, the distance between neighboring gate structures
Also less and less, this requires the size of the opening formed in photoresist layer also constantly to reduce, and by lithographic equipment and technique
The limitation of condition, when small-sized (being less than 80 nanometers) of the opening formed in photoresist layer, is existed by exposure imaging technique
The opening formed in photoresist layer easily produces the skew of position so that etch the etched hole that first medium layer is formed along opening
Position can produce skew, and the etched hole of formation is in addition to retaining source/drain region surface, and the etched hole can also expose part grid
The surface of pole structure, is filled after metal in etched hole, and the metal plug of formation is not only electrically connected also with the source/drain region of transistor
It can be electrically connected with grid structure, cause bridge joint (bridge) phenomenon of source/drain region and grid structure, influence the performance of transistor.
Therefore, the invention provides a kind of forming method of semiconductor structure, by without mask etching technique in grid knot
The width that formation size is adjusted between side wall, thus adjacent size regulation side wall on etching stop layer between structure can be made
Small, the width between adjacent size regulation side wall will not be limited by photoetching process, thus be increased in etching second dielectric layer
The window of photoetching and etching technics when formation second is open.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.When the embodiment of the present invention is described in detail, for purposes of illustration only, schematic diagram can disobey general ratio
Make partial enlargement, and the schematic diagram is example, and it should not be limited the scope of the invention herein.In addition, in reality
The three-dimensional space of length, width and depth should be included in making.
Fig. 1~Figure 13 is the structural representation of the forming process of semiconductor structure of the embodiment of the present invention.
With reference to Fig. 1 there is provided Semiconductor substrate 200, some discrete pseudo- grid 201 are formed in the Semiconductor substrate 200,
Being formed with the side wall of the pseudo- grid 201 between side wall, adjacent pseudo- grid 201 has the first opening 203.
The material of the Semiconductor substrate 200 is silicon (Si), germanium (Ge) or SiGe (GeSi), carborundum (SiC)；Also may be used
To be silicon-on-insulator (SOI), germanium on insulator (GOI)；Or can also be for other materials, III-V such as GaAs
Compounds of group.The Semiconductor substrate 200 can also inject certain Doped ions to change electrical parameter according to design requirement.
Fleet plough groove isolation structure (not shown) is also formed with the Semiconductor substrate 200, the fleet plough groove isolation structure is used
In isolating different transistors, prevent from being electrically connected between different crystal pipe, the material of the fleet plough groove isolation structure can be
Silica, silicon nitride, silicon oxynitride one or more therein.
The pseudo- grid 201 subsequently form recessed as the sacrifice layer for being subsequently formed metal gate electrode after pseudo- grid 201 are removed
Groove, then filling metal forms metal gate electrode in a groove.
The material of the pseudo- grid 201 is polysilicon, and the forming process of pseudo- grid is：Formed in the Semiconductor substrate 200
Polysilicon material layer；Patterned photoresist layer is formed on the polysilicon material layer；With the patterned photoresist layer
The polysilicon material layer described in mask etching, forms some discrete pseudo- grid 201.
Silicon oxide layer can also be formed between pseudo- grid 201 and Semiconductor substrate 200.
Side wall is also formed with the both sides side wall of the pseudo- grid 201, the side wall includes offset side wall 202 and is disposed offset from
Master wall 220 on side wall 202.
The material of the offset side wall 202 is silica, and the formation process of offset side wall 202 is thermal oxide, inclined being formed
Move after side wall 202, in addition to：It is mask with the pseudo- grid 201 and offset side wall 202, the is carried out to the Semiconductor substrate 200
One ion implanting, shallow doped region is formed in the Semiconductor substrate of pseudo- grid 201 and offset side wall 202 both sides.
After shallow doped region is formed, master wall 220, the master wall 220 are formed on the surface of the offset side wall 202
Forming process be：Form the covering pseudo- grid 201, offset side wall 202 and the spacer material on the surface of Semiconductor substrate 200 layer；
Without spacer material layer described in mask etching, master wall 220 is formed on the surface of offset side wall 202.
The master wall 220 can be single or multiple lift stacked structure.
In the present embodiment, the master wall 220 is the silicon nitride of individual layer.
After master wall 220 is formed, in addition to：It is mask with the master wall 220 and pseudo- grid 201, carries out the second ion
Injection, forms deep doped region in the Semiconductor substrate 200 of pseudo- grid 201 and the both sides of master wall 220, the deep doped region and shallow mixes
Miscellaneous area constitutes the source/drain region of transistor.
First ion implanting is identical with the type for the foreign ion that the second ion implanting is injected, the foreign ion bag
N-type impurity ion and p type impurity ion are included, the N-type impurity ion is phosphonium ion, arsenic ion or antimony ion, the p type impurity
Ion is boron ion, gallium ion or indium ion.The type of first ion implanting and the second ion implanting implanting impurity ion
Selected according to the type of transistor to be formed, when transistor to be formed be N-type transistor when, the first ion implanting and
The foreign ion of second ion implanting is the foreign ion of N-type, when transistor to be formed is P-type transistor, the first ion
The foreign ion of injection and the second ion implanting is the foreign ion of p-type.
With reference to Fig. 2, the side wall is removed, in the side wall and top surface of the pseudo- grid 201 and the first 203 bottoms of opening
The surface of Semiconductor substrate 200 on form etching stopping material layer 215.
In the present embodiment, the master wall 220 (referring to Fig. 1) in the side wall is removed, then in the pseudo- grid 201, skew
Etching stopping material layer 215 is formed on the surface of side wall 202 and Semiconductor substrate 200.
Remove the master wall 220 and use wet etching, the etching solution that wet etching is used is removing master for concentrated phosphoric acid
During side wall 220, the offset side wall 202 is as the stop-layer etched, to protect the side wall of pseudo- grid 201.
In the present embodiment, the purpose for removing master wall 220 is so that the space between adjacent pseudo- grid 201 increases, after being easy to
Continue and size regulation side wall is formed on the etching stop layer between adjacent pseudo- grid 201.
In other embodiments of the invention, when removing the master wall 220, the skew side can also be removed simultaneously
Wall 202.
The etching stopping material layer 215 be the silicon nitride with tensile stress or the silicon nitride with compression stress,
The etching stopping material layer 215 is subsequently formed etching stop layer, the stopping when etching stop layer of formation serves not only as etching
Layer, the etching stop layer can also apply tension or compression to the channel region of transistor, to improve transistor channel region
Carrier mobility, specifically, when transistor to be formed be N-type transistor when, the etching stopping material layer 215
For the silicon nitride with tensile stress, when transistor to be formed is the transistor of p-type, the etching stopping material layer 215
For the silicon nitride with compression stress.
The thickness of the etching stopping material layer 215 is 80~400 angstroms, and the quarter is formed using chemical vapor deposition method
Erosion stops material layer 215.
With reference to Fig. 3, first medium material layer 205, first medium material layer are formed in the etching stopping material layer 215
Full first opening of 205 fillings；The first medium material layer 205 and etching stopping material layer 215 are planarized, with pseudo- grid 201
Surface is stop-layer, and etching is formed on the surface of Semiconductor substrate 200 of the side wall of the pseudo- grid 201 and the first bottom being open
Stop-layer 204.
The first medium material layer and etching stopping material layer are planarized using chemical mechanical milling tech.
The material of the first medium material layer 205 is silica or other suitable materials.
With reference to Fig. 4, the pseudo- grid 201 (referring to Fig. 3) are removed, groove is formed；In bottom portion of groove formation high-K gate dielectric layer；
Metal gate electrode 206, the full groove of the filling of metal gate electrode 206 are formed on high-K gate dielectric layer.
Remove the pseudo- grid 201 and use wet etching, the solution that wet etching is used is KOH or TMAH (tetramethyl hydrogen-oxygen
Change ammonium) or NH3.H2O。
In the embodiment of the present invention, the high-K gate dielectric layer and metal gate electrode 206 constitute grid structure, grid structure
Gate dielectric layer is high-k dielectric material, and the material of the metal gate electrode 206 is metal, and specific high-k dielectric material can be
HfO2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3Or BaSrTiO etc., the metal can be
W, Al, Cu, Ti, Ag, Au, Pt or Ni etc..
In other embodiments of the invention, the material of the gate dielectric layer of grid structure can be silica, gate electrode
Material can be polysilicon, and the forming process of corresponding grid structure, etching stop layer and first medium layer is：In the grid
Etching stopping material layer is formed on the side wall and top surface of structure and the semiconductor substrate surface of the first open bottom；Carving
Erosion stops forming first medium material layer in material layer, full first opening of first medium material layer filling；Planarization is described
First medium material layer and etching stopping material layer, using the surface of grid structure as stop-layer, in the side wall of the grid structure
Etching stop layer is formed with the semiconductor substrate surface of the bottom of the first opening；Subsequently through being etched back to, the opening of removal first is interior
Segment thickness first medium material layer, first medium layer, the surface of first medium layer are formed on etching stop layer
Less than the top surface of grid structure.It should be noted that when planarizing the first medium material layer, described can also etch
The surface of stop-layer is stop-layer.
With reference to Fig. 5, it is etched back to remove the first medium material layer 205 of the first segment thickness being open in 203 (referring to Fig. 2)
(referring to Fig. 4), forms first medium layer 207 on etching stop layer 204, and the surface of the first medium layer 207 is less than grid
The top surface of structure.
Be etched back to the first medium material layer 205 and use wet etching solution, the etching that wet etching is used easily for
Hydrofluoric acid solution.
The thickness of the first medium material layer 205 for being etched back to remove is situated between for first in the first opening after planarization
The 1/3~2/3 of the gross thickness of the material bed of material 205, is formed in favor of follow-up using without mask etching technique on first medium layer 207
Size regulation side wall and adjacent size regulation side wall between spacing control.
With reference to Fig. 6, the covering first medium layer 207 and grid structure surface and the part of etching stop layer 204 are formed
The size regulation material layer 208 on surface.
The size regulation material layer 208 is subsequently used for forming size regulation side wall.
The material of the size regulation material layer 208 and first medium layer 207 and the material for the second dielectric layer being subsequently formed
Material is differed, and the material of the size regulation material layer 208 is silicon nitride, silicon oxynitride or carbonitride of silicium.In the present embodiment, institute
The material for stating size regulation material layer 208 is carbonitride of silicium.
The thickness of the size regulation material layer 208 is less than the 1/2 of the first 203 (referring to Fig. 5) width W of opening.Specific
Embodiment in, the thickness of size regulation material layer 208 can be 200~500 angstroms.
Form the size regulation material layer 208 and use chemical vapor deposition method, including low-pressure chemical vapor deposition work
Skill (LPCVD), high-density plasma enhanced chemical vapor deposition processes (PECVD) or atom layer deposition process (ALD).
In the present embodiment, form the size regulation material layer 208 and use atom layer deposition process, adjust the size to be formed
Saving material layer 208 has more accurate thickness and the pattern on surface.
With reference to Fig. 7, size regulation material layer 208 (referring to Fig. 6) described in no mask etching, in the etching stop layer 204
Size regulation side wall 209 is formed on the surface of side wall, and size regulation side wall 209 is located on first medium layer 207.
Described is plasma etch process, the etching gas that the plasma etch process is used without mask etching technique
Body is CH3F or CH2F2, etching gas flow is 10-300sccm, and source power is 500-3000W, and bias power is 200-
2000W, the pressure of chamber is 10-300mtorr, the size to be formed is adjusted the bottom width of side wall 209 and the difference of top width
Away from smaller, and make the space D precision between adjacent size regulation side wall 209 higher.
Size regulation side wall 209 as subsequent etching first be open in first medium layer and second dielectric layer cover
Space D between film, adjacent size regulation side wall 209 defines the size of the 3rd opening formed between subsequent gate structure,
Namely define the size of the metal plug formed in the 3rd opening.
In the present embodiment, material layer 208 (referring to Fig. 6) is adjusted by depositing operation formation size, then without mask etching
The size regulation material layer formation size regulation side wall 209, thus the space D that adjacent size is adjusted between side wall 209 will not
Limited by photoetching and etching technics, the space D between adjacent size regulation side wall 209 can be made very small, and be conducive to carrying
The integrated level of high device.In the particular embodiment, the space D between adjacent size regulation side wall 209 can be received for 10~80
Rice.
In other embodiments of the invention, Fig. 8 is refer to, size described in no mask etching adjusts material layer, forms chi
After very little regulation side wall 209, it is the first medium layer in mask continuation the first opening of etching that side wall 209 can also be adjusted with size
207 and the etching stop layer 204 of segment thickness, the etching stop layer 204 of segment thickness is removed by etching, subsequently in shape
Be mask with size regulation side wall 209 in metal plug technique into after second dielectric layer, can easily in cut through the
Remaining etching stop layer 204 in one opening, to expose source/drain region surface.
The thickness of the etching stop layer 204 of the removal is the 1/2~2/3 of the original thickness of etching stop layer 204, specific
Embodiment in, the thickness of the etching stop layer 204 of removal is 50~200 angstroms
With reference to Fig. 7 and Fig. 9 is referred to, form the covering etching stop layer 204, grid structure, size and adjust side wall 209
Second dielectric layer 210.
The material of the material of the second dielectric layer 210 and size regulation side wall 209 is differed, and is subsequently etching described the
During second medium layer 210, second dielectric layer 210 adjusts the etching selection selection of side wall 209 than being more than or equal to 20 relative to size:1.
The material of the second dielectric layer 210 can be silica, low-k materials or ultralow-k material film, low-k materials it is relative
Dielectric constant is less than 3.9, and the relative dielectric constant of ultralow-k material film is less than 2.8.In the embodiment of the present invention, the second dielectric layer
210 material is silica.
With reference to Figure 10, being formed in the second dielectric layer 210 in photoresist layer 211, the photoresist layer 211 has cruelly
Expose the 4th opening 212 on the surface of second dielectric layer 210, the 4th opening 212 is located at the top of size regulation side wall 209.
The photoresist layer 211 is existed as mask during subsequent etching second dielectric layer 210 by exposed and developed technique
The 4th opening 212 is formed in photoresist layer 211.
In the embodiment of the present invention, between being adjusted due to size between the presence of side wall 209, adjacent size regulation side wall 209
Size away from the metal plug formed in the width for determining the be subsequently formed the 3rd opening and the 3rd opening, the 3rd opening
The size of metal plug formed in width and the 3rd opening will not by the 4th opening 212 widths affect, thus this hair
In bright embodiment, the width of the 4th opening 212 is more than the spacing between adjacent size regulation side wall 209, so as to increase
Photoresist layer 211 is exposed and developing process photoetching window.
It is mask with the photoresist layer 211 with reference to Figure 11, along the 4th 212 (referring to Figure 10) of opening etching described second
Dielectric layer 210, forms the second opening 213 in second dielectric layer 210, and the second opening 213 exposes size regulation side wall 209；
It is mask with size regulation side wall 209 along the second opening 213, first medium layer 207 and etching in the opening of etching first
Stop-layer 204, forms the 3rd and is open, and the 3rd opening exposes source/drain region surface.
Etch the second dielectric layer 210 and first medium layer 207 uses anisotropic dry etching, the etching of use
Gas is CF4、C2F6、C3F8、C4F8In one or more.
Etch the etching stop layer 204 and use anisotropic dry etching or sputtering technology, anisotropic dry method
The gas used is etched for CHF3、CH2F2In one or more, the gas that sputtering technology is used is Ar.
In other embodiments of the invention, when being filled with second dielectric layer between size regulation side wall 209, then with institute
It is mask to state size regulation side wall 209, etches second dielectric layer and etching stop layer 204 in the first opening, forms the 3rd and open
Mouthful.
In other embodiments of the invention, Figure 12 is refer to, when the position of the 4th opening formed in photoresist layer 211
It can also be mask with the photoresist layer 211 when producing skew, the 4th opening etching described second of skew is produced along position
Dielectric layer 210, forms the second opening 213, the second opening 213 exposes portion size regulation side wall 209 surface, then again with institute
It is the first medium layer 207 and etching stop layer 204 in mask, the opening of etching first to state size regulation side wall 209, forms the 3rd
Opening, the 3rd opening exposes source/drain region surface, and size adjusts the presence of side wall 209, although the second opening of formation
213 have the skew of position, but the position of the 3rd opening will not be offset, and the 3rd opening can accurately expose source/drain region
Surface, subsequently when the 3rd opening and the second opening 213 form metal plug, metal plug can be electrically connected with source-drain area well
Connect.
With reference to Figure 11 and Figure 13 is referred to, metal is filled in the second opening 213 and the 3rd opening, metal plug 214 is formed,
Metal plug 214 is electrically connected with source/drain region.
The material of the metal plug 214 can be tungsten, aluminium or copper, can also be other suitable conductive materials, described
The formation process of metal plug 214 is sputtering or electroplates.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (20)
1. a kind of forming method of semiconductor structure, it is characterised in that including：
Semiconductor substrate is provided, being formed with the Semiconductor substrate between some grid structures, neighboring gate structures has the
Source/drain region is formed with one opening, the Semiconductor substrate of grid structure both sides, what the side wall of the grid structure and first were open
There is etching stop layer on the semiconductor substrate surface of bottom；
First medium layer is formed on etching stop layer in the described first opening, the surface of the first medium layer is less than grid
The top surface of structure；
Form the size regulation material of the covering first medium layer and grid structure surface and etching stop layer part surface
Layer；
The size regulation material layer is etched using without mask etching technique, is formed on the surface of etching stop layer side wall
Size adjusts side wall, and size regulation side wall is located on first medium layer；
Form the second dielectric layer that the covering etching stop layer, grid structure, size adjust side wall；
The second dielectric layer is etched, second is formed in the second dielectric layer and is open, the second opening exposes size regulation
Side wall；
Along the second opening, side wall is adjusted as mask using the size, first medium layer and etching stopping in the opening of etching first
Layer, forms the 3rd and is open, and the 3rd opening exposes source/drain region surface；
Metal is filled in the second opening and the 3rd opening, metal plug is formed, metal plug is electrically connected with source/drain region.
2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the size adjusts the material of side wall
Differed with the material of second dielectric layer.
3. the forming method of semiconductor structure as claimed in claim 2, it is characterised in that when etching the second dielectric layer,
Second dielectric layer adjusts the etching selection selection of side wall than being more than or equal to 20 relative to size:1.
4. the forming method of semiconductor structure as claimed in claim 2, it is characterised in that the size adjusts the material of side wall
For silicon nitride, silicon oxynitride or carbonitride of silicium, the material of the second dielectric layer is silica, low-k materials or ultralow-k material film.
5. the forming method of the semiconductor structure as described in claim 1 or 4, it is characterised in that described without mask etching technique
For plasma etch process, the etching gas that the plasma etch process is used is CH3F or CH2F2, etching gas stream
Measure as 10-300sccm, source power is 500-3000W, bias power is 200-2000W, and the pressure of chamber is 10-300mtorr.
6. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the size regulation material layer, chi
The thickness of very little regulation side wall is less than the 1/2 of the first A/F.
7. the forming method of semiconductor structure as claimed in claim 6, it is characterised in that the size regulation material layer, chi
The thickness of very little regulation side wall is 200~500 angstroms.
8. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the grid structure includes being located at half
Gate dielectric layer on conductor substrate and the gate electrode on gate dielectric layer.
9. the forming method of semiconductor structure as claimed in claim 8, it is characterised in that the material of the gate dielectric layer is oxygen
SiClx, the material of the gate electrode is polysilicon.
10. the forming method of semiconductor structure as claimed in claim 8, it is characterised in that the material of the gate dielectric layer is
High-k dielectric material, the material of the gate electrode is metal.
11. the forming method of semiconductor structure as claimed in claim 9, it is characterised in that the etching stop layer and first
The forming process of dielectric layer is：In the side wall and top surface and the Semiconductor substrate of the first open bottom of the grid structure
Etching stopping material layer is formed on surface；First medium material layer, the first medium material are formed in etching stopping material layer
Full first opening of bed of material filling；The first medium material layer and etching stopping material layer are planarized, with the surface of grid structure
For stop-layer, etching stopping is formed on the semiconductor substrate surface of the side wall of the grid structure and the first bottom being open
Layer；It is etched back to remove the first medium material layer of the segment thickness in the first opening, first medium is formed on etching stop layer
Layer, the surface of the first medium layer is less than the top surface of grid structure.
12. the forming method of semiconductor structure as claimed in claim 10, it is characterised in that the grid structure, etch-stop
Only the forming process of layer and first medium layer is：Some discrete pseudo- grid, the side wall of the pseudo- grid are formed on a semiconductor substrate
On be formed between side wall, adjacent pseudo- grid have first opening；Source/drain is formed in the Semiconductor substrate of pseudo- grid and side wall both sides
Area；Remove the side wall；On the side wall and top surface and the semiconductor substrate surface of the first open bottom of the pseudo- grid
Form etching stopping material layer；First medium material layer, the first medium material are formed in the etching stopping material layer
Full first opening of layer filling；The first medium material layer and etching stopping material layer are planarized, using the surface of pseudo- grid as stopping
Layer, etching stop layer is formed on the semiconductor substrate surface of the side wall of the pseudo- grid and the first bottom being open；Remove described
Pseudo- grid, form groove；In bottom portion of groove formation high-K gate dielectric layer；Metal gate electrode, the gold are formed on high-K gate dielectric layer
Belong to the full groove of gate electrode filling；It is etched back to remove the first medium material layer of the segment thickness in the first opening, in etching stopping
First medium layer is formed on layer, the surface of the first medium layer is less than the top surface of grid structure.
13. the forming method of the semiconductor structure as described in claim 11 or 12, it is characterised in that described to be etched back to what is removed
The thickness of first medium material layer is 1/3~2/3 of the first medium material layer gross thickness in the first opening after planarization.
14. the forming method of semiconductor structure as claimed in claim 10, it is characterised in that the high-k dielectric material is
HfO2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3Or BaSrTiO, the metal be W, Al,
Cu, Ti, Ag, Au, Pt or Ni.
15. the forming method of the semiconductor structure as described in claim 11 or 12, it is characterised in that the etching stopping material
The thickness of layer is 80~400 angstroms.
16. the forming method of the semiconductor structure as described in claim 11 or 12, it is characterised in that without chi described in mask etching
Very little regulation material layer, while forming size regulation side wall, etching removes part first medium layer and part in the first opening
The etching stop layer of thickness.
17. the forming method of semiconductor structure as claimed in claim 16, it is characterised in that the etching stop layer of the removal
Thickness be etching stop layer original thickness 1/2~2/3.
18. the forming method of semiconductor structure as claimed in claim 17, it is characterised in that the thickness of the etching stop layer of removal
Spend for 50~200 angstroms.
19. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that also include：In the second medium
Being formed on layer has the 4th opening for exposing second medium layer surface in photoresist layer, the photoresist layer；Along the 4th opening
The second dielectric layer is etched, second is formed in second dielectric layer and is open.
20. the forming method of semiconductor structure as claimed in claim 19, it is characterised in that the width of the 4th opening is big
The spacing between side wall is adjusted in adjacent size.
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| US10090249B2 (en) | 2015-12-17 | 2018-10-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and manufacturing method thereof |
| US9716154B2 (en) * | 2015-12-17 | 2017-07-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure having a gas-filled gap |
| CN107706233B (en) * | 2016-08-08 | 2022-07-12 | 联华电子股份有限公司 | Semiconductor device and method of making the same |
| CN110299320B (en) * | 2018-03-21 | 2023-11-21 | 联华电子股份有限公司 | Semiconductor device and manufacturing method thereof |
| CN110729183B (en) * | 2018-07-16 | 2022-08-23 | 中芯国际集成电路制造(上海)有限公司 | Metal gate forming method and semiconductor device |
| CN111863709B (en) * | 2019-04-29 | 2024-03-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112951720B (en) * | 2019-11-26 | 2024-03-22 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure and semiconductor device |
| CN113809007B (en) * | 2020-06-11 | 2024-03-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN114256136B (en) * | 2020-09-22 | 2024-03-26 | 长鑫存储技术有限公司 | Contact window structure, metal plug, forming method of metal plug and semiconductor structure |
| CN114361107B (en) * | 2022-03-10 | 2022-06-21 | 合肥晶合集成电路股份有限公司 | Interconnection structure and preparation method thereof |
| CN116960064B (en) * | 2023-09-20 | 2024-08-27 | 深圳市新凯来技术有限公司 | Method for preparing semiconductor structure |
| CN118263191B (en) * | 2024-05-30 | 2024-08-23 | 杭州积海半导体有限公司 | Semiconductor device and method for manufacturing the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5084416A (en) * | 1989-02-17 | 1992-01-28 | Matsushita Electronics Corporation | Method of forming a low resistance contact by forming a contact hole within a recess |
| CN102412187A (en) * | 2011-04-29 | 2012-04-11 | 上海华力微电子有限公司 | Side wall hard mask contact hole/through hole etching technology |
| CN102456613A (en) * | 2010-10-29 | 2012-05-16 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| GB9928285D0 (en) * | 1999-11-30 | 2000-01-26 | Koninkl Philips Electronics Nv | Manufacture of trench-gate semiconductor devices |
-
2014
- 2014-05-04 CN CN201410184867.7A patent/CN105097649B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5084416A (en) * | 1989-02-17 | 1992-01-28 | Matsushita Electronics Corporation | Method of forming a low resistance contact by forming a contact hole within a recess |
| CN102456613A (en) * | 2010-10-29 | 2012-05-16 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN102412187A (en) * | 2011-04-29 | 2012-04-11 | 上海华力微电子有限公司 | Side wall hard mask contact hole/through hole etching technology |
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