CN105097524B - The forming method of MOS transistor and the forming method of CMOS transistor - Google Patents
The forming method of MOS transistor and the forming method of CMOS transistor Download PDFInfo
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Abstract
A kind of forming method of MOS transistor and the forming method of CMOS transistor.Wherein, the forming method of the MOS transistor includes：Semiconductor substrate is provided, there is dummy grid in the semiconductor substrate；Source region and drain region are respectively formed in the semiconductor substrate of the dummy grid down either side；Interlayer dielectric layer is formed on the semiconductor substrate, and the upper surface of the interlayer dielectric layer is flushed with the dummy grid upper surface；The dummy grid is removed using pulsed plasma etching technics and forms opening；Metal gates are formed using the metal material filling opening.It is improved using the MOS transistor performance that the forming method of the MOS transistor is formed.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to the forming methods and CMOS transistor of a kind of MOS transistor
Forming method.
Background technique
With the continuous development of semiconductor fabrication process, the characteristic size of the semiconductor devices in integrated circuit
(Critical Dimension, CD) is smaller and smaller, in order to solve small size device bring a series of problems, high dielectric constant
(k) technology that the gate dielectric layer of material and metal gates (metal gate) combine is introduced into the manufacture of MOS transistor
Cheng Zhong.
To avoid the metal material of metal gates from impacting the other structures of MOS transistor, the metal gates with
The gate stack structure of high-k gate dielectric layer generallys use rear grid technique (gate-last) production.In the process, to be formed
Gate location be initially formed the dummy grid being made of materials such as polysilicons, and after forming source-drain area, the puppet can be removed
Grid simultaneously forms gate openings in the position of dummy grid, and then fills metal gates in the gate openings.Due to metal
Grid is made again after the completion of source-drain area injects, this is reduced the quantity of subsequent process steps, avoids metal
Material is unsuitable for the problem of carrying out high-temperature process.
However, the forming method of existing MOS transistor, during removing dummy grid, what is generallyd use is continuous wave
(continuous wave, CW) plasma etch process.But continuous wave plasma etch process is removing width not
With dummy grid when, will form the different opening of depth.
In a kind of situation, as shown in Figure 1, providing semiconductor base 100, semiconductor base 100 can specifically include substrate
With the multilayered structures such as interlayer dielectric layer.Dummy grid (not shown), and the width of each dummy grid are formed on semiconductor base 100
It is different.The dummy grid is removed using continuous wave plasma etch process, to form opening 101 and opening 102.Opening
102 width is greater than opening 101, and the width for representing the dummy grid originally in opening 102, which is greater than to be located at originally, to be open in 101
Dummy grid width.It will be noted from fig. 1 that the depth of opening 102 is greater than the depth of opening 101, i.e., described continuous wave etc.
Plasma etching technique is larger to the etch rate of the biggish dummy grid of width.
In another case, semiconductor base 200 can specifically include lining as shown in Fig. 2, providing semiconductor base 200
The multilayered structures such as bottom and interlayer dielectric layer.Dummy grid (not shown), and the width of each dummy grid are formed on semiconductor base 200
Degree is different.The dummy grid is removed using continuous wave plasma etch process, to form opening 201 and opening 202.Opening
202 width is greater than opening 201, and the width for representing the dummy grid originally in opening 202, which is greater than to be located at originally, to be open in 201
Dummy grid width.From fig. 2 it can be seen that the depth of opening 202 is less than the depth of opening 201, i.e., described continuous wave etc.
Plasma etching technique is larger to the etch rate of the lesser dummy grid of width.
Due to will form after the dummy grid of the forming method removal different in width of existing MOS transistor, depth is different to be opened
Mouthful, cause the threshold voltage of finally formed different MOS transistors that difference occurs, declines the performance of semiconductor devices.Equally
The problem of exist in the forming process of CMOS transistor.
For this reason, it may be necessary to a kind of forming method of new MOS transistor and the forming method of CMOS transistor, to avoid going
Except different in width dummy grid when form the different opening of depth.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of MOS transistor and the forming method of CMOS transistor,
It is identical with each opening depth for guaranteeing that removal is formed after dummy grid, to guarantee that the threshold voltage of each MOS transistor is identical, mention
The performance of high MOS transistor and CMOS transistor.
To solve the above problems, the present invention provides a kind of forming method of MOS transistor, including：
Semiconductor substrate is provided, there is dummy grid in the semiconductor substrate；
Source region and drain region are respectively formed in the semiconductor substrate of the dummy grid down either side；
Interlayer dielectric layer is formed on the semiconductor substrate, on the upper surface of the interlayer dielectric layer and the dummy grid
Surface flushes；
The dummy grid is removed using pulsed plasma etching technics and forms opening；
Metal gates are formed using the metal material filling opening.
Optionally, the pulsed plasma etching technics is lock-out pulse plasma etch process, the synchronous arteries and veins
The gas for rushing plasma etch process use includes Ar and HBr.
Optionally, the pressure range that the lock-out pulse plasma etch process uses for 25mTorr~75mTorr,
The power bracket used for 1500w~2500w, the bias voltage ranges used for 50V~150V, the pulse frequency that uses for
2.5KHz~7.5KHz.
Optionally, the gas that the lock-out pulse plasma etch process uses further includes O2, and O2Range of flow
For 5sccm~15sccm.
Optionally, after lock-out pulse plasma etch process, the forming method further includes：To it is described be open into
Horizontal synchronizing pulse plasma repair process, the gas that the lock-out pulse plasma repair process uses includes CF4。
Optionally, the pressure range that the lock-out pulse plasma repair process uses for 25mTorr~75mTorr,
The power bracket used for 150w~450w, the bias voltage ranges used for 50V~150V, the pulse frequency that uses for
2.5KHz~7.5KHz.
Optionally, after the lock-out pulse plasma repair process, the forming method further includes：It opens described
Mouth carries out nitridation repair process, the N that the nitridation repair process uses2Range of flow is 50sccm~150sccm, the nitridation
The time of repair process is 50s~150s.
Optionally, before carrying out the lock-out pulse plasma etch process, the forming method further includes：
It forms hard mask layer and covers the dummy grid and the interlayer dielectric layer；
It forms photoresist layer and covers the hard mask layer；
Removal is located at the photoresist layer and the hard mask layer on dummy grid；
Remove the remaining photoresist layer.
To solve the above problems, the present invention also provides a kind of forming methods of CMOS transistor, including：
Semiconductor substrate is provided, the semiconductor substrate has first area and second area, has on the first area
There are the first metal gates, there is dummy grid on the second area；
The first source region and the first leakage are respectively formed in the semiconductor substrate of the first metal gates down either side
Area；
The second source region and the second drain region are formed in the semiconductor substrate of the dummy grid down either side；
Interlayer dielectric layer is formed on the semiconductor substrate, on the upper surface of the interlayer dielectric layer and the dummy grid
Surface flushes；
The dummy grid is removed using pulsed plasma etching technics and forms opening；
The opening is filled using metal material and forms the second metal gates.
Optionally, the pulsed plasma etching technics is lock-out pulse plasma etch process, the synchronous arteries and veins
The gas for rushing plasma etch process use includes Ar and HBr.
Optionally, the gas that the lock-out pulse plasma etch process uses further includes O2, and O2Range of flow
For 5sccm~15sccm.
Optionally, after lock-out pulse plasma etch process, the forming method further includes：To it is described be open into
Horizontal synchronizing pulse plasma repair process, the gas that the lock-out pulse plasma repair process uses includes CF4。
Optionally, after the lock-out pulse plasma repair process, the forming method further includes：It opens described
Mouth carries out nitridation repair process, the N that the nitridation repair process uses2Range of flow is 50sccm~150sccm, the nitridation
The time of repair process is 50s~150s.
Optionally, before carrying out the lock-out pulse plasma etch process, the forming method further includes：
It forms hard mask layer and covers the dummy grid and the interlayer dielectric layer；
It forms photoresist layer and covers hard mask layer；
Removal is located at the photoresist layer and the hard mask layer on the dummy grid；
Remove the remaining photoresist layer.
Optionally, the first area is NMOS transistor region and the second area is PMOS transistor region, or
First area described in person is PMOS transistor region and the second area is NMOS transistor region.
Compared with prior art, technical solution of the present invention has the following advantages that：
In technical solution of the present invention, opening is formed using pulsed plasma etching technics removal dummy grid, due to arteries and veins
Rushing plasma is etched by certain frequency, has of short duration time out after etching every time, in this time out,
Etch products can be uniformly dispersed, and provide identical environment for the etching of next frequency, this etching and the process suspended are continuous
Ground repeats, to make the pulsed plasma etching technics no matter to the dummy grid of which kind of width etching speed all having the same
Rate, to make to be formed by, each opening depth is identical, guarantees the threshold value electricity of finally formed MOS transistor or CMOS transistor
Press equal, the performance of raising MOS transistor and CMOS transistor.
Further, dummy grid, the same toning of lock-out pulse plasma are removed using lock-out pulse plasma etch process
Source power and the equal generation of bias power are saved, and the electron temperature in lock-out pulse plasma is lower, to other structures
Damaging action is small, to further increase the performance of MOS transistor and CMOS transistor.
Further, hard mask layer and photoresist layer are formed on dummy grid, are removing whole photoresist layers and then use
Pulsed plasma etching technics removes dummy grid, thus prevent action of plasma from generating pollutant in photoresist layer, thus
Carry out the removal of dummy grid in cleaner environment.
Detailed description of the invention
Fig. 1 is a kind of open condition schematic diagram that the forming method of existing MOS transistor is formed；
Fig. 2 is another open condition schematic diagram that the forming method of existing MOS transistor is formed；
Fig. 3 to Fig. 7 is each step counter structure signal of forming method of MOS transistor provided by the embodiment of the present invention
Figure；
Fig. 8 to Figure 12 is each step counter structure signal of forming method of CMOS transistor provided by the embodiment of the present invention
Figure.
Specific embodiment
As described in background, existing method removes dummy grid using continuous wave plasma etch process, due to even
Continuous wave plasma has different etch rates to the dummy grid of different in width, therefore, causes the opening depth to be formed different,
Occur that the removal of some position dummy grids is not clean, the structure below some local dummy grids is etched the various problems such as damage.
For this purpose, the present invention proposes, opening is formed using pulsed plasma etching technics removal dummy grid, due to pulse etc.
Gas ions are etched by certain frequency, have of short duration time out after etching every time, in this time out, etching
Product can be uniformly dispersed, and provide identical environment for the etching of next frequency, to guarantee that the opening to be formed is having the same
Depth.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
The embodiment of the present invention provides a kind of forming method of MOS transistor, please refers to Fig. 3 to Fig. 7.
Referring to FIG. 3, providing semiconductor substrate 300, there is dummy grid 302 in semiconductor substrate 300.Semiconductor substrate
Also there is high-K dielectric layer 301 between 300 and dummy grid 302.The two sides of dummy grid 302 and high-K dielectric layer 301 are simultaneously by side wall
303 covering, and 300 upper surface of semiconductor substrate and the side of side wall 303 be etched stop-layer 310 covering.Etching stop layer
310 upper surfaces are flushed with 302 upper surface of dummy grid.
In the present embodiment, can also have cap layer (not shown) and interface between high-K dielectric layer 301 and dummy grid 302
Layer (not shown), the boundary layer are located above the cap layer.Cap layer can prevent the metal gates being subsequently formed from spreading
To high-K dielectric layer 301, and boundary layer can reinforce the connection function of cap layer with the metal gates being subsequently formed.
In the present embodiment, semiconductor substrate 300 can be：Elemental semiconductor, including silicon crystal or germanium crystal, insulate edge body
Upper silicon (Silicon On Insulator, SOI) structure or silicon upper epitaxial layer structure；Compound semiconductor, including silicon carbide, arsenic
Change gallium, gallium phosphide, indium phosphide, indium arsenide or dysprosium indium；Alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs,
GaInAs, GaInP, GaInAsP or their combination.
In the present embodiment, the material of dummy grid 302 can be polysilicon, silicon nitride or amorphous carbon etc..High-K dielectric layer
301 material can be HfO2、HFSiO、HfON、La2O3、LaAlO、Al2O3、ZrO2、ZrSiO、TiO2Or Y2O3.Cap layer
Material can be titanium nitride, and the material of boundary layer can be silica.Etching stop layer 310 can provide answers masterpiece accordingly
With, and the stop layer as etch step, to prevent above-mentioned source region and drain region by over etching, material can for silicon nitride or
Carbonitride of silicium etc..
After forming the dummy grid 302, the present embodiment further includes the semiconductor substrate in 302 down either side of dummy grid
It is respectively formed source region (not shown) and drain region (not shown) in 300, specifically the source can be formed by the methods of ion implanting
Area and the drain region.
In the present embodiment, semiconductor substrate 300 can also include it other than being formed with the source region and the drain region
Its doped region, for example, p-type trap or N-shaped trap.Doped region can adulterate the p-type dopant of such as boron or BF2, or such as
The n-type dopant of phosphorus or arsenic.
With continued reference to FIG. 3, on a semiconductor substrate formed interlayer dielectric layer 320, the upper surface of interlayer dielectric layer 320 with
302 upper surface of dummy grid flushes.
In the present embodiment, the material of interlayer dielectric layer 320 can be silica, boron-phosphorosilicate glass (BPSG), fluorine silica glass
(FSG) or non-impurity-doped silica glass (USG) etc., can using chemically mechanical polishing (Chemical Mechanical Polish,
The methods of) CMP flush the upper surface of interlayer dielectric layer 320 with 302 upper surface of dummy grid.
With continued reference to FIG. 3, forming hard mask layer 330 covers dummy grid 302 and interlayer dielectric layer 320.
In the present embodiment, the material of hard mask layer 330 can be titanium nitride, and titanium nitride can not only play the work of mask layer
With, additionally it is possible to prevent metal from spreading.
With continued reference to FIG. 3, forming photoresist layer 340 covers hard mask layer 330.
In the present embodiment, photoresist layer 340 can be formed by spin coating proceeding.
Referring to FIG. 4, removal is located at photoresist layer 340 and hard mask layer 330 on dummy grid 302, formed patterned
Photoresist layer 340 ' and patterned hard mask layer 330 '.
It removes the photoresist layer 340 being located on dummy grid 302 and the specific process of hard mask layer 330 includes：Pass through exposure
Patterning photoresist layer 340 ' (i.e. removal is located at the photoresist layer 340 on dummy grid 302) is formed with techniques such as developments, then to scheme
The photoresist layer 340 ' of case is exposure mask, and removal is located at the hard mask layer 330 on dummy grid 302, forms patterned hard exposure mask
Layer 330 '.
In the present embodiment, removal is located at after photoresist layer and hard mask layer on dummy grid 302, in addition to exposure dummy grid
Except 302 upper surface, while also exposure at least partly 320 upper surface of interlayer dielectric layer.In other words, in order to make dummy grid 302
Upper surface be completely exposed to facilitate subsequent removal dummy grid 302,320 upper surface of interlayer dielectric layer also can partially be exposed.
Referring to FIG. 5, remaining (patterned) photoresist layer 340 ' shown in removal Fig. 4.
In existing method, usually after the hard mask layer on removal dummy grid, remaining photoresist layer is not gone all
It removes, but by remaining photoresist layer and hard mask layer together as mask, to be etched to dummy grid.But it is remaining
Photoresist layer can decompose during subsequent removal dummy grid, form dip dyeing object and disseminate each conductive structure.For this purpose, the present embodiment
In, especially before carrying out dummy grid 302 and removing, remaining photoresist layer 340 ' is all removed, and only with remaining (pattern
Change) hard mask layer 330 ' be mask, for being etched to dummy grid 302, to guarantee that subsequent dummy grid 302 removed
Journey carries out in clean environment, improves the performance for being formed by MOS transistor.
Referring to FIG. 6, with remaining hard mask layer 330 ' shown in Fig. 5 for mask, using pulsed plasma etching technics
It removes dummy grid 302 and forms opening 304.
In the present embodiment, since pulsed plasma is etched by certain frequency, have after etching every time of short duration
Time out, in this time out, etch products can be uniformly dispersed, and provide identical ring for the etching of next frequency
The process of border, this etching and pause is repeated continuously, to make the pulsed plasma etching technics no matter to which kind of width
The dummy grid of degree etch rate all having the same, to make to be formed by each opening depth identical.And described pulse etc. from
Daughter etching technics is further lock-out pulse plasma etch process, the temperature of the included electronics of lock-out pulse plasma
It is lower than the temperature that common (asynchronous) pulsed plasma includes electronics, thus lock-out pulse plasma to dummy grid 302 it
Outer other structures damage is small, helps to improve the performance of semiconductor devices.What lock-out pulse plasma etch process used
Gas includes Ar and HBr, and wherein the range of flow of Ar can be 100sccm~200sccm, and the range of flow of HBr can be
150sccm~450sccm.Lock-out pulse plasma can be by making the frequency of source power (source power) be equal to biasing function
The frequency of rate (bias power), and two Frequency Synchronizations and generate.
In the present embodiment, pressure range that the lock-out pulse plasma etch process uses can for 25mTorr~
75mTorr, the power bracket used can be 1500w~2500w, and the bias voltage ranges used can be 50V~150V, adopt
Pulse frequency be can be 2.5KHz~7.5KHz, the duty ratio of lock-out pulse plasma can be 20%~60%.
In the present embodiment, the gas that the lock-out pulse plasma etch process uses can also include O2, and O2's
Range of flow is 5sccm~15sccm.When in gas contain O2When, it can reduce lock-out pulse plasma etch process to interlayer
The etch rate of dielectric layer 320 to protect interlayer dielectric layer 320, and then keeps the insulating effect between semiconductor devices
Well, the performance of MOS transistor is improved.
In the present embodiment, after lock-out pulse plasma etch process, pulse can also be synchronized to opening 304
Plasma repair process, the gas that lock-out pulse plasma repair process uses includes CF4.The lock-out pulse plasma
The pressure range that body repair process uses for 25mTorr~75mTorr, the power bracket used for 150w~450w, use
Bias voltage ranges are 50V~150V, and the pulse frequency used is 2.5KHz~7.5KHz, lock-out pulse plasma duty ratio
It can be 10%~30%, the processing time can be 5s~15s。
In the present embodiment, after lock-out pulse plasma repair process, nitridation reparation can also be carried out to opening 304
Processing, the N that nitridation repair process uses2Range of flow be 50sccm~150sccm, nitrogenize repair process time be 50s~
150s.Nitridation repair process can be passivated the oxygen gap in (high K) gate dielectric layer, thus improve the medium of MOS transistor through when
Puncture (time dependent dielectric breakdown, TDDB) performance.
In the present embodiment, after the nitridation repair process, opening 304 can also be carried out clearly using diluted hydrofluoric acid again
It washes.
Referring to FIG. 7, forming metal gates 305 using metal material filling opening 304.
In the present embodiment, the metal material can be for such as tungsten (W), aluminium (Al), copper (Cu), golden (Au) or silver (Ag)
Deng.
Existing method generallys use continuous wave plasma etch process removal dummy grid 302, but in background technique
It is mentioned the threshold voltage that it will lead to different MOS transistors and difference occurs.Therefore, the present embodiment uses lock-out pulse plasma
Body etching technics removes dummy grid 302, due to lock-out pulse plasma to dummy grid 302 (for polysilicon, silicon nitride or without fixed
Shape carbon material is formed) etching it is identical with damage rate, i.e. quarter of the lock-out pulse plasma to the dummy grid 302 of different in width
It is identical to lose rate, therefore the dummy grid 302 of each MOS transistor can be removed simultaneously, to guarantee the different MOS transistors to be formed
Threshold voltage is equal, improves the performance of MOS transistor.
Further embodiment of this invention also provides a kind of forming method of CMOS transistor, please refers to Fig. 8 to Figure 12.
Semiconductor substrate 400 is provided, semiconductor substrate 400 has first area and second area, in the present embodiment, first
Region is NMOS transistor region, and as marked region shown in NFET in Fig. 8, second area is PMOS transistor region, in Fig. 8
Mark region shown in PFET.It should be noted that in other embodiments of the invention, first area may be PMOS crystal
Area under control domain, corresponding at this time, second area is NMOS transistor region.In the present embodiment, there is the first metal on first area
Grid 404 has dummy grid 403 on second area.Also there is high K to be situated between semiconductor substrate 400 and the first metal gates 404
Matter layer 402.The two sides of first metal gates 404 and high-K dielectric layer 402 are covered by side wall 406 simultaneously, and semiconductor substrate 400
Upper surface and the side of side wall 406 be etched stop-layer 410 covering.410 upper surface of etching stop layer and the first metal gates
404 upper surfaces flush.
Also there is high-K dielectric layer 401 between semiconductor substrate 400 and dummy grid 403.Dummy grid 403 and high-K dielectric layer
401 two sides are covered by side wall 405 simultaneously, and 400 upper surface of semiconductor substrate and the side of side wall 405 are etched stop-layer
410 coverings.410 upper surface of etching stop layer is flushed with 403 upper surface of dummy grid.402 layers of high K dielectric and the first metal gates
Can also have cap layer (not shown) and boundary layer (not shown) between 404, between high-K dielectric layer 401 and dummy grid 403
It can have cap layer (not shown) and boundary layer (not shown).Semiconductor substrate 400 can also include area of isolation 400A, every
The first area and second area are isolated from region 400A.
In the present embodiment, semiconductor substrate 400 can be：Elemental semiconductor, including silicon crystal or germanium crystal, on insulator
Silicon (SOI, Silicon On Insulator) structure or silicon upper epitaxial layer structure；Compound semiconductor, including silicon carbide, arsenic
Gallium, gallium phosphide, indium phosphide, indium arsenide or dysprosium indium；Alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs,
GaInAs, GaInP, GaInAsP or their combination.
In the present embodiment, the material of dummy grid 403 can be polysilicon, silicon nitride or amorphous carbon etc..High-K dielectric layer
401 and the material of high-K dielectric layer 402 can be HfO2、HFSiO、HfON、La2O3、LaAlO、Al2O3、ZrO2、ZrSiO、TiO2
Or Y2O3.The material of cap layer can be titanium nitride, and the material of boundary layer can be silica.Etching stop layer 410 can provide
Corresponding stress, and the stop layer as etch step, to prevent above-mentioned source region and drain region by over etching, material can be with
For silicon nitride or carbonitride of silicium etc..
In the present embodiment, area of isolation 400A can use such as local oxidation of silicon (LOCOS) or shallow trench isolation
(STI) it is formed.The present embodiment is specifically made of STI, and the material that each sti region can use can be silica, nitridation
Silicon, silicon oxynitride or their combination.
Although not shown in the drawing the present embodiment further includes in the semiconductor substrate 400 of 404 down either side of the first metal gates
It is respectively formed the first source region (not shown) and the first drain region (not shown), and in the semiconductor substrate of 403 down either side of dummy grid
The second source region (not shown) and the second drain region (not shown) are formed in 400.
With continued reference to FIG. 8, forming interlayer dielectric layer 420, the upper table of interlayer dielectric layer 420 in semiconductor substrate 400
Face is flushed with 403 upper surface of dummy grid, and the upper surface of interlayer dielectric layer 420 is also neat with 404 upper surface of the first metal gates simultaneously
It is flat.
In the present embodiment, the material of interlayer dielectric layer 420 can be silica, boron-phosphorosilicate glass (BPSG), fluorine silica glass
(FSG) or non-impurity-doped silica glass (USG) etc., can using chemically mechanical polishing (Chemical Mechanical Polish,
The methods of) CMP flush the upper surface of interlayer dielectric layer 420 with 403 upper surface of dummy grid.
With continued reference to FIG. 8, forming hard mask layer 430 covers dummy grid 403 and interlayer dielectric layer 420.
In the present embodiment, the material of hard mask layer 430 can be titanium nitride, and titanium nitride can not only play the work of mask layer
With, additionally it is possible to prevent metal from spreading.
With continued reference to FIG. 8, forming photoresist layer 440 covers hard mask layer 430, and removes and be located on dummy grid 403
Photoresist layer 440.
In the present embodiment, photoresist layer 440 can be formed by spin coating proceeding, then pass through the removal of the techniques such as exposure and imaging
Photoresist layer 440 on dummy grid 403.
Referring to FIG. 9, being mask with photoresist layer 440, removal is located at the hard mask layer 430 on dummy grid 403.
In the present embodiment, hard mask layer 430 can be etched using anisotropic dry etch process, in the process, led to
The thickness of normal photoresist layer 440 can reduce, and removal is located at after the hard mask layer 430 on dummy grid 403, remaining patterned hard
Mask layer 430 '.
Referring to FIG. 10, remaining photoresist layer 440 shown in removal Fig. 9.
In existing method, usually after the hard mask layer on removal dummy grid, remaining photoresist layer is not gone all
It removes, but by remaining photoresist layer and hard mask layer together as mask, to be etched to dummy grid.But it is remaining
Photoresist layer can decompose during subsequent removal dummy grid, form dip dyeing object and disseminate each conductive structure.For this purpose, the present embodiment
In, especially before carrying out dummy grid 403 and removing, remaining photoresist layer 440 is all removed, and only with remaining (pattern
Change) hard mask layer 430 ' be mask, for being etched to dummy grid 403, to guarantee that subsequent dummy grid 403 removed
Journey carries out in clean environment, improves the performance for being formed by CMOS transistor.
Figure 11 is please referred to, with remaining hard mask layer 430 ' shown in Figure 10 for mask, work is etched using pulsed plasma
Skill removes dummy grid 403 and forms opening 407.
In the present embodiment, the pulsed plasma etching technics is lock-out pulse plasma etch process, synchronous arteries and veins
The gas for rushing plasma etch process use includes Ar and HBr, wherein the range of flow of Ar can for 100sccm~
The range of flow of 200sccm, HBr can be 150sccm~450sccm.Lock-out pulse plasma can be by making source power
The frequency of (source power) be equal to bias power (bias power) frequency, and two Frequency Synchronizations and generate.Together
The temperature of the included electronics of pace pulse plasma is lower than the temperature that common (asynchronous) pulsed plasma includes electronics, therefore
Lock-out pulse plasma is small to the other structures damage except dummy grid 403, helps to improve the performance of semiconductor devices.
In the present embodiment, pressure range that the lock-out pulse plasma etch process uses can for 25mTorr~
75mTorr, the power bracket used can be 1500w~2500w, and the bias voltage ranges used can be 50V~150V, adopt
Pulse frequency be can be 2.5KHz~7.5KHz, the duty ratio of lock-out pulse plasma can be 20%~60%.
In the present embodiment, the gas that the lock-out pulse plasma etch process uses can also include O2, and O2's
Range of flow is 5sccm~15sccm.When in gas contain O2When, it can reduce lock-out pulse plasma etch process to interlayer
The etch rate of dielectric layer 420 to protect interlayer dielectric layer 420, and then keeps the insulating effect between semiconductor devices
Well, the performance of MOS transistor is improved.
In the present embodiment, after lock-out pulse plasma etch process, pulse can also be synchronized to opening 407
Plasma repair process, the gas that lock-out pulse plasma repair process uses includes CF4.The lock-out pulse plasma
The pressure range that body repair process uses for 25mTorr~75mTorr, the power bracket used for 150w~450w, use
Bias voltage ranges are 50V~150V, and the pulse frequency used is 2.5KHz~7.5KHz, lock-out pulse plasma duty ratio
It can be 10%~30%, the processing time can be 5s~15s.
In the present embodiment, after lock-out pulse plasma repair process, nitridation reparation can also be carried out to opening 407
Processing, the N that nitridation repair process uses2Range of flow be 50sccm~150sccm, nitrogenize repair process time be 50s~
150s.Nitridation repair process can be passivated the oxygen gap in (high K) gate dielectric layer, to improve the dielectric breakdown of MOS transistor
(time dependent dielectric breakdown, TDDB) performance.
In the present embodiment, after the nitridation repair process, opening 407 can also be carried out clearly using diluted hydrofluoric acid again
It washes.
Figure 12 is please referred to, the second metal gates 409 are formed using metal material filling opening 407.
In the present embodiment, the metal material can be for such as tungsten (W), aluminium (Al), copper (Cu), golden (Au) or silver (Ag)
Deng.
Existing method generallys use continuous wave plasma etch process removal dummy grid 403, but in background technique
It is mentioned the threshold voltage that it will lead to different CMOS transistors and difference occurs.Therefore, the present embodiment using lock-out pulse etc. from
Daughter etching technics remove dummy grid 403, due to lock-out pulse plasma to dummy grid 403 (for polysilicon, silicon nitride or nothing
Amorphous carbon material is formed) etching it is identical with damage rate, i.e., lock-out pulse plasma is to the dummy grid 403 of different in width
Etch rate is identical, therefore can remove the dummy grid 403 of each MOS transistor simultaneously, to guarantee the different CMOS to be formed crystalline substance
Body pipe threshold voltage is equal, improves the performance of CMOS transistor.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (13)
1. a kind of forming method of MOS transistor, which is characterized in that including：
Semiconductor substrate is provided, there is in the semiconductor substrate dummy grid, each dummy grid it is of different size；
Source region and drain region are respectively formed in the semiconductor substrate of the dummy grid down either side；
Interlayer dielectric layer, the upper surface of the interlayer dielectric layer and the dummy grid upper surface are formed on the semiconductor substrate
It flushes；
It forms hard mask layer and covers the dummy grid and the interlayer dielectric layer；
It forms photoresist layer and covers the hard mask layer；
Removal is located at the photoresist layer and the hard mask layer on dummy grid；
Remove the remaining photoresist layer；
The dummy grid is removed using pulsed plasma etching technics and forms opening, is etched according to certain frequency, every time
There is time out, time out makes etch products be evenly distributed, and the process of etching and pause is repeated, to make after etching
It is identical that opening depth must be formed by for the dummy grid of different in width；
Metal gates are formed using the metal material filling opening.
2. the forming method of MOS transistor as described in claim 1, which is characterized in that the pulsed plasma etches work
Skill is lock-out pulse plasma etch process, the gas that the lock-out pulse plasma etch process uses include Ar and
HBr。
3. the forming method of MOS transistor as claimed in claim 2, which is characterized in that the lock-out pulse plasma is carved
The pressure range that etching technique uses for 25mTorr~75mTorr, the power bracket used for 1500w~2500w, use it is inclined
Setting voltage range is 50V~150V, and the pulse frequency used is 2.5KHz~7.5KHz.
4. the forming method of MOS transistor as claimed in claim 3, which is characterized in that the lock-out pulse plasma is carved
The gas that etching technique uses further includes O2, and O2Range of flow be 5sccm~15sccm.
5. the forming method of MOS transistor as claimed in claim 2, which is characterized in that in lock-out pulse plasma etching
It further include that pulsed plasma repair process is synchronized to the opening, the lock-out pulse plasma is repaired after technique
The gas that multiple processing uses includes CF4。
6. the forming method of MOS transistor as claimed in claim 5, which is characterized in that the lock-out pulse plasma is repaired
Handle the pressure range used again as 25mTorr~75mTorr, the power bracket used is 150w~450w, the biasing of use
Voltage range is 50V~150V, and the pulse frequency used is 2.5KHz~7.5KHz.
7. the forming method of MOS transistor as claimed in claim 6, which is characterized in that in the lock-out pulse plasma
After repair process, the forming method further includes：Nitridation repair process is carried out to the opening, the nitridation repair process is adopted
N2Range of flow is 50sccm~150sccm, and the time of the nitridation repair process is 50s~150s.
8. a kind of forming method of CMOS transistor, which is characterized in that including：
Semiconductor substrate is provided, the semiconductor substrate has first area and second area, has the on the first area
One metal gates, have dummy grid on the second area, each dummy grid it is of different size；
The first source region and the first drain region are respectively formed in the semiconductor substrate of the first metal gates down either side；
The second source region and the second drain region are formed in the semiconductor substrate of the dummy grid down either side；
Interlayer dielectric layer, the upper surface of the interlayer dielectric layer and the dummy grid upper surface are formed on the semiconductor substrate
It flushes；
It forms hard mask layer and covers the dummy grid and the interlayer dielectric layer；
It forms photoresist layer and covers hard mask layer；
Removal is located at the photoresist layer and the hard mask layer on the dummy grid；
Remove the remaining photoresist layer；
The dummy grid is removed using pulsed plasma etching technics and forms opening, is etched according to certain frequency, every time
There is time out, time out makes etch products be evenly distributed, and the process of etching and pause is repeated, to make after etching
It is identical that opening depth must be formed by for the dummy grid of different in width；
The opening is filled using metal material and forms the second metal gates.
9. the forming method of CMOS transistor as claimed in claim 8, which is characterized in that the pulsed plasma etches work
Skill is lock-out pulse plasma etch process, the gas that the lock-out pulse plasma etch process uses include Ar and
HBr。
10. the forming method of CMOS transistor as claimed in claim 9, which is characterized in that the lock-out pulse plasma
The gas that etching technics uses further includes O2, and O2Range of flow be 5sccm~15sccm.
11. the forming method of CMOS transistor as claimed in claim 9, which is characterized in that carved in lock-out pulse plasma
After etching technique, the forming method further includes：Pulsed plasma repair process, the synchronization are synchronized to the opening
The gas that pulsed plasma repair process uses includes CF4。
12. the forming method of CMOS transistor as claimed in claim 9, which is characterized in that in the lock-out pulse plasma
After body repair process, the forming method further includes：Nitridation repair process, the nitridation repair process are carried out to the opening
The N of use2Range of flow is 50sccm~150sccm, and the time of the nitridation repair process is 50s~150s.
13. the forming method of CMOS transistor as claimed in claim 8, which is characterized in that the first area is NMOS brilliant
Body area under control domain and the second area are PMOS transistor region or the first area is PMOS transistor region and described
Second area is NMOS transistor region.
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| CN1771589A (en) * | 2003-04-03 | 2006-05-10 | 先进微装置公司 | Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device |
| CN101631897A (en) * | 2007-02-21 | 2010-01-20 | 应用材料股份有限公司 | Pulsed plasma system with pulsed sample bias for etching semiconductor structures |
| CN102983076A (en) * | 2011-09-07 | 2013-03-20 | 中国科学院微电子研究所 | Semiconductor integrated circuit manufacturing method |
| CN102983099A (en) * | 2011-09-07 | 2013-03-20 | 中国科学院微电子研究所 | Semiconductor integrated circuit manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1771589A (en) * | 2003-04-03 | 2006-05-10 | 先进微装置公司 | Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device |
| CN101631897A (en) * | 2007-02-21 | 2010-01-20 | 应用材料股份有限公司 | Pulsed plasma system with pulsed sample bias for etching semiconductor structures |
| CN102983076A (en) * | 2011-09-07 | 2013-03-20 | 中国科学院微电子研究所 | Semiconductor integrated circuit manufacturing method |
| CN102983099A (en) * | 2011-09-07 | 2013-03-20 | 中国科学院微电子研究所 | Semiconductor integrated circuit manufacturing method |
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