CN105096906B - Visual Signal Transmission System - Google Patents

Abstract

A visual signal transmission system. The visual signal transmission system includes a multi-branch bus, a first source driver chip, a second source driver chip and a timing controller. The first source driver chip includes a first source driver circuit and a first terminal circuit. The first terminal circuit is coupled to the multi-branch bus and the first source driver circuit, and is used to provide a first terminal resistor. The second source driver chip includes a second source driver circuit and a second terminal circuit. The second terminal circuit is coupled to the multi-branch bus and the second source driver circuit, and is used to provide a second terminal resistor. The timing controller is connected to the first source driver chip and the second source driver chip through the multi-branch bus.

Description

Visual Signal Transmission System

technical field

The invention relates to a transmission system, in particular to a visual signal transmission system.

Background technique

Displays are widely used electronic products today. In order to realize the realism and vividness of the display image, it is inevitable to increase the image resolution and increase the image update frequency, so the display for high-speed application is born accordingly. Facing the requirements of high-speed applications, the reflection and attenuation of the transmission line will make it difficult to increase the frequency of the display, so the transmission line must have appropriate impedance matching.

In the multi-drop architecture of the display, a single output channel of the timing controller is coupled to several source driver chips via a pair of transmission lines. Traditionally, termination resistors have been placed on the printed circuit board closest to the input of the source driver chip to match the impedance of the transmission line. However, when the termination resistance on the printed circuit board does not match the impedance of the transmission line, signal reflection will occur, resulting in distortion of the transmitted signal.

Contents of the invention

The invention relates to a visual signal transmission system.

According to the present invention, a visual signal transmission system is proposed. The visible signal transmission system includes a multi-drop bus, a first source driver chip, a second source driver chip and a timing controller. The first source driver chip includes a first source driver circuit and a first terminal circuit. The first termination circuit is coupled to the multi-drop bus and the first source driver circuit, and is used for providing a first termination resistance. The second source driver chip includes a second source driver circuit and a second terminal circuit. The second termination circuit is coupled to the multi-branch bus and the second source driving circuit, and is used for providing a second termination resistance. The timing controller is connected to the first source driver chip and the second source driver chip through a multi-branch bus.

Description of drawings

In order to have a better understanding of the above description and other aspects of the present invention, preferred embodiments are listed below, and the following detailed descriptions are made in conjunction with the accompanying drawings. in:

FIG. 1 is a schematic diagram of a visual signal transmission system according to a first embodiment,

FIG. 2 is a partial schematic diagram of a visual signal transmission system according to a first embodiment,

Fig. 3 is a timing diagram of visible signal data transmission according to the first embodiment,

FIG. 4 is a schematic diagram of a terminal circuit according to the first embodiment,

Fig. 5 is a schematic diagram of a setting command according to the first embodiment,

Figure 6 is a schematic diagram of providing terminal resistors for all terminal circuits at the same time,

Fig. 7 is a schematic diagram of providing terminal resistance for part of the terminal circuit,

Fig. 8 is a schematic diagram of not providing terminal resistors for all terminal circuits at the same time,

Fig. 9 is a timing diagram of data transmission of a visual signal according to the second embodiment,

FIG. 10 is a schematic diagram of a terminal circuit according to a third embodiment,

Fig. 11 is a schematic diagram of a setting command according to a third embodiment,

12 is a schematic diagram of a visual signal transmission system according to a fourth embodiment,

Fig. 13 is a schematic diagram of a visual signal transmission system according to a fifth embodiment.

Description of reference symbols

1: Visual signal transmission system

11, 12: multi-branch bus

11a～11f, 12a～12f: transmission line

13a~13c, 14a~14c: source driver chips

15: Timing controller

111, 121: Impedance matching components

131a～131c, 141a～141c: terminal circuit

132a-132c, 142a-142c: source drive circuits

1321a～1321c: receiving circuit

1322a～1322c: driving signal generator

1323a～1323c: registers

C1～C3: setting command

D1～D3: Visual signal data

DIO1, DIO2: data input and output start signal

LD: download signal

LV0: bus signal

M1～M4: multiplexer

R1～R6: resistance

RT1～RT6, 112, 122: terminal resistance

SW: switch

Ssw: switch signal

SEL0, SEL1: selection signal

TF: image time

TS1, TS2, TS3: set time period

TD1, TD2, TD3: Transmission period

Detailed ways

first embodiment

Referring to FIG. 1, FIG. 1 is a schematic diagram of a visual signal transmission system according to a first embodiment. The visual signal transmission system 1 includes a multi-drop bus (Multi-drop Bus) 11 , a multi-drop bus 12 , source driver chips 13 a - 13 c , source driver chips 14 a - 14 c and a timing controller 15 . The timing controller 15 is connected to the source driver chips 13 a - 13 c through the multi-branch bus 11 , and is connected to the source driver chips 14 a - 14 c through the multi-branch bus 12 . The source driver chip 13a includes a terminal circuit 131a and a source driver circuit 132a. The termination circuit 131a is coupled to the multi-drop bus 11 and the source driver circuit 132a, and serves to provide a termination resistance. The source driver chip 13b includes a terminal circuit 131b and a source driver circuit 132b. The termination circuit 131b is coupled to the multi-branch bus 11 and the source driver circuit 132b, and serves to provide a termination resistance. The source driver chip 13c includes a termination circuit 131c and a source driver circuit 132c. The termination circuit 131c is coupled to the multi-drop bus 11 and the source driver circuit 132c, and serves to provide a termination resistance.

The source driver chip 14a includes a termination circuit 141a and a source driver circuit 142a. The termination circuit 141a is coupled to the multi-drop bus 12 and the source driver circuit 142a, and is used to provide a termination resistance. The source driver chip 14b includes a termination circuit 141b and a source driver circuit 142b. The termination circuit 141b is coupled to the multi-drop bus 12 and the source driver circuit 142b, and is used to provide a termination resistance. The source driver chip 14c includes a termination circuit 141c and a source driver circuit 142c. The termination circuit 141c is coupled to the multi-drop bus 12 and the source driver circuit 142c, and serves to provide a termination resistance.

The multi-drop bus 11 and the multi-drop bus 12 are transmitted, for example, in a mini Low-Voltage Differential Signaling (mini Low-Voltage Differential Signaling, mini-LVDS) format. The multi-drop bus 11 includes a transmission line 11a and a transmission line 11b, and the multi-drop bus 12 includes a transmission line 12a and a transmission line 12b. Timing controller 15 is connected to source driver chips 13a-13c through transmission line 11a and transmission line 11b, and timing controller 15 is connected to source driver chips 14a-14c through transmission line 12a and transmission line 12b.

Referring to FIG. 2 and FIG. 3 at the same time, FIG. 2 is a partial schematic diagram of the visual signal transmission system according to the first embodiment, and FIG. 3 is a timing diagram of the visual signal data transmission according to the first embodiment. The source driving circuit 132a includes a receiving circuit 1321a, a driving signal generator 1322a and a register 1323a. The source driving circuit 132b includes a receiving circuit 1321b, a driving signal generator 1322b and a register 1323b. The source driving circuit 132c includes a receiving circuit 1321c, a driving signal generator 1322c and a register 1323c.

The bus signal LV0 represents setting commands and visual signal data transmitted via the multi-branch bus 11 , and the timing controller 15 transmits the bus signal LV0 to the source driver chips 13 a - 13 c via the multi-branch bus 11 . The download signal LD indicates the start of a picture time TF. The timing controller 15 outputs the download signal LD to the source driver chip 13a. When the download signal LD occurs, the receiving circuit 1321 a receives the setting command C1 via the multi-drop bus 11 during the setting period TS1 , and receives the visual signal data D1 via the multi-drop bus 11 during the transmission period TD1 . The transmission period TD1 is after the setting period TS1. The termination circuit 131 a provides a termination resistance according to a setting command C1 for a set period TS1 and connects the termination resistance to the multi-drop bus 11 . The driving signal generator 1322a outputs a corresponding source driving signal according to the visible signal data D1. After the transmission period TD1 ends, the source driver chip 13 a outputs the data input and output start signal DIO1 to the source driver chip 13 b.

After the data input and output start signal DIO1 activates the source driver chip 13b, the receiving circuit 1321b receives the setting command C2 via the multi-branch bus 11 during the setting period TS2, and receives the visual signal data D2 via the multi-branch bus 11 during the transmission period TD2 . The transmission period TD2 is after the setting period TS2. The termination circuit 131 b provides a termination resistance according to a setting command C2 for a set period TS2 , and connects the termination resistance to the multi-drop bus 11 . The driving signal generator 1322b outputs a corresponding source driving signal to the panel according to the visible signal data D2. After the transmission period TD2 ends, the source driver chip 13b outputs the data input and output start signal DIO2 to the source driver chip 13c.

After the data input and output start signal DIO2 activates the source driver chip 13c, the receiving circuit 1321c receives the setting command C3 via the multi-branch bus 11 during the setting period TS3, and receives the visual signal data D3 via the multi-branch bus 11 during the transmission period TD3 . The transfer period TD3 is after the set period TS3. The termination circuit 131c provides a termination resistance according to a setting command C3 for a set period TS3, and connects the termination resistance to the multi-drop bus 11. The driving signal generator 1322c outputs a corresponding source driving signal according to the visible signal data D3.

The terminal circuits 131 a - 131 c in the above embodiments provide terminal resistors sequentially, and the terminal resistors provided by the terminal circuits 131 a - 131 c can be connected in parallel via the multi-branch bus 11 . However, the practical application is not limited thereto. In another embodiment, the termination circuit 131 a stops providing the termination resistance after the transmission period TD1 ends. The termination circuit 131b stops supplying the termination resistance after the transfer period TD2 ends. The termination circuit 131c stops supplying the termination resistance after the transfer period TD3 ends. In this way, the termination resistors provided by the termination circuits 131 a - 131 c are not connected in parallel with each other via the multi-branch bus 11 . When the visible signal data is transmitted, the corresponding terminal circuit stops providing terminal resistance.

Referring to FIG. 2, FIG. 4 and FIG. 5, FIG. 4 is a schematic diagram of a terminal circuit according to the first embodiment, and FIG. 5 is a schematic diagram of a setting command according to the first embodiment. The circuit design of the aforementioned terminal circuits 131b and 131c may be the same as that of the terminal circuit 131a, and the setting command C1 includes a switch signal Ssw, a selection signal SEL0, and a selection signal SEL1. The terminal circuit 131a includes resistors R1 to R6, a selection circuit, and a switch SW. The switch signal Ssw is used to control the switch SW. The resistance values of the resistors R1-R3 are different from each other, and the resistance values of the resistors R4-R6 are different from each other. The selection circuit includes multiplexers M1-M4.

The multiplexers M1 and M2 select one of the resistors R1-R3 as the first candidate resistors according to the selection signal SEL0 of the setting command C1 during the setting period TS1, and the multiplexers M3 and M4 are set During the period TS1, one of the resistors R4-R6 is selected as the second candidate resistor according to the selection signal SEL1 of the setting command C1. The switch SW is turned on for the set period TS1 according to the switch signal Ssw of the set command C1 to provide a termination resistance. If the multiplexers M1 and M2 select the resistor R1 as the first candidate resistor and the multiplexers M3 and M4 select the resistor R4 as the second candidate resistor during the set period TS1, the termination resistor provided by the termination circuit 131a That is, resistor R1 is connected in series with resistor R4.

Referring to FIG. 1 , FIG. 4 and FIG. 6 at the same time, FIG. 6 is a schematic diagram of providing terminal resistors for all terminal circuits at the same time. The termination circuits 131 a - 131 c can respectively provide termination resistors RT1 - RT3 , and simultaneously connect both ends of the termination resistors RT1 - RT3 to the multi-branch bus 11 . Terminal resistors RT1-RT3 can be obtained from the combination of resistors R1-R6. For example, the terminal resistor RT1 may be a resistor R1 connected in series with a resistor R4. The terminal resistor RT2 may be a resistor R2 connected in series with a resistor R5. The terminal resistor RT3 may be a resistor R3 connected in series with a resistor R6. The terminal resistor RT1 is connected in parallel with the terminal resistor RT2 and the terminal resistor RT3 via the multi-branch bus 11 . The termination circuits 141 a - 141 c can respectively provide termination resistors RT4 - RT6 , and connect both ends of the termination resistors RT4 - RT6 to the multi-branch bus 12 at the same time. The terminal resistor RT4 is connected in parallel with the terminal resistor RT5 and the terminal resistor RT6 via the multi-branch bus 12 .

Referring to FIG. 1 and FIG. 7 at the same time, FIG. 7 is a schematic diagram of providing terminal resistors for some terminal circuits. Terminal circuit 131b, terminal circuit 131c, terminal circuit 141a and terminal circuit 141b respectively provide terminal resistance RT2, terminal resistance RT3, terminal resistance RT4 and terminal resistance RT5, and terminal circuit 131a and terminal circuit 141c do not provide terminal resistance RT1 and terminal resistance respectively RT6. Both ends of the terminating resistor RT2 and the terminating resistor RT3 are connected to the multi-branch bus 11 at the same time, and both ends of the terminating resistor RT4 and the terminating resistor RT5 are connected to the multi-branch bus 12 at the same time. Both ends of the terminating resistor RT1 are not connected to the multi-drop bus 11 at the same time, and both ends of the terminating resistor RT6 are not connected to the multi-drop bus 12 at the same time.

Referring to FIG. 1 and FIG. 8 at the same time, FIG. 8 is a schematic diagram for all terminal circuits without providing terminal resistors at the same time. The terminal circuits 131 a to 131 c are not provided with terminal resistors RT1 to RT3 respectively, and the terminal circuits 141 a to 141 c are not provided with terminal resistors RT4 to RT6 respectively. Both ends of the terminating resistor RT1 are not connected to the multi-drop bus 11 at the same time, and both ends of the terminating resistor RT2 are not connected to the multi-drop bus 11 at the same time. Both ends of the terminating resistor RT3 are not connected to the multi-drop bus 11 at the same time, and both ends of the terminating resistor RT4 are not connected to the multi-drop bus 12 at the same time. Both ends of the terminating resistor RT5 are not connected to the multi-drop bus 12 at the same time, and both ends of the terminating resistor RT6 are not connected to the multi-drop bus 12 at the same time.

second embodiment

Referring to FIG. 2 and FIG. 9 at the same time, FIG. 9 is a timing diagram of visual signal data transmission according to the second embodiment. The second embodiment is mainly different from the first embodiment in that the terminal circuit 131a, the terminal circuit 131b and the terminal circuit 131c all provide terminal resistance according to the setting command C1 at the set period TS1, and connect the terminal resistance to the multi-branch bus 11. Further, the receiving circuit 1321 a receives the setting command C1 via the multi-drop bus 11 during the setting period TS1 , and receives the visual signal data D1 via the multi-drop bus 11 during the transmission period TD1 . The termination circuit 131 a , the termination circuit 131 b , and the termination circuit 131 c all provide a termination resistance according to a setting command C1 for a set period TS1 , and connect the termination resistance to the multi-drop bus 11 . The driving signal generator 1322a outputs a corresponding source driving signal according to the visible signal data D1. After the transmission period TD1 ends, the source driver chip 13 a outputs the data input and output start signal DIO1 to the source driver chip 13 b.

After the data input and output start signal DIO1 activates the source driver chip 13b, the receiving circuit 1321b receives the visible signal data D2 via the multi-branch bus 11 during the transmission period TD2. The transmission period TD2 follows the transmission period TD1. The driving signal generator 1322b outputs a corresponding source driving signal according to the visible signal data D2. After the transmission period TD2 ends, the source driver chip 13b outputs the data input and output start signal DIO2 to the source driver chip 13c. After the data input and output start signal DIO2 activates the source driver chip 13c, the receiving circuit 1321c receives the visible signal data D3 via the multi-branch bus 11 during the transmission period TD3. The transfer period TD3 follows the transfer period TD2. The driving signal generator 1322c outputs a corresponding source driving signal according to the visible signal data D3.

third embodiment

Referring to FIG. 2, FIG. 4, FIG. 5, FIG. 10 and FIG. 11 simultaneously, FIG. 10 is a schematic diagram of a terminal circuit according to a third embodiment, and FIG. 11 is a schematic diagram of a setting command according to a third embodiment. The main difference between the third embodiment and the first embodiment is that the terminal circuit 131a of the third embodiment does not include multiplexers M3-M4 and resistors R4-R6, and the setting command C1 of the third embodiment does not Includes selection signal SEL1. The multiplexers M1 and M2 select one of the resistors R1-R3 as the terminal resistance according to the selection signal SEL0 of the setting command C1 during the setting period TS1, and the switch SW is switched according to the setting command C1 during the setting period TS1. Signal Ssw is turned on to provide a termination resistance.

Fourth embodiment

Referring to FIG. 1 and FIG. 12 simultaneously, FIG. 12 is a schematic diagram of a visual signal transmission system according to a fourth embodiment. The main difference between the fourth embodiment and the first embodiment is that the visual signal transmission system 4 further includes an impedance matching element 111 and an impedance matching element 121 . The impedance matching element 111 and the impedance matching element 121 are, for example, resistors, capacitors or inductors. Impedance matching element 111 is provided at multi-drop bus 11 , and impedance matching element 121 is provided at multi-drop bus 12 . In addition to the terminal resistors provided by the source driver chips 13a-13c and the source driver chips 14a-14c, the visible signal transmission system 4 can also use The impedance matching element 111 and the impedance matching element 121 outside 14c make the adjustment of impedance matching more flexible.

fifth embodiment

Referring to FIG. 1 and FIG. 13 simultaneously, FIG. 13 is a schematic diagram of a visual signal transmission system according to a fifth embodiment. The main difference between the fifth embodiment and the first embodiment is that the visual signal transmission system 5 further includes an impedance matching element 111, a terminal resistor 112, an impedance matching element 121, and a terminal resistor 122, and the multiple components of the visual signal transmission system 5 The branch bus 11 further includes transmission lines 11c to 11f and transmission lines 12c to 12f. The impedance matching element 111 is provided between the transmission line 11c and the transmission line 11d, and the impedance matching element 121 is provided between the transmission line 12c and the transmission line 12d. The impedance matching element 111 can match the impedance of the transmission line 11c and the transmission line 11d with the terminal resistors provided by the source driver chips 13a-13c. The impedance matching element 121 can match the impedance of the transmission line 12c and the transmission line 12d with the termination resistors provided by the source driver chips 14a-14c. The terminal resistance 112 is provided between the transmission line 11e and the transmission line 11f, and the terminal resistance 122 is provided between the transmission line 12e and the transmission line 12f. The terminal resistor 112 is used for impedance matching with the transmission line 11e and the transmission line 11f, and the terminal resistor 122 is used for impedance matching with the transmission line 12e and the transmission line 12f.

When the terminating resistor is arranged on the printed circuit board, the signal entering the source driver chip still has to go through a path of impedance mismatch, so the signal received by the source driver chip will still be distorted. In contrast, the visible signal transmission system described in the above embodiments embeds the terminal resistor in the source driver chip, thus shortening the path of impedance mismatch, thereby improving the distortion of the signal received by the source driver chip. In addition, due to the different arrangement positions of the source driver chips, the transmission line resistances between different source driver chips and timing controllers may be different. The terminal circuit described in the above embodiments can flexibly adjust the resistance of the terminal resistor, so that each source driver chip and the transmission line can achieve proper impedance matching.

In summary, although the present invention has been disclosed by the preferred embodiments above, they are not intended to limit the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of claims.

Claims (16)

1. A visual signal transmission system, comprising: A multi-drop bus comprising a plurality of first transmission lines and a plurality of second transmission lines; timing controller; The first source driver chip is connected to the timing controller through the plurality of first transmission lines, and includes: a first source driver circuit; and A first termination circuit, which is coupled to the plurality of first transmission lines and the first source driver circuit, and is used for providing a first termination resistance with a first adjustable resistance, wherein the first The adjustable resistance value is determined according to the first setting command output by the timing controller during the first setting period, and the timing controller transmits the first visual signal data to the first source during the first transmission period a drive circuit, the first transfer period is after the first set period; and The second source driver chip is connected to the timing controller through the plurality of second transmission lines, and includes: a second source driver circuit; and A second termination circuit, which is coupled to the plurality of second transmission lines and the second source driver circuit, and is used to provide a second termination resistance with a second adjustable resistance, wherein the second The adjustable resistance value is determined according to the second setting command output by the timing controller during the second setting period, and the timing controller transmits the second visual signal data to the second source during the second transmission period The driving circuit, the second transmission period is after the second set period. 2. The visual signal transmission system according to claim 1, wherein the first source driver circuit comprises: A first receiving circuit configured to receive the first setting command via the multi-drop bus during the first setting period, and receive the first possible command via the multi-drop bus during the first transmission period. Depending on the signal data, the first transmission period and the first set period are within one image time; and a first driving signal generator, configured to output a plurality of first source driving signals according to the first visible signal data; Wherein, the first termination circuit provides the first termination resistance according to the first setting command during the first setting period, and connects the first termination resistance to the multi-branch bus. 3. The visual signal transmission system according to claim 2, wherein the first source driver circuit further comprises: The first register is used to store the first setting command. 4. The visual signal transmission system according to claim 2, wherein said first termination circuit stops supplying said first termination resistance after said first transmission period ends. 5. The visual signal transmission system according to claim 2, wherein said first terminal circuit comprises: a plurality of first resistors having different resistance values from each other; and A selection circuit for selecting a part of the first resistors according to the first setting command during the first setting period, wherein the number of the first resistors in this part is one or more, and the first a termination resistance is generated based on at least the portion of the first resistance; and A switch is used to connect at least the part of the first resistor, and provide the first terminal resistor according to the first setting command. 6. The visual signal transmission system according to claim 5, wherein the first setting command includes a first selection signal, and the selection circuit includes: a first multiplexer; and A second multiplexer, which and the first multiplexer select one of the first resistors as the first terminal resistor according to the first selection signal. 7. The visual signal transmission system according to claim 6, wherein the first setting command further includes a switch signal for controlling the switch. 8. The visual signal transmission system according to claim 5, wherein the first terminal circuit further includes a plurality of second resistors, the resistance values of these second resistors are different from each other, and the first setting command includes the first A selection signal and a second selection signal, the selection circuit includes: a first multiplexer; a second multiplexer, which and the first multiplexer select one of the first resistors as a first candidate resistor according to the first selection signal; a third multiplexer; and A fourth multiplexer, which and the third multiplexer select one of the second resistors as a second candidate resistor according to the second selection signal, and the switch is electrically connected to the first candidate resistance and the second candidate resistance to provide the first termination resistance. 9. The visual signal transmission system according to claim 8, wherein the first setting command further includes a switch signal for controlling the switch. 10. The visual signal transmission system according to claim 2, wherein the second source driver circuit comprises: A second receiving circuit configured to receive the second setting command via the multi-drop bus during the second setting period, and receive the second possible command via the multi-drop bus during the second transmission period. video signal data; and a second driving signal generator, configured to output a plurality of second source driving signals according to the second visible signal data; Wherein, the second termination circuit connects the second termination resistor to the multi-branch bus. 11. The visual signal transmission system according to claim 10, wherein the second source driver circuit further comprises: The second register is used for storing the second setting command. 12. The visual signal transmission system according to claim 10, wherein said second termination circuit stops supplying said second termination resistance after said second transmission period ends. 13. The visual signal transmission system according to claim 1, further comprising: An impedance matching element is provided on the multi-drop bus. 14. The visual signal transmission system according to claim 1, wherein both ends of the first terminating resistor are simultaneously connected to the multi-branch bus, and both ends of the second terminating resistor are simultaneously connected to The multi-drop bus. 15. The visual signal transmission system according to claim 1, wherein both ends of the first terminating resistor are connected to the multi-branch bus at the same time, and both ends of the second terminating resistor are not connected at the same time to the multi-drop bus. 16. The visual signal transmission system according to claim 1, wherein both ends of the first terminating resistor are not simultaneously connected to the multi-branch bus, and both ends of the second terminating resistor are not simultaneously connected to the multi-branch bus. connected to the multi-drop bus.