CN105095532B - The operation method of half node CMP model in a kind of host node domain - Google Patents
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Abstract
The present invention relates to the operation methods and semiconductor devices preparation method of half node CMP model in a kind of host node domain.The operation method includes: step (a): providing host node domain；Step (b): the host node domain is divided into several net regions, and geometry extraction directly is carried out to each net region, obtains numerical information；Step (c): the geological information in the numerical information is reduced to obtain half-section point geometry information, carries out half node CMP simulation according to the half-section point geometry information；Step (d): output analog result data, and determine the defects of simulation process point；Step (e): the defect point is analyzed on the host node domain；Step (f): domain modification guidance rule is generated, and is modified.The method of the invention is by adjusting the size of mesh opening in VCMP method, i.e., by adjusting the simulation resolution ratio of VCMP and the process shrink factor, to avoid two processing steps taken considerable time, to improve simulation precision.
Description
Technical field
The present invention relates to semiconductor fields, in particular it relates to half node CMP model in a kind of host node domain
Operation method and semiconductor devices preparation method.
Background technique
Ic manufacturing technology is a complicated technique, and technology innovation quickly, characterizes ic manufacturing technology
One key parameter is minimum feature size, i.e. critical size (critical dimension, CD).With semiconductor technology
It continues to develop, the critical size of device is smaller and smaller, and the reduction just because of critical size just to be arranged hundred on each chip
Ten thousand devices are possibly realized.
With the continuous diminution of semiconductor technology device size, when the dimensions of semiconductor devices is contracted to nanometer nodes,
Manufacturability design (Design for Manufacturing, DFM) in semi-conductor industry nano-engineer flow and method
It becomes more and more important.The DFM refer to by the production efficiency of fast lifting chip yield and reduce production cost for the purpose of,
Rule, tool and method in the design of Unify legislation chip, so that preferably duplication of the control integrated circuit to physics wafer, is
The design of process variability in a kind of predictable manufacturing process, so that from whole process that wafer manufactures is designed into up to optimizing.
The diminution of crystal grain (Die) size at present or technical process reduction, which refer in semiconductor device, simply partly to be led for one
The diminution of body device size, is primarily referred to as transistor.The diminution of crystal grain can guarantee to integrate more crystal grain on wafer,
And identical circuit design is kept, to reduce the cost of product.
The diminution of usual crystal grain advances International Semiconductor Technology Blueprint (International Technology
Roadmap for Semiconductors, ITRS) defined in lithography node, but sometimes the lithography node of crystal grain not by
ITRS definition, referred to as half node (Half-Node), wherein half node is one between two process nodes in ITRS
Kind alternative techniques (stop gap), to help the cost for reducing device.
In addition, with the continuous diminution of dimensions of semiconductor devices, the connection between IC designer and manufacturer more steps up
It is close, the design or manufacturability design (Design for Manufacturing, DFM) of device can reinforce designer and
Connection between manufacturer.By DFM, the data of Integrated manufacture can make the cooperation between designer and manufacturer, to mention
High production yields and processing performance, while reducing design cycle and design cost.
Fig. 1 is the process flow chart of domain preparation in the prior art, wherein the virtual chemistry machine involved in the DFM process
Tool polishes (Virtual Chemical Mechanical Polishing, VCMP), wherein including the host node version of CMP process
The process flow chart for scheming preparation is as shown in Figure 2 a.Usual half node domain be manufacturer provide follow host node design rule
Domain carries out what a certain proportion of diminution obtained, includes the verifying of DFM VCMP in half node domain, wherein typical process
As shown in Figure 2 b, the half node domain need to obtain before carrying out VCMP simulation, which, which usually passes through on simulation tool, collects
At domain instrument or by the domain instrument that third party provides reduce realize according to a certain percentage, the shortcomings that the method
It is that the step of domain reduces must carry out before simulation, and there is no integrated domain works for the simulation tool sometimes
Tool, the reduction process are needed by manually third party's tool being selected to carry out, and step needs take a substantial amount of time, especially
In batch process.
Further, since simulation process is on the host node domain i.e. half node domain for being directly applied to reduce, so defeated
Identification information and geological information out is also diminution, thus in the analysis for carrying out defect point, it needs on the domain of diminution
It executes, but the modification of normal domain is to carry out in original layout, therefore after obtaining domain alteration ruler, need first
Convert alteration ruler to the alteration ruler for meeting host node design rule, this is equally a very time-consuming process.In addition,
A large amount of disk space is occupied due to needing to store the domain of diminution in this process.
Therefore, the analogy method of VCMP needs to do the method there are above-mentioned multiple drawbacks in DFM in the prior art
It is further improved, to eliminate above-mentioned drawback.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In order to solve the problems in the existing technology the present invention, provides half node CMP mould in a kind of host node domain
The operation method of type, comprising:
Step (a): host node domain is provided；
Step (b): being divided into several net regions for the host node domain, and directly to each net region into
Row geometry extracts, and obtains numerical information；
Step (c): the geological information in the numerical information is reduced to obtain half-section point geometry information, according to institute
It states half-section point geometry information and carries out half node CMP simulation；
Step (d): output analog result data, and determine the defects of simulation process point；
Step (e): the defect point is analyzed on the host node domain；
Step (f): domain modification guidance rule is generated, and is modified.
Preferably, the step (b) includes following sub-step:
Step (b-1): the host node domain is divided by several net regions according to grid resolution；
Step (b-2): without reducing, directly progress geometry extraction obtains numerical information to indicate for the net region
The host node domain.
Preferably, the numerical information includes identification information and geological information.
Preferably, the identification information includes grid number and mesh coordinate；
The geological information includes mesh-density, grid line width and grid perimeter.
Preferably, the step (c) includes following sub-step:
Step (c-1): the geological information for representing host node domain is reduced by the process shrink factor, to obtain
Replace the half-section point geometry information of half node domain described in table；
Step (c-2): half node CMP simulation is carried out according to the half-section point geometry information, to obtain the analog result.
Preferably, the step (d) includes following sub-step:
Step (d-1): simulation value information obtained in half node CMP simulation is exported, to obtain the simulation
As a result；
Step (d-2) checks the simulation value information, and unusual simulation value information is filtered out；
Step (d-3) identification information according to corresponding to the simulation value of the abnormality is found in the host node domain
Upper corresponding grid, to determine defect point.
Preferably, the defect point refers to analog result beyond expected net region, the net region is to violate
The pattern of design rule or unreasonable territory pattern.
Preferably, repeating step (a)-step (f) until through verifying after carrying out the modification.
The present invention also provides a kind of semiconductor layout preparation methods, and the method includes selecting with the aforedescribed process in main section
The step of half node CMP simulation is carried out in point domain.
In order to solve the problems in the existing technology the present invention, provides a kind of half-section applied in host node domain
Point VCMP simulated technological process method, the method by adjusting the size of mesh opening (Grid size) in VCMP method, i.e., by adjusting
The simulation resolution ratio (VCMP simulation Resolution) and the process shrink factor of VCMP, to avoid in the prior art
Two processing steps taken considerable time, to improve simulation precision.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, device used to explain the present invention and principle.In the accompanying drawings,
Fig. 1 process flow chart that in the prior art prepared by domain；
Fig. 2 a includes the process flow chart of the host node domain preparation of CMP process in the prior art；
Fig. 2 b includes the process flow chart of the half node domain preparation of CMP process in the prior art；
Fig. 3 is the process of the host node domain Picking up geometry information in the embodiment of the invention comprising CMP process
Schematic diagram；
Fig. 4 a is the structural schematic diagram that the host node domain size of mesh opening comprising CMP process reduces in the prior art；
Fig. 4 b is the structure that the host node domain size of mesh opening in the embodiment of the invention comprising CMP process reduces
Schematic diagram；
Fig. 5 is process flow chart prepared by the host node domain in the embodiment of the invention comprising CMP process.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singular
It is intended to include plural form.Additionally, it should be understood that when using term "comprising" and/or " comprising " in the present specification
When, indicate that there are the feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of one or more
Other a features, entirety, step, operation, element, component and/or their combination.
Now, an exemplary embodiment of the present invention is more fully described with reference to the accompanying drawings.However, these exemplary realities
Applying example can be implemented with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.It should
These embodiments that are to provide understood are in order to enable disclosure of the invention is thoroughly and complete, and by these exemplary implementations
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, using identical appended drawing reference
It indicates identical element, thus description of them will be omitted.
The operation method of half node CMP model in a kind of host node domain of the present invention is done into one with reference to the accompanying drawing
The explanation of step.
Embodiment 1
In order to solve the problems in the existing technology the present invention, provides a kind of half-section applied in host node domain
Point VCMP simulated technological process method, the method by adjusting the size of mesh opening (Grid size) in VCMP method, i.e., by adjusting
The simulation resolution ratio (VCMP simulation Resolution) of VCMP and drag into reduce the factor, to avoid in the prior art
Two processing steps taken considerable time.
Fig. 5 is the process flow chart inventing the host node domain in a specific embodiment comprising CMP process and preparing, in conjunction with
Fig. 5 is further described the method for the invention.
Specifically, comprising the following steps:
Step (a): host node domain is provided；
Step (b): being divided into several net regions for the host node domain, and directly to each net region into
Row geometry extracts, and obtains numerical information；
Step (c): the geological information in the numerical information is reduced to obtain half-section point geometry information, according to described half
Node geological information carries out half node CMP simulation；
Step (d): output analog result data, and determine the defects of simulation process point；
Step (e): the obtained defect point is analyzed on the host node domain；
Step (f): domain modification guidance rule is generated, and is modified.
Specifically, wherein in the step (a), the host node domain refers to its domain knot with larger size
The domain structure of the nodes such as structure, such as 65nm, 45nm, but be not limited to that the numberical range.It needs with the development of technology
Will the domain structure described in half node (half-node) technique size it is more smaller than host node domain structure.
Include following sub-step in the step (b):
The host node domain is divided into several net regions according to grid resolution by step (b-1)；
Without reducing, directly progress geometry extraction obtains mentioning numerical information to indicate for the net region step (b-2)
The host node domain.
Specifically, in this step, before VCMP simulation, it is necessary to pass through required resolution ratio (i.e. size of mesh opening, Grid
Size layout information) is extracted, during extracting layout information, the host node domain divides multiple grids into first
(Grid), the identification information (Identification Information) and geometry letter in each grid are then extracted
It ceases (Geometry information), as shown in figure 3, for the half-section in the embodiment of the invention including CMP process
The flow diagram that point territory pattern and size of mesh opening reduce.
Wherein the identification information (Identification Information) include mesh coordinate (coordinate),
Grid numbers (Grid ID)；The geological information (Geometry information) includes density (Density), line width
(Line Width) and perimeter (Perimeter) etc..
After extraction obtains the numerical information, the domain is indicated by a series of numerical information, and
And a series of geological information is being subsequently used for simulation process.
The resolution ratio (resolution) or size of mesh opening (Grid size) are by the grid regions in the present invention
The amplification (magnification) in domain or the process shrink factor are adjusted.Wherein Fig. 4 b is that the present invention one is specific real
The process that host node territory pattern and size of mesh opening in mode comprising CMP process reduce is applied, can be observed by the process
It arrives, in the prior art, the host node domain selects domain instrument by process shrink factor f to the host node version first
Figure is reduced, and then extracts the domain after diminution by size of mesh opening m, after extraction the grid identification information with
And geological information is to reduce relative to host node domain, as shown in fig. 4 a.
And in embodiments herein, the host node domain directly passes through size of mesh opening n and extracts, wherein described
Relationship between n and m is m=n × f, as shown in Figure 4 b, is had in the method for the prior art and in the method for the invention identical
Lattice number or identical mesh shape, unlike, in the method for the invention, after the extraction no matter the grid
Identification information and geological information all do not reduce.
Heretofore described size of mesh opening or resolution ratio are by grid resolution in the prior art or size of mesh opening M
With the product reciprocal of process shrink factor f, the size of mesh opening does not reduce in the present invention, is by the host node domain
It is obtained after directly dividing.
In actual operation, the processing step is to be directed to have to reduce to obtain half node territory pattern from host node domain
Wafer operated, therefore, VCMP simulation must run according to the half-section point geometry information, therefore execution step (c)
The geological information is contracted to half-section point geometry information, half node CMP simulation is carried out according to the half-section point geometry information.
The step (c) includes following sub-step:
Step (c-1) by the process shrink factor by the geological information in the numerical information for representing host node domain into
Row reduces, to obtain the half-section point geometry information, to represent half node domain；
Step (c-2) carries out CMP simulation according to the half-section point geometry information, to obtain analog result.
Specifically, in the prior art, after extracting layout information, the layout information has reduced, so can
Directly to carry out VCMP simulation, and in the method for the invention, the layout information of the extraction does not reduce, therefore is carrying out
Before VCMP simulation, it is necessary to execute a reduction process, the reduction process is by work in VCMP process in this embodiment
Skill reduces what factor f was realized, and in this embodiment, the reduction process is that the geological information data obtained for extraction carry out
, there is no being reduced to physical layout, processing is carried out for geological information data and saves a large amount of time.
It is of the present invention to the improvement is that the domain that geometric figure of domain is not reduced, but be extracted
Information carries out diminution processing, to indicate half node layout information, so as to avoid the step reduced in the prior art to domain
Suddenly, a large amount of time is saved, especially in batch process.
Then CMP simulation, the VCMP analogy method and in the prior art method are carried out with the layout information after reducing
It is identical, it is to be carried out for geometry domain after reducing, only the method for the invention is after extracting numerical information to the numerical value
Information is reduced, and is then simulated, and details are not described herein.
After indicating that the information of half node domain carries out simulation acquisition analog result, analog result is exported, to obtain
Defect point and related data are stated, to search the defects of described simulation process point, including following sub-step:
Step (d-1), which will be simulated, obtains the output of simulation value information in CMP simulation, to obtain analog result；
Step (d-2) checks the simulation value information according to the filter algorithm write in advance, by unusual simulation
Numerical information filters out；
Step (d-3) identification information according to corresponding to the simulation value of the abnormality is found in the host node domain
Upper corresponding grid, to determine defect point.
Specifically, after simulation steps, with the output of identification information and geological information, to obtain simulation knot
Fruit, comprising thickness and CMP recess (dishing) etc. in the analog result, meanwhile, it is some special
(extraordinary) grid can be filtered out by the filtering algorithm (filtering algorithm) write in advance, the institute filtered out
Grid is stated as defect point (hotspot).
The defect point (hotspot) typically refers to analog result beyond anticipation, and the defect point is mostly to violate to set
Count the pattern of rule perhaps unreasonable territory pattern for example with ultralow or superelevation density or have it is too big or
Too small line width etc..
By the geological information, the identification information for violating design rule can be directly found very much, then basis
The identification information directly can find the defect dot grid by domain preview tool in domain the preview window.
In this step since the layout information and the host node grid correspond, do not need to described
Information is handled, and corresponding net region can be directly found according to the layout information, so as to avoid the prior art
In obtain analog result after need to be converted into result (amplifying processing) corresponding with host node domain, save a large amount of
Time.
In the step (e) on the host node domain carry out defect point analysis, with the determination defect point whether
The structure being desirable to passes through verifying if desired result does not need to modify；If desired it modifies, executes step
Suddenly (f).
In the step (f) after modifying, step (a)-step (f) is repeated until through verifying.
Specifically, modification guidance rule is generated according to the domain preview and geological information, such as increases dummy pattern
Or groove (Slot) is inserted into increased or decrease the density in defect point region.
The method of the invention and the prior art the difference is that, described in the prior art extraction information be reduce
, it is the domain for the diminution obtaining modification guidance rule, in order to correctly be positioned in host node domain, it is necessary to right
The modification guidance rule reduces the factor according to reduction process and amplifies, and letter is identified described in the method described in the present invention
Breath is directly extracted by host node domain, is not reduced, so avoiding the step of amplifying to domain.
Embodiment 2
The present invention also provides a kind of manufacturability design, the fortune including half node CMP model in above-mentioned host node domain
Row method.
In addition, the present invention also provides a kind of semiconductor layout preparation method, the step including the manufacturability design
Suddenly.
Specifically, the domain preparation method includes providing domain, is inserted into sealing ring insertion, is inserted into dummy pattern,
The verifying being designed carries out the preparation output of domain if the domain is not modified, will be modified if there is modification
Domain re-starts inspection.
Wherein the verifying of the design includes manufacturability design (Design for Manufacturing, DFM) and sets
Meter rule checks (DRC, Design Rule Check), wherein the DFM includes virtual chemically mechanical polishing (Virtual
Chemical Mechanical Polishing, VCMP), photoetching electronic analysis (Litho Electric Analysis), close
Keypad domain analysis (Critical Area Analysis), domain approach effect (Layout Proximity Effect), domain
Independence effect (Layout Depenment Effect) etc..
Wherein, the virtual chemically mechanical polishing (Virtual Chemical Mechanical Polishing, VCMP)
Method described in embodiment 1 is selected, with VCMP simulation it is contemplated that the change of thickness and thickness after the cmp step
Change.By using special filter algorithm (filtering algorithm), filtered beyond expected wafer landform or thickness
Out, become defect point (hotspot), the defect point (hotspot) adjusts identified and analysis for further design and layout
Whole or modification.
In order to solve the problems in the existing technology the present invention, provides a kind of VCMP applied in host node domain
Simulated technological process method, the method is by adjusting the size of mesh opening (Grid size) in VCMP method, i.e., by adjusting VCMP's
Resolution ratio (VCMP simulation Resolution) and the process shrink factor are simulated, to avoid two consumptions in the prior art
Take the processing step of plenty of time, to improve simulation precision.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (9)
1. the operation method of half node CMP model in a kind of host node domain, comprising:
Step (a): host node domain is provided；
Step (b): the host node domain is divided into several net regions, and directly each net region is carried out several
What is extracted, and obtains numerical information；
Step (c): the geological information in the numerical information is reduced to obtain half-section point geometry information, according to half node
Geological information carries out half node CMP simulation；
Step (d): output CMP analog result data, and determine the defects of half node CMP simulation process point；
Step (e): the defect point is analyzed on the host node domain；
Step (f): domain modification guidance rule is generated, and is modified.
2. the method according to claim 1, wherein the step (b) includes following sub-step:
Step (b-1): the host node domain is divided by several net regions according to grid resolution；
Step (b-2): the net region is without reducing, directly progress geometry extraction, obtains numerical information to indicate described
Host node domain.
3. the method according to claim 1, wherein the numerical information includes identification information and geological information.
4. according to the method described in claim 3, it is characterized in that, the identification information includes grid number and mesh coordinate；
The geological information includes mesh-density, grid line width and grid perimeter.
5. the method according to claim 1, wherein the step (c) includes following sub-step:
Step (c-1): the geological information for representing host node domain is reduced by the process shrink factor, to obtain generation
The half-section point geometry information of half node domain described in table；
Step (c-2): half node CMP simulation is carried out to the half-section point geometry information of acquisition, to obtain the analog result.
6. the method according to claim 1, wherein the step (d) includes following sub-step:
Step (d-1): simulation value information obtained in half node CMP simulation is exported, to obtain the analog result；
Step (d-2) checks the simulation value information, and unusual simulation value information is filtered out；
Step (d-3) identification information according to corresponding to the simulation value of the abnormality finds the phase on the host node domain
Corresponding grid, to determine defect point.
7. the method according to claim 1, wherein the defect point refers to analog result beyond expected grid
Region, the net region are the pattern or unreasonable territory pattern for violating design rule.
8. the method according to claim 1, wherein repeating step (a)-after carrying out the modification
Step (f) is until through verifying.
9. a kind of semiconductor layout preparation method, the method includes selecting method described in one of claim 1 to 8 in main section
The step of half node CMP simulation is carried out in point domain.
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| CN102024083A (en) * | 2010-12-15 | 2011-04-20 | 中国科学院微电子研究所 | A Method for Extracting Capacitance of Interconnect Structures Containing Redundant Metal |
| CN102521468A (en) * | 2011-12-30 | 2012-06-27 | 中国科学院微电子研究所 | Method and device for extracting parasitic parameters of interconnection line |
| CN103559364A (en) * | 2013-11-13 | 2014-02-05 | 中国科学院微电子研究所 | Method for Extracting Layout Graphic Features of Chip Layout and CMP Simulation Method |
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| US8671367B2 (en) * | 2008-06-25 | 2014-03-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit design in optical shrink technology node |
| US8745554B2 (en) * | 2009-12-28 | 2014-06-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Practical approach to layout migration |
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| CN102024083A (en) * | 2010-12-15 | 2011-04-20 | 中国科学院微电子研究所 | A Method for Extracting Capacitance of Interconnect Structures Containing Redundant Metal |
| CN102521468A (en) * | 2011-12-30 | 2012-06-27 | 中国科学院微电子研究所 | Method and device for extracting parasitic parameters of interconnection line |
| CN103559364A (en) * | 2013-11-13 | 2014-02-05 | 中国科学院微电子研究所 | Method for Extracting Layout Graphic Features of Chip Layout and CMP Simulation Method |
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