CN105093811B - Method and system for estimating MEEF larger graph - Google Patents
Method and system for estimating MEEF larger graph Download PDFInfo
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- CN105093811B CN105093811B CN201510497384.7A CN201510497384A CN105093811B CN 105093811 B CN105093811 B CN 105093811B CN 201510497384 A CN201510497384 A CN 201510497384A CN 105093811 B CN105093811 B CN 105093811B
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- 238000000034 method Methods 0.000 title claims abstract description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 85
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 85
- 239000010703 silicon Substances 0.000 claims abstract description 85
- 238000004088 simulation Methods 0.000 claims abstract description 25
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- 238000005457 optimization Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000011165 process development Methods 0.000 description 2
- 238000012937 correction Methods 0.000 description 1
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Abstract
The invention discloses a method and a system for estimating a large MEEF graph, wherein the method comprises the following steps: the method comprises the steps of increasing an offset a on the whole of an original photomask layer and reducing an offset B on the whole of the original photomask layer to obtain a photomask layer graph A and a photomask layer graph B, wherein the offset a is increased on the whole of the original photomask layer and the offset B is reduced on the whole of the original photomask layer; simulating the photomask layer graph A and the photomask layer graph B by utilizing an OPC model to obtain a simulated silicon wafer graph AA and a simulated silicon wafer graph BB of the photomask layer graph A and the photomask layer graph B; carrying out logic operation on the simulation silicon wafer graph AA and the simulation silicon wafer graph BB to obtain a difference graph; the width of the difference pattern is calculated, and the position with the larger width of the difference pattern is selected, so that the problem that some patterns are possibly combined with errors of a photomask to become new hot spots on the silicon wafer due to the fact that MEFF is larger in conventional silicon wafer hot spot inspection is effectively solved, and an important basis is provided for subsequent hot spot verification and process optimization.
Description
Technical Field
The invention relates to an OPC (Optical Proximity Correction) method, in particular to a method and a system for changing Mask offset and calculating an estimated MEEF (Mask Error Enhancement Factor) larger pattern according to an OPC simulation result.
Background
MEEF (Mask Error Enhancement Factor) is generally one of the criteria for measuring the photolithography process. The definition of MEEF is MEEF ═ Δ CD silicon wafer/Δ (CD mask/M), and CD is an abbreviation for critical dimension. Where M is the magnification of the mask, M is 4 in general, CD mask is 4 times the mask CD, CD mask/M is 1 times the mask CD, Δ (CD mask/M) is the variation of the CD on the 1 times mask, and Δ CD silicon wafer is the variation of the CD on the silicon wafer. MEFF can also be understood as the 1-fold change in mask CD by 1nm, the change in CD on a silicon wafer. A larger MEEF indicates a larger influence of mask variation on the CD on the silicon wafer.
Because the minimum design rule is different for each layer, i.e., the minimum CD for each layer, the reticle levels used by different lithography layers are different for accuracy and cost. The higher the mask level, the smaller the error between the actual mask CD and the ideal mask CD. However, for any class of mask, there is always an error between the actual mask CD and the ideal mask CD. The combination of MEEF and reticle errors has a greater effect on the wafer CD, which is MEEF x Δ (CD reticle/M).
Usually, photolithography process development and silicon wafer hot spot inspection are focused on individual patterns with smaller photolithography process windows, the types of patterns on an actual photomask are many, and the MEEF of a conventional pattern is difficult to accurately represent the MEEF of the actual pattern.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a method and a system for estimating a MEEF larger pattern, wherein the method utilizes an OPC model simulation method to screen out the MEEF larger pattern in all photomask patterns during OPC inspection to be used as a hot spot on a silicon wafer for subsequent verification, so that the problem that some patterns are possibly combined with errors of the photomask to become a new hot spot on the silicon wafer due to the fact that the MEFF is larger in the conventional silicon wafer hot spot inspection is effectively avoided, and an important basis is provided for subsequent hot spot verification and process optimization.
To achieve the above and other objects, the present invention provides a method for estimating a large MEEF pattern, comprising the steps of:
step one, on the basis of an original photomask layer, increasing an offset (a) and reducing an offset (B) for the original photomask layer to obtain a photomask layer graph (A) and a photomask layer graph (B) which increase the offset (a) and reduce the offset (B) for the original photomask layer;
simulating the photomask layer graph (A) and the photomask layer graph (B) by utilizing an OPC model to obtain a simulated silicon wafer graph (AA) and a simulated silicon wafer graph (BB) of the photomask layer graph (A) and the photomask layer graph (B);
performing logic operation on the simulated silicon wafer graph (AA) and the simulated silicon wafer graph (BB) to obtain a difference graph (CC) of the simulated silicon wafer graph (AA) and the simulated silicon wafer graph (BB);
and step four, calculating the width of the difference graph (CC) and selecting the position with larger width of the difference graph (CC).
Further, in the third step, performing a logical negation operation on the analog silicon wafer pattern (AA) and the analog silicon wafer pattern (BB).
Furthermore, the width of the differential pattern (CC) is 1 time of the CD variation of the photomask, and the variation of the CD on the silicon wafer is simulated.
Further, the larger the width of the difference pattern (CC) is, the larger MEEF is, and the larger the influence of the mask variation on the CD on the silicon wafer is.
Further, in step four, the position of the pattern with the maximum width of 10% of the difference pattern (CC) is selected.
Further, the overall increasing offset a and the overall decreasing offset b are 0.5 nm.
In order to achieve the above object, the present invention further provides a system for estimating a large MEEF graph, including:
the zooming module is used for increasing the offset (a) and reducing the offset (B) on the whole of the original photomask layer on the basis of the original photomask layer to obtain a photomask layer graph (A) and a photomask layer graph (B) which increase the offset (a) and reduce the offset (B) on the whole;
the OPC simulation module simulates the photomask layer graph (A) and the photomask layer graph (B) by utilizing an OPC model to obtain a simulated silicon wafer graph (AA) and a simulated silicon wafer graph (BB) of the photomask layer graph (A) and the photomask layer graph (B);
the logic operation module is used for carrying out logic operation on the simulation silicon chip graph (AA) and the simulation silicon chip graph (BB) to obtain a difference graph (CC) of the simulation silicon chip graph (AA) and the simulation silicon chip graph (BB);
the width calculation module is used for calculating the width of the difference graph (CC) and selecting the position with larger width of the difference graph (CC).
Further, the logic operation module carries out logic negation operation on the simulation silicon chip graph (AA) and the simulation silicon chip graph (BB).
Further, the width calculating module selects the position of the pattern having the maximum width of 10% of the difference pattern (CC).
Further, the overall increasing offset a and the overall decreasing offset b are 0.5 nm.
Compared with the prior art, the method and the system for predicting the MEEF larger graph utilize an OPC model to simulate the simulated graph on the silicon wafer after increasing the overall offset of the photomask layer and the simulated graph on the silicon wafer after reducing the overall offset of the photomask layer during OPC inspection, calculate the equivalent MEEF of all photomask layer graphs, screen out the graph with the larger MEEF in all photomask graphs, and determine the graph with the smaller photoetching process window by combining DOF, thereby effectively avoiding the problem that certain graphs are possibly combined with the error of the photomask to become a new hot spot on the silicon wafer due to the larger MEFF in the conventional silicon wafer hot spot inspection, and providing important basis for subsequent hot spot verification and process optimization.
Drawings
FIG. 1 is a method of estimating a large MEEF pattern according to the present invention;
FIG. 2 is a diagram of an original mask layer in the preferred embodiment of the present invention;
FIG. 3 illustrates an overall increase in the offset a and an overall decrease in the offset b of the mask layer in accordance with a preferred embodiment of the present invention;
FIG. 4 is a diagram illustrating a mask layer pattern A with an increased offset a according to the preferred embodiment of the present invention;
FIG. 5 is a mask layer pattern B with an overall increased offset B according to the preferred embodiment of the present invention;
FIG. 6 is a simulated silicon wafer pattern AA of the mask layer pattern A in the preferred embodiment of the present invention;
FIG. 7 is a simulated silicon wafer pattern BB of a mask layer pattern B in the preferred embodiment of the present invention;
FIG. 8 is a diagram of a difference graph CC according to the preferred embodiment of the present invention;
FIG. 9 is a schematic diagram illustrating a larger pattern position of an original mask layer pattern MEEF in the preferred embodiment of the present invention;
FIG. 10 is a system diagram of a system for predicting a larger MEEF graph according to the present invention.
Detailed Description
Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.
FIG. 1 is a flowchart illustrating steps of a method for estimating a large MEEF pattern according to the present invention. As shown in fig. 1, the method for estimating the large MEEF graph of the present invention includes the following steps:
and 101, on the basis of the original photomask layer, increasing the offset a and reducing the offset B integrally on the original photomask layer to obtain a photomask layer graph A and a photomask layer graph B which increase the offset a and reduce the offset B integrally. The ranges of offset a and offset b are: more than or equal to 1 OPC calculation lattice point and less than the minimum design rule. Assuming that fig. 2 is the original mask layer pattern, an offset a is added to the original mask layer as a whole and an offset B is reduced as a whole, as shown in fig. 3, to obtain a mask layer pattern a and a mask layer pattern B with an offset a increased as a whole and an offset B reduced as a whole, as shown in fig. 4 and 5.
Step 102, simulating the photo-mask layer pattern a and the photo-mask layer pattern B by using an OPC model to obtain a simulated silicon wafer pattern AA and a simulated silicon wafer pattern BB of the photo-mask layer pattern a and the photo-mask layer pattern B, as shown in fig. 6 and 7.
And 103, performing logical negation operation on the analog silicon wafer graph AA and the analog silicon wafer graph BB to obtain a difference graph CC of the analog graph AA and the analog graph BB. The difference pattern CC is shown in fig. 8. The width of the difference pattern CC is 1 time of the CD variation (a + b) of the photomask, and the variation of the CD on the silicon wafer is simulated. The larger the width of the difference pattern CC is, the larger MEEF is, and the larger the influence of the variation of the light shield on the CD on the silicon wafer is.
Step 104, calculating the width Of the difference pattern CC, selecting the position with larger width Of the difference pattern CC, i.e. the position Of the original mask layer pattern with larger MEEF, such as the circled positions in fig. 8 and 9, and enlarging the position Of the pattern with larger MEEF in fig. 8 in fig. 9, if the pattern with larger MEEF is also the pattern with smaller DOF (Depth Of Focus), the pattern is the pattern with smaller photolithography process window, and can be used as a reference for photolithography process development and a hotspot on a silicon wafer for subsequent verification.
The invention will be further described by a specific embodiment with reference to fig. 2 to 9: assuming that fig. 2 is an original mask layer pattern, an offset a (a is 0.5nm) and an offset B (B is 0.5nm) are added to the original mask layer as a whole, and then a mask layer pattern a and a mask layer pattern B are obtained as shown in fig. 3, as shown in fig. 4 and 5.
And simulating the photomask layer graph A and the photomask layer graph B by using an OPC model to obtain a simulated silicon wafer graph AA and a simulated silicon wafer graph BB of the photomask layer graph A and the photomask layer graph B, as shown in FIGS. 6 and 7.
And then performing logical negation operation on the simulation silicon wafer graph AA and the simulation silicon wafer graph BB to obtain a difference graph CC of the simulation graph AA and the simulation graph BB, as shown in FIG. 8. The width of the difference pattern CC is 1 mask CD variation a + b, which is 1nm, and the variation of the CD on the silicon wafer, i.e., the MEEF obtained by simulation, is simulated. The larger the width of the difference pattern CC is, the larger MEEF is, and the larger the influence of the variation of the light shield on the CD on the silicon wafer is.
Finally, the width of the difference pattern CC is calculated, the position of the pattern with the larger width of the difference pattern CC, namely the position of the pattern with the larger MEEF of the original photomask layer pattern, such as the circled positions in figures 8 and 9, is selected, the figure 9 enlarges the position of the pattern with the larger MEEF in figure 8, if the pattern with the larger MEEF is also the pattern with the smaller DOF, the pattern is the pattern with the smaller photoetching process window, and can be used as the reference for developing the photoetching process and can also be used as a hot spot on a silicon wafer for subsequent verification.
FIG. 10 is a system architecture diagram of a system for estimating a large MEEF pattern according to the present invention. As shown in fig. 1, a system for estimating a large MEEF graph according to the present invention includes: a scaling module 10, an OPC simulation module 11, a logic operation module 12 and a width calculation module 13.
The zooming module 10 increases the offset a and decreases the offset B to the original photomask layer on the basis of the original photomask layer to obtain a photomask layer graph A and a photomask layer graph B which increase the offset a and decrease the offset B; the OPC simulation module 11 simulates the photomask layer graph A and the photomask layer graph B by using an OPC model to obtain a simulated silicon wafer graph AA and a simulated silicon wafer graph BB of the photomask layer graph A and the photomask layer graph B; the logic operation module 12 performs a logic non-operation on the simulated silicon wafer pattern AA and the simulated silicon wafer pattern BB to obtain a difference pattern CC of the simulated silicon wafer pattern AA and the simulated silicon wafer pattern BB, specifically, the width of the difference pattern CC is 1 time of the change a + b of the photomask CD to 1nm, the variation of the CD on the simulated silicon wafer is the simulated MEEF, and the larger the width of the difference pattern CC is, the larger the MEEF is, the larger the influence of the variation of the photomask on the CD on the silicon wafer is; the width calculating module 13 is configured to calculate the width of the difference pattern CC, and select a position where the width of the difference pattern CC is larger, that is, a position where the mask layer pattern MEEF is larger.
In conclusion, the method and the system for predicting the large MEEF pattern utilize an OPC model to simulate the simulated pattern on the silicon wafer after increasing the overall offset of the photomask layer and the simulated pattern on the silicon wafer after reducing the overall offset of the photomask layer during OPC inspection, calculate the equivalent MEEF of all photomask layer patterns, screen out the large MEEF pattern in all photomask patterns, and determine the pattern with a small photoetching process window by combining DOF, thereby effectively avoiding the problem that certain patterns are not considered in conventional silicon wafer hotspot inspection and possibly combined with errors of the photomask to become a new hotspot on the silicon wafer due to the large MEFF, and providing important basis for subsequent hotspot verification and process optimization.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (10)
1. A method for estimating a large MEEF graph comprises the following steps:
step one, on the basis of an original photomask layer, increasing an offset (a) and reducing an offset (B) for the original photomask layer to obtain a photomask layer graph (A) and a photomask layer graph (B) which increase the offset (a) and reduce the offset (B) for the original photomask layer;
simulating the photomask layer graph (A) and the photomask layer graph (B) by utilizing an OPC model during OPC inspection to obtain a simulated silicon wafer graph (AA) and a simulated silicon wafer graph (BB) of the photomask layer graph (A) and the photomask layer graph (B);
performing logic operation on the simulated silicon wafer graph (AA) and the simulated silicon wafer graph (BB) to obtain a difference graph (CC) of the simulated silicon wafer graph (AA) and the simulated silicon wafer graph (BB);
and step four, calculating the width of the difference pattern (CC), and selecting the position with larger width of the difference pattern (CC), namely the position of the pattern with larger MEEF of the original photomask layer pattern, so as to be used as the reference for developing the photoetching process or as the hot spot on the silicon chip for subsequent verification.
2. The method of claim 1, wherein the method comprises the steps of: and in the third step, performing logical negation operation on the analog silicon chip pattern (AA) and the analog silicon chip pattern (BB).
3. The method of claim 2, wherein the method comprises the steps of: the width of the differential pattern (CC) is 1 time of the CD variation of the photomask, and the variation of the CD on the silicon wafer is simulated.
4. A method of predicting a larger profile of MEEF as claimed in claim 3, wherein: the larger the width of the difference pattern (CC) is, the larger MEEF is, and the larger the influence of the variation of the light receiving mask on the CD on the silicon wafer is.
5. The method of claim 4, wherein the method comprises the steps of: in step four, the position of the pattern with the maximum width of 10% of the difference pattern (CC) is selected.
6. The method of claim 5, wherein the method comprises the steps of: the overall increasing offset a and the overall decreasing offset b are 0.5 nm.
7. A system for predicting a larger graphic of MEEF, comprising:
the zooming module is used for increasing the offset (a) and reducing the offset (B) on the whole of the original photomask layer on the basis of the original photomask layer to obtain a photomask layer graph (A) and a photomask layer graph (B) which increase the offset (a) and reduce the offset (B) on the whole;
the OPC simulation module simulates the photomask layer graph (A) and the photomask layer graph (B) by utilizing an OPC model during OPC inspection to obtain a simulated silicon wafer graph (AA) and a simulated silicon wafer graph (BB) of the photomask layer graph (A) and the photomask layer graph (B);
the logic operation module is used for carrying out logic operation on the simulation silicon chip graph (AA) and the simulation silicon chip graph (BB) to obtain a difference graph (CC) of the simulation silicon chip graph (AA) and the simulation silicon chip graph (BB);
and the width calculation module is used for calculating the width of the difference pattern (CC), selecting the position with larger width of the difference pattern (CC), namely the position with larger MEEF of the original photomask layer pattern, and using the position as the reference of the development of the photoetching process or as a hot spot on a silicon chip for subsequent verification.
8. The system of claim 7, wherein the system is further configured to predict a larger MEEF pattern by: the logic operation module carries out logic negation operation on the simulation silicon chip graph (AA) and the simulation silicon chip graph (BB).
9. The system of claim 8, wherein the system is further configured to predict a larger MEEF pattern by: the width calculation module selects the position of the pattern with the maximum width of 10% of the difference pattern (CC).
10. The system of claim 8, wherein the system is further configured to predict a larger MEEF pattern by: the overall increasing offset a and the overall decreasing offset b are 0.5 nm.
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| JP4192618B2 (en) * | 2003-02-17 | 2008-12-10 | ソニー株式会社 | Mask correction method |
| CN101398859B (en) * | 2007-09-29 | 2010-09-08 | 上海华虹Nec电子有限公司 | Method for introducing light shield partial increment magnification coefficient into optical proximity effect model building |
| CN102043326B (en) * | 2009-10-20 | 2012-07-11 | 中芯国际集成电路制造(上海)有限公司 | Mask graph correcting method |
| US8492054B2 (en) * | 2011-03-25 | 2013-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for patterning fine features |
| CN103576444B (en) * | 2012-08-07 | 2016-07-06 | 中芯国际集成电路制造(上海)有限公司 | A kind of optical proximity correction method of mask plate |
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