CN105093739A - Liquid crystal display panel and antistatic array substrate thereof - Google Patents
Liquid crystal display panel and antistatic array substrate thereof Download PDFInfo
- Publication number
- CN105093739A CN105093739A CN201510458872.7A CN201510458872A CN105093739A CN 105093739 A CN105093739 A CN 105093739A CN 201510458872 A CN201510458872 A CN 201510458872A CN 105093739 A CN105093739 A CN 105093739A
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- diode
- adjacent
- static circuit
- data lines
- array base
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Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses a liquid crystal display panel and an antistatic array substrate thereof. The array substrate comprises a substrate, a plurality of scanning lines, a plurality of data lines and a plurality of first antistatic circuits. The scanning lines and the data lines are intersected on the substrate to define a display area. One first antistatic circuit is arranged between every two adjacent scanning lines or data lines, so that every two adjacent scanning lines or data lines discharge electricity to each other through the corresponding first antistatic circuit. In this way, static electricity accumulation can be reduced.
Description
Technical field
The present invention relates to technical field of liquid crystal display, particularly relate to the array base palte of a kind of display panels and electrostatic prevention thereof.
Background technology
Because the manufacturing process of display panels is complicated, be easy to produce electrostatic phenomenon, cause thin film transistor (TFT) breakdown and damage, serious impact is caused on the yield of display panels and quality.
As shown in Figure 1, in prior art, the display panels of electrostatic prevention comprises multi-strip scanning line 11, a plurality of data lines 12, multiple anti-static circuit 13 and public electrode wire 14, every bar sweep trace 11 is all connected with public electrode wire 14 by anti-static circuit 13 with every bar data line 12, all realizes discharging by anti-static circuit 13 and public electrode wire 14 to make sweep trace 11 and data line 12.Wherein, anti-static circuit 13 comprises diode 131 and diode 132, as shown in Figure 2.The positive pole of diode 131 is connected with the negative pole of diode 132, and the negative pole of diode 131 is connected with the positive pole of diode 132, and the positive pole of diode 132 is connected with sweep trace 11 or data line 12, and the positive pole of diode 131 is connected with public electrode wire 14.In order to prevent pressure reduction between sweep trace 11 and data line 12 excessive, it is very wide that the live width of public electrode wire 14 is done, and to reduce resistance, improves transmissibility; But the width of display panels frame can be increased, be unfavorable for the design of narrow frame.
Summary of the invention
Embodiments provide the array base palte of a kind of display panels and electrostatic prevention thereof, can electrostatic accumulation be reduced, reduce the cabling of public electrode wire, be beneficial to narrow frame design.
The invention provides a kind of array base palte of electrostatic prevention, it comprises substrate, multi-strip scanning line, a plurality of data lines and multiple first anti-static circuit, multi-strip scanning line and a plurality of data lines intersect and are arranged on substrate, to define a viewing area, at adjacent two sweep traces or arrange the first anti-static circuit between adjacent two data lines, mutually discharged by the first anti-static circuit to make two adjacent sweep traces or adjacent two data lines.
Wherein, at adjacent two sweep traces and all arrange the first anti-static circuit between adjacent two data lines.
Wherein, one end of two adjacent sweep traces arranges the first anti-static circuit; Or adjacent two one end of data line arranges the first anti-static circuit.
Wherein, the two ends of two adjacent sweep traces all arrange the first anti-static circuit; Or adjacent two the two ends of data line all arrange the first anti-static circuit.
Wherein, the first electrostatic prevention is arranged at the outside of viewing area.
Wherein, first anti-static circuit comprises the first diode, the second diode and the first film transistor, the negative pole of the first diode is connected the grid of the first film transistor respectively with the negative pole of the second diode, the source electrode of the first film transistor is connected with the positive pole of the first diode, the drain electrode of the first film transistor is connected with the positive pole of the second diode, and the positive pole of the first diode and the positive pole of the second diode are connected respectively to two adjacent sweep traces or adjacent two data lines.
Wherein, array base palte comprises the second anti-static circuit further, and the data line being positioned at a plurality of data lines both sides is connected with public electrode wire by the second anti-static circuit; Or the sweep trace being positioned at multi-strip scanning line both sides is connected with public electrode wire by the second anti-static circuit.
Wherein, the second electrostatic prevention is arranged at the outside of viewing area.
Wherein, second anti-static circuit comprises the 3rd diode, the 4th diode and the second thin film transistor (TFT), negative pole and the negative pole of the 4th diode of the 3rd diode are connected the grid of the second thin film transistor (TFT) respectively, the source electrode of the second thin film transistor (TFT) is connected with the positive pole of the 3rd diode, the drain electrode of the second thin film transistor (TFT) is connected with the positive pole of the 4th diode, and positive pole and the positive pole of tetrode of the 3rd diode are connected the data line being positioned at a plurality of data lines both sides or the sweep trace being positioned at multi-strip scanning line both sides and public electrode wire respectively.
The present invention also provides a kind of display panels, and it comprises above-mentioned array base palte.
Pass through such scheme, the invention has the beneficial effects as follows: the present invention passes through at adjacent two sweep traces or arrange the first anti-static circuit between adjacent two data lines, mutually discharged by the first anti-static circuit to make two adjacent sweep traces or adjacent two data lines, electrostatic accumulation can be reduced, reduce the cabling of public electrode wire, be beneficial to narrow frame design.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.Wherein:
Fig. 1 is the structural representation of the display panels of electrostatic prevention in prior art;
Fig. 2 is the circuit diagram of anti-static circuit in Fig. 1;
Fig. 3 is the structural representation of the array base palte of first embodiment of the invention;
Fig. 4 is the circuit diagram of the first anti-static circuit in Fig. 3;
Fig. 5 is the structural representation of the array base palte of second embodiment of the invention;
Fig. 6 is the circuit diagram of the second anti-static circuit in Fig. 5;
Fig. 7 is the structural representation of the display panels of first embodiment of the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under performing creative labour prerequisite, belong to the scope of protection of the invention.
Shown in Figure 3, Fig. 3 is the structural representation of the array base palte of first embodiment of the invention.As described in Figure 3, the array base palte 3 that the present embodiment discloses comprises substrate 31, multi-strip scanning line 32, a plurality of data lines 33 and multiple first anti-static circuit 34.
Multi-strip scanning line 32 and a plurality of data lines 33 intersect setting on the substrate 31, to define a viewing area A.Wherein multi-strip scanning line 32 extends along first direction, and a plurality of data lines 33 extends along second direction, and first direction is vertical with second direction.
At adjacent two sweep traces 32 or arrange the first anti-static circuit 34 between adjacent two data lines 33, mutually discharged by the first anti-static circuit 34 to make two adjacent sweep traces 32 or adjacent two data lines 33.
Preferably, at adjacent two sweep traces 32 and all arrange the first anti-static circuit 34 between adjacent two data lines 33, to reduce the pressure reduction between pressure reduction between multi-strip scanning line 32 or a plurality of data lines 33.
First anti-static circuit 34 is set in one end of adjacent two sweep traces 32, the first anti-static circuit 34 is set in one end of adjacent two data lines 33.
Preferably, the first anti-static circuit 34 is all set at the two ends of adjacent two sweep traces 32, at the two ends of adjacent two data lines 33, first anti-static circuit 34 is all set, to improve transmissibility.
As shown in Figure 4, the first anti-static circuit 34 comprises the first diode D1, the second diode D2 and the first film transistor T1.Wherein, negative pole and the negative pole of the second diode D2 of the first diode D1 are connected the grid G of the first film transistor T1 respectively, the source S of the first film transistor T1 is connected with the positive pole of the first diode D1, and the drain D of the first film transistor T1 is connected with the positive pole of the second diode D2.
The positive pole of the first diode D1 and the positive pole of the second diode D2 are connected respectively to two adjacent sweep traces 32 or adjacent two data lines 33.Namely the positive pole of the first diode D1 is connected with sweep trace 321, and the positive pole of the second diode D2 is connected with sweep trace 322, and sweep trace 322 is adjacent with sweep trace 321; The positive pole of the first diode D1 is connected with data line 331, and the positive pole of the second diode D2 is connected with data line 332, and data line 332 is adjacent with data line 331.
When sweep trace 322 is larger with the pressure reduction of scanning 321, or when data line 332 is larger with the pressure reduction of data line 331, the current potential of the grid G of the first film transistor T1 raises, now the first film transistor T1 conducting, to make sweep trace 322 and sweep trace 321 mutually discharge, data line 332 and data line 331 discharge mutually; And then the pressure reduction between sweep trace 322 and sweep trace 321 reduces, the pressure reduction between data line 332 and data line 331 reduces.Therefore the electrostatic accumulation of multi-strip scanning line 32 and a plurality of data lines 33 is reduced.
Preferably, the first anti-static circuit 34 is arranged on the outside of viewing area A, affects viewing area A to avoid the first anti-static circuit 34.
Compared with the display panels of prior art electrostatic prevention, the present embodiment passes through at adjacent two sweep traces 32 and all arrange the first anti-static circuit 34 between adjacent two data line 33, all mutually discharged by the first anti-static circuit 34 to make two adjacent sweep traces 32 and adjacent two data lines 33, the electrostatic accumulation of multi-strip scanning line 32 and a plurality of data lines 33 can be reduced, and reduce the cabling of public electrode wire, be beneficial to narrow frame design.
The present invention also provides the array base palte of the second embodiment, and the basis of its array base palte 3 disclosed in the first embodiment is described.Array base palte that the present embodiment discloses 3 also comprises the second anti-static circuit 35, as shown in Figure 5.Wherein, the second anti-static circuit 35 is arranged at the outside of viewing area A.Viewing area A is affected to avoid the second anti-static circuit 35.
Wherein, the data line being positioned at a plurality of data lines 33 both sides is connected with public electrode wire 4 by the second anti-static circuit 35; Or the sweep trace being positioned at multi-strip scanning line 32 both sides is connected with public electrode wire 4 by the second anti-static circuit 35.
Preferably, the data line being positioned at a plurality of data lines 33 both sides is connected with public electrode wire 4 by the second anti-static circuit 35; The sweep trace being positioned at multi-strip scanning line 32 both sides is also connected with public electrode wire 4 by the second anti-static circuit 35.
As shown in Figure 6, second anti-static circuit 35 comprises the 3rd diode D3, 4th diode D4 and the second thin film transistor (TFT) T2, negative pole and the negative pole of the 4th diode D4 of the 3rd diode D3 are connected the grid of the second thin film transistor (TFT) T2 respectively, the source electrode of the second thin film transistor (TFT) T2 is connected with the positive pole of the 3rd diode D3, the drain electrode of the second thin film transistor (TFT) T2 is connected with the positive pole of the 4th diode D4, positive pole and the positive pole of tetrode D4 of the 3rd diode D3 are connected the data line being positioned at a plurality of data lines 33 both sides or the sweep trace being positioned at multi-strip scanning line 32 both sides and public electrode wire 4 respectively.
When be positioned at a plurality of data lines 33 both sides data line or be positioned at the pressure reduction of the sweep trace of multi-strip scanning line 32 both sides and public electrode wire 4 larger time, the current potential of the grid of the second thin film transistor (TFT) T2 raises, now the second thin film transistor (TFT) T2 conducting, is discharged with public electrode wire 4 by the second anti-static circuit 35 mutually with the data line making to be positioned at a plurality of data lines 33 both sides or the sweep trace that is positioned at multi-strip scanning line 32 both sides; And then the pressure reduction between sweep trace 32 and data line 33 reduces.Therefore the electrostatic accumulation of multi-strip scanning line 32 and a plurality of data lines 33 is reduced.
The present invention also provides a kind of display panels, as shown in Figure 7, the display panels that the present embodiment discloses comprises array base palte 71 and sector region 72, and sector region 72 is for layout cabling, the array base palte 3 that array base palte 71 discloses for above-described embodiment, does not repeat them here.
In sum, the present invention passes through at adjacent two sweep traces or arrange the first anti-static circuit between adjacent two data line, is mutually discharged by the first anti-static circuit to make two adjacent sweep traces or adjacent two data lines; The data line being positioned at a plurality of data lines both sides is connected with public electrode wire by the second anti-static circuit; Or the sweep trace being positioned at multi-strip scanning line both sides is connected with public electrode wire by the second anti-static circuit, to make the data line being positioned at a plurality of data lines both sides mutually be discharged by the second anti-static circuit and public electrode wire, or the sweep trace being positioned at multi-strip scanning line both sides is discharged mutually by the second anti-static circuit and public electrode wire; Can electrostatic accumulation be reduced, reduce the cabling of public electrode wire, be beneficial to narrow frame design.
The foregoing is only embodiments of the invention; not thereby the scope of the claims of the present invention is limited; every utilize instructions of the present invention and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (10)
1. the array base palte of an electrostatic prevention, it is characterized in that, described array base palte comprises substrate, multi-strip scanning line, a plurality of data lines and multiple first anti-static circuit, described multi-strip scanning line and described a plurality of data lines intersect setting on the substrate, to define a viewing area, at adjacent two described sweep traces or arrange described first anti-static circuit between adjacent two described data lines, mutually discharged by described first anti-static circuit to make described two adjacent sweep traces or described two adjacent data lines.
2. array base palte according to claim 1, is characterized in that, at adjacent two described sweep traces and all arrange described first anti-static circuit between adjacent two described data lines.
3. array base palte according to claim 1, is characterized in that, one end of described two adjacent sweep traces arranges described first anti-static circuit; Or one end of described two adjacent data lines arranges described first anti-static circuit.
4. array base palte according to claim 1, is characterized in that, the two ends of described two adjacent sweep traces all arrange described first anti-static circuit; Or the two ends of described two adjacent data lines all arrange described first anti-static circuit.
5. array base palte according to claim 1, is characterized in that, described first electrostatic prevention is arranged at the outside of described viewing area.
6. array base palte according to claim 1, it is characterized in that, described first anti-static circuit comprises the first diode, second diode and the first film transistor, negative pole and the negative pole of described second diode of described first diode are connected the grid of described the first film transistor respectively, the source electrode of described the first film transistor is connected with the positive pole of described first diode, the drain electrode of described the first film transistor is connected with the positive pole of described second diode, the positive pole of described first diode and the positive pole of described second diode are connected respectively to described two adjacent sweep traces or adjacent two data lines.
7. the array base palte according to claim 1-6 any one, is characterized in that, described array base palte comprises the second anti-static circuit further, and the data line being positioned at described a plurality of data lines both sides is connected with public electrode wire by described second anti-static circuit; Or the sweep trace being positioned at described multi-strip scanning line both sides is connected with public electrode wire by described second anti-static circuit.
8. array base palte according to claim 7, is characterized in that, described second electrostatic prevention is arranged at the outside of described viewing area.
9. array base palte according to claim 7, it is characterized in that, described second anti-static circuit comprises the 3rd diode, 4th diode and the second thin film transistor (TFT), negative pole and the negative pole of described 4th diode of described 3rd diode are connected the grid of described second thin film transistor (TFT) respectively, the source electrode of described second thin film transistor (TFT) is connected with the positive pole of described 3rd diode, the drain electrode of described second thin film transistor (TFT) is connected with the positive pole of described 4th diode, be positioned at described in the positive pole of described 3rd diode is connected respectively with the positive pole of described tetrode described a plurality of data lines both sides data line or described in be positioned at the sweep trace of described multi-strip scanning line both sides and described public electrode wire.
10. a display panels, is characterized in that, described display panels comprises the described array base palte described in claim 1-9 any one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510458872.7A CN105093739A (en) | 2015-07-30 | 2015-07-30 | Liquid crystal display panel and antistatic array substrate thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510458872.7A CN105093739A (en) | 2015-07-30 | 2015-07-30 | Liquid crystal display panel and antistatic array substrate thereof |
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| Publication Number | Publication Date |
|---|---|
| CN105093739A true CN105093739A (en) | 2015-11-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510458872.7A Pending CN105093739A (en) | 2015-07-30 | 2015-07-30 | Liquid crystal display panel and antistatic array substrate thereof |
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| CN (1) | CN105093739A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107290908A (en) * | 2017-06-23 | 2017-10-24 | 武汉华星光电技术有限公司 | Electrostatic discharge protective circuit and liquid crystal display panel |
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|---|---|---|---|---|
| CN1737883A (en) * | 2004-03-09 | 2006-02-22 | 三星Sdi株式会社 | Flat panel display and manufacturing method thereof |
| US20080123005A1 (en) * | 2006-11-29 | 2008-05-29 | Samsung Electronics Co., Ltd. | Array Substrate and Display Panel Having the Same |
| TW200842471A (en) * | 2007-04-25 | 2008-11-01 | Au Optronics Corp | Active device array substrate |
| CN202550507U (en) * | 2012-03-15 | 2012-11-21 | 京东方科技集团股份有限公司 | Electrostatic protection circuit, array substrate and display device |
| CN102983102A (en) * | 2012-12-04 | 2013-03-20 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, as well as display device |
-
2015
- 2015-07-30 CN CN201510458872.7A patent/CN105093739A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1737883A (en) * | 2004-03-09 | 2006-02-22 | 三星Sdi株式会社 | Flat panel display and manufacturing method thereof |
| US20080123005A1 (en) * | 2006-11-29 | 2008-05-29 | Samsung Electronics Co., Ltd. | Array Substrate and Display Panel Having the Same |
| TW200842471A (en) * | 2007-04-25 | 2008-11-01 | Au Optronics Corp | Active device array substrate |
| CN202550507U (en) * | 2012-03-15 | 2012-11-21 | 京东方科技集团股份有限公司 | Electrostatic protection circuit, array substrate and display device |
| CN102983102A (en) * | 2012-12-04 | 2013-03-20 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, as well as display device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107290908A (en) * | 2017-06-23 | 2017-10-24 | 武汉华星光电技术有限公司 | Electrostatic discharge protective circuit and liquid crystal display panel |
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Application publication date: 20151125 |
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