CN105093003A

CN105093003A - Method for testing characteristic representing crosstalk between high voltage and low voltage

Info

Publication number: CN105093003A
Application number: CN201410216906.7A
Authority: CN
Inventors: 徐帆; 陈曦; 张翼; 程玉华
Original assignee: Shanghai Research Institute of Microelectronics of Peking University
Current assignee: Shanghai Research Institute of Microelectronics of Peking University
Priority date: 2014-05-22
Filing date: 2014-05-22
Publication date: 2015-11-25

Abstract

The invention provides a method for testing an effect of a high-voltage environment to a standard cell library. A working environment in which an SOI low-voltage device and a high-voltage device coexist is considered. According to the method of the invention, through measuring delay of a measured cell and signal fluctuation, detection to the operation state of the cell in a high-voltage environment is realized. Through setting a plurality of distances between the high-voltage device and the low-voltage device, and setting the starting time of the high-voltage device through a buffer, different kinds of effects of the high-voltage environment to a testing unit are tested. A selector is added into a testing chip for reducing number of PADs, thereby realizing a purpose of reducing the area of the chip.

Description

Characterize the method for testing of the mutual crosstalk effect of high-low pressure

Technical field

The invention belongs to chip design field, particularly utilize the method for testing that hyperbaric environment affects SOI standard cell lib.

Background technology

Along with the fast development of integrated circuit, there is increasing problem in traditional silicon technology: the raising of integrated level result in increasing sharply of power consumption in device theory, device architecture and manufacture craft, the thinning dielectric layer that causes of gate oxide is easily breakdown, and these problems all seriously govern the development of integrated circuit.And SOI is as a kind of Fully dielectric isolation technology, there is the advantage that conventional bulk silicon is incomparable.Due to its employing is Fully dielectric isolation structure, and the radioresistance characteristic of SOI device is good, completely eliminates the latch-up of Bulk CMOS circuit, and SOI technology is less than traditional body silicon area.

But only how understanding SOI device carries out designing, manufacturing is inadequate.To general IC deviser, for want of design platform and IP instrument are supported, even if it is also at a loss as to what to do to allow IC deviser want to adopt this technique.Form the industrialization needs chained file relevant to robotization platform in SOI technology, and standard cell lib connects the bridge between integrated circuit (IC) design and manufacturing process.So set up a set of standard cell lib accurately to become a necessary job.

Due to the singularity of SOI technology, the high tension apparatus of SOI can be produced with on a chip with commonplace components, we need to consider that hyperbaric environment is on the impact of library unit, and this patent proposes a kind of test circuit, and this circuit characterizes the working condition of standard block under hyperbaric environment.

Summary of the invention

The present invention proposes the method for testing that a kind of hyperbaric environment affects standard cell lib, consider the working environment that SOI low pressure and high tension apparatus coexist, the method, by measuring the delay of unit under test and the fluctuation of signal, realizes under hyperbaric environment, the detection of test cell working condition.

Arrange and the high tension apparatus of low-voltage device different distance in test chip, by controlling the unlatching of different distance high tension apparatus, measure its impact on low voltage experiment unit, final test result has directive function to deviser.

Consider that the different start-up time of high tension apparatus is different on the impact of test cell, as Fig. 2 high tension apparatus can have impact to the logical value of test cell in start-up time 1 unlatching, high tension apparatus opens the fluctuation affecting test cell signal at start-up time 2.BUF and selector switch are set to control the start-up time of high tension apparatus, to reach the object of test.

In order to reduce the area of test chip, selector switch logic being set at test chip, being controlled the opening and closing of test cell by selector switch, and the start-up time of high tension apparatus.This method can reduce input pin number greatly, thus reaches the object reducing chip area.

Accompanying drawing explanation

Fig. 1 is embodiment of the present invention method of testing schematic diagram;

The different start-up time of Fig. 2 high tension apparatus affects schematic diagram for standard block.

Embodiment

1 as Fig. 1, different test cells is connected with input port, selected the output of test cell by selector control signal control1, high-pressure modular is placed according to the different distance with test cell, controlled the unlatching of different distance high-pressure modular by selector switch control3.

2 as Fig. 2, is controlled the unlatching of different B UF by control2 signal, controls the start-up time of high-pressure modular.

3Set, controls the unlatching of high-pressure modular with input signal co-controlling selector switch 2

4 use control2 controlled selector 2, select 0 BUF, high tension apparatus and to-be-measured cell are opened simultaneously, the start-up time 1 namely shown in Fig. 2.Measure the impact of unlatching for test cell logical value of now high-voltage signal.

5 use control2 controlled selector 3, select multiple BUF, high tension apparatus are opened, the start-up time 2 namely shown in Fig. 2 in the to-be-measured cell signal stabilization moment.The output terminal of direct measurement test cell checks the fluctuation situation of signal.

Claims

1. a testing high voltage environment method that standard block is affected, the impact of the Switch Controller standard block of test different distance high tension apparatus, and high tension apparatus start-up time is for the impact of test cell.

2. the test circuit of testing high voltage device start-up time impact as claimed in claim 1, is characterized in that arranging selection impact damper not at the same level by logical circuit, thus controls the start-up time of high tension apparatus.

3. test circuit as claimed in claim 1, be is characterized in that arranging selector switch logic in test chip inside, is controlled the opening and closing of test cell by selector switch, and the start-up time of high tension apparatus, thus reaches the object reducing chip area.