CN105068951A - On-chip system bus with anisochronous transmission structure - Google Patents

Abstract

The invention discloses an on-chip system bus, comprising a request priority queue, an arbiter group, an address and control signal selector, an internet and an address decoder. A primary device transmits a bus request signal to the address decoder; the address decoder transmits an application signal to the request priority queue according to the bus request signal; the request priority queue latches the application signal and generates a chip selection signal, and transmits the chip selection signal to the internet, and transmits the application signal to the arbiter group at the same time; the arbiter group transmits an arbitration result signal to the internet; the internet selects data and a handshake signal from the primary device to slave device according to the arbitration result signal, and the internet controls the data and the handshake signal from the primary device to slave device according to the chip selection signal. The on-chip system bus of the invention has different transmission time among different primary devices and slave devices on a large-area chip to achieve high-speed, parallel and real-time communication among devices.

Description

A System-on-Chip Bus with Non-isochronous Transfer Structure

technical field

The invention belongs to the field of on-chip communication, in particular to an on-chip system bus with non-isochronous transmission structure.

Background technique

With the development of integrated circuit technology, the SoC requires more processor cores, coprocessor cores and more on-chip peripherals. Moreover, the rapid development of technologies such as multimedia and communication requires a high-speed, parallel, and real-time communication mode between devices on the chip.

In order to pursue a higher transmission rate, the frequency of the system bus is constantly increasing, but because of more functional requirements such as multi-core and multi-peripheral hardware, even with the support of more sophisticated technology, the area of the chip is also constantly expanding, which leads to Discrepancy between on-chip device transfer time and bus frequency. When the various bus systems currently exist are used in high-frequency and high-bandwidth systems in large-area chips, if the data is transmitted in a pipeline, it will result in the use of more pipeline registers and consume a lot of resources; otherwise, it can only reduce Bus clock frequency, which affects the overall performance of the bus.

If there is only one data bus, when two devices are communicating with each other, if other devices want to access another device, although there is no conflict between devices, the device can only wait, or allow higher priority The device interrupted the current communication. A single data bus limits the data throughput of the entire system. Systems with high data throughput requirements require simultaneous communication between multiple groups of devices: as long as it is not because of device correlation (for example, two master devices access a slave device at the same time), You can communicate in parallel.

Figure 1 is a schematic diagram of the connection of on-chip devices in a system of the prior art, wherein slave device 0 (slave 0) can only be accessed by master device 0 and master device 1, and slave device 1 and slave device group 2 can be accessed by all master devices access. Slave 0, slave 1 and slave group 2 can be accessed in parallel by three different masters. The structure 10 in the figure is a simple schematic diagram of the bus. The arbitration mechanism of the bus can make the high-priority devices use the bus first, so the lower-priority devices need to wait. If there is no proper way, when the higher priority devices continuously send out bus requests, the lower priority devices will not get the right to use the bus for a long time. For systems with high real-time requirements, such as communication systems, the bus needs to be able to ensure that a device obtains the right to use the bus within a specified bus cycle.

Contents of the invention

(1) Technical problems to be solved

The object of the present invention is to provide a system-on-chip bus, especially with different transmission times (clock cycles) between different master-slave devices on a large-area chip, so as to realize high-speed, parallel and real-time communication between devices.

(2) Technical solution

The present invention provides a system-on-chip bus for communication between a master device and a slave device, including a request priority queue, an arbiter group, an address and control signal selector, an interconnection network, and an address decoder; wherein,

The master device sends the bus request signal to the address decoder, and sends the corresponding address signal and control signal to the address and control signal selector;

The address decoder sends an immediate request vector to the arbitrator group according to the bus request signal, and simultaneously sends the immediate request vector to a request priority queue;

The request priority queue latches the immediate application vector, generates a chip selection signal, and sends the chip selection signal to the Internet, and at the same time, generates a queue application vector and sends it to the arbitrator group;

The arbitrator group sends an arbitration result signal to the address and control signal selector according to the application signal, and the address and control signal selector selects the address signal and control signal of the master device according to the arbitration result signal and transmits it to the slave device;

The arbitrator group also sends the arbitration result signal to the Internet, and the Internet selects the data and handshake signals from the master device to the slave device according to the arbitration result signal, and the Internet also controls the data and handshake signals from the slave device to the master device direction according to the chip selection signal .

(3) Beneficial effects

1. The present invention provides a system-on-chip bus, in which the transmission cycles between devices are allowed to be different, and the bus frequency is determined by the device with a shorter transmission time, and the path between devices with a transmission distance of more than one bus cycle is determined by multiple The periodic path is constrained, so that the contradiction between the bus frequency and the transmission time between devices on a large-area chip is solved with a unified bus form and the minimum hardware overhead. Therefore, the bus frequency can be higher according to the design requirements; between devices with short transmission time High-speed data transmission can be performed in the bus cycle; there is no need to use pipeline registers and bus agents between devices with long transmission times, reducing resource consumption.

2. The system-on-chip bus provided by the present invention provides a corresponding bus protocol, which is a single-edge pipeline bus protocol, which divides the sending of bus application, address and control signals and the sending of data into two pipeline levels To operate, the key is that no additional bus application operation is required. When applying for the bus, the address and control signal are given, and the next shot receives and sends data according to the handshake signal, so that the single-edge operation ensures high bus frequency, pipeline operation and no additional The bus application time ensures the bus efficiency even when the bus is handed over; in particular, the master device of the multi-cycle path will not affect the response efficiency of the bus and the slave device during non-burst transmission.

3. The system-on-chip bus provided by the present invention has a request priority queue, and the priority of requests is determined by the order of entering the queue, which ensures the real-time performance of device request responses.

Description of drawings

FIG. 1 is a simple schematic diagram of device connections of a system-on-chip in the prior art.

FIG. 2 is a structural diagram of a system-on-chip bus provided by an embodiment of the present invention.

Fig. 3 is a structural diagram of an arbitrator group in an embodiment of the present invention.

Fig. 4 is a schematic diagram of 3-to-3 full interconnection between master and slave devices in an embodiment of the present invention.

Fig. 5 is a structural diagram of an application priority queue in an embodiment of the present invention.

Fig. 6 is an interface block diagram of the master device and the slave device in the embodiment of the present invention.

Fig. 7 is a sequence diagram of one-to-one transmission between master and slave devices in the embodiment of the present invention.

Fig. 8 is a sequence diagram of main line handover in the embodiment of the present invention.

FIG. 9 is a sequence diagram of master devices of a dual-cycle path and a single-cycle path using the bus to read and write each other in an embodiment of the present invention.

FIG. 10 is a timing diagram of a burst write sequence and a bus handover sequence in an embodiment of the present invention.

FIG. 11 is a timing diagram of a burst transmission of a two-cycle path in an embodiment of the present invention.

FIG. 12 is a sequence diagram of multiple master devices competing for a bus at the same time in the embodiment of the present invention.

Detailed ways

The invention provides a system-on-chip bus, which includes a request priority queue, an arbiter group, an address and control signal selector, an interconnection network, and an address decoder; a master device sends a bus request signal to the address decoder, and sends a corresponding The address signal and control signal are sent to the address and control signal selector; the address decoder sends an immediate application vector to the arbitrator group and the request priority queue according to the bus request signal; the request priority queue latches the application signal to generate a chip select signal , and send the chip select signal to the Internet, and at the same time, give the application vector of each slave device group according to the first-in-first-out principle, and the queue empty directly selects the result of the address decoder as the application signal of the current cycle and sends it to the arbitrator group ; The arbitrator group sends an arbitration result signal to the address and control signal selector according to the application signal, and the address and control signal selector selects the address signal and control signal of the master device according to the arbitration result signal, and transmits it to the slave device. The arbiter group also sends an arbitration signal The result signal is sent to the Internet, and the Internet selects the data and handshake signals from the master device to the slave device according to the arbitration result signal, and the Internet also controls the data and handshake signals from the slave device to the master device according to the chip selection signal.

In one embodiment, the system-on-chip bus also includes an address and control signal memory, and the arbiter group also returns a grant signal to the request priority queue, and the bus request signal of the master device enters the request priority queue according to the grant signal. Queue, and at the same time make the address signal and control signal of the master device enter the address and control signal memory.

In one embodiment, the system-on-chip bus further includes a first selector. When the request priority queue is empty, the request priority queue sends a queue empty signal to the control terminal of the first selector, and the first selector directly Select the address signal and control signal sent by the master device to the address and control signal selector, otherwise, the first selector selects the address signal and control signal in the address and control signal memory to the address and control signal selector.

In one embodiment, the system-on-chip bus also includes a second selector. When the request priority queue is empty, the request priority queue sends a queue empty signal to the control terminal of the second selector, and the second selector directly The application signal sent by the address decoder is selected to the arbitrator group, otherwise, the second selector selects the application signal sent by the request priority queue to the arbitrator group.

In one embodiment, the arbitrator group includes one or more arbitrators, and the number of arbitrators is the same as the number of slave devices.

In one embodiment, the arbitration logic in the arbiter is a priority encoder.

In one embodiment, the system-on-chip bus further includes an arbitration result register, and the arbitrator group first sends the arbitration result signal to the arbitration result register, and then sends the arbitration result signal to the interconnection through the arbitration result register. network.

In one embodiment, after sending the signal in this cycle, the master device directly sends write data to the slave device in the next cycle without waiting for the authorization signal, and monitors the handshake signal sent by the slave device.

In one embodiment, the system-on-chip bus transmits the signal sent by the master device to the slave device through one or more clock cycles.

In one embodiment, the control signal sent by the master device carries timing information of the master device, and the response period of the slave device is controlled by the timing information of the master device, so as to match the transmission rate between the master device and the slave device. The on-chip system bus of the present invention has different transmission times (clock cycles) between different master-slave devices on a large-area chip, and realizes high-speed, parallel and real-time communication between devices.

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

Fig. 2 is the structural diagram of system on chip bus that the present invention provides, as shown in Fig. 2, bus 10 comprises request priority queue 201, arbitrator group 202, address and control signal memory 203, address and control signal selector 204, arbitration Result register 205, interconnection network 206, address decoder 207, first selector 208 and second selector 209 (in the lower left corner of the structural block diagram in the figure, there is a clock input triangle mark to indicate that this structure is sequential logic or there is sequential logic therein , this notation applies to other figures in this article). Each main equipment can send bus request signal at any moment, and the address and the control signal of this request are provided simultaneously; Address decoder 207 provides immediate request vector to corresponding slave equipment (group) according to the address that main equipment provides, And send the immediate application vector to the request priority queue 201, and use it as a chip selection signal to control data selection from the device side to the master device side after latching, and at the same time request the priority queue to give the queue request vector according to the principle of first-in-first-out ; For each slave device (group), according to the "queue empty" signal corresponding to the slave device queue in the request priority queue 201, if it is empty, then select the immediate application vector, if it is not empty, then select the queue application vector, and select the result as an arbiter The input of group 202 is the bus request signal; after arbitration, the result of each arbitrator returns the response signal to the request priority queue 201, enabling the request that is not granted the bus immediately to enter the request priority queue 201, and the relevant address/ The control signal enters the address and control signal memory 203, and the address and control signal of the master device granted to the bus is selected and transmitted to each slave device port by the arbitration result control address and control signal selector 204, and is latched by the slave device. It is convenient to read and write data in the next cycle; at the same time, the arbitration result will also be locked in the arbitration result register 205, which is used for the Internet 206 to select the data (write data) and handshake signal from the master device to the slave device direction, and lock it in the request priority queue 201 The chip select signal will control the data (read data) and handshake signals of the Internet 206 from the device to the master device. In the next operation cycle when the master device sends the request signal, it can write data or read data from the slave device, and at the same time give the next bus request. Wherein, the number of arbitrators in the arbiter group 202 is the same as the number of current slave devices (groups), and the corresponding relationship between the two is as shown in the corresponding relationship between arbitrators and slave devices (groups) in FIG. 1 .

FIG. 3 is an internal structural diagram of the arbiter 202 in this embodiment. First, the input of each arbitrator is an application vector whose bit width is the same as the number of master devices that can access the slave device (group), and the value in the vector is "high", indicating that the corresponding master device needs to apply for the slave device (group) access, and the arbitration logic is to select a master device from these applications to give the bus. Because of the existence of the bus application priority queue 201, the main function of the arbitration logic here is to select one of the master devices that apply for the bus at the same time, so the arbitration logic can be a relatively simple fixed priority arbitration logic, such as a priority encoder . The output of each arbiter is a vector with the same bit width as the input, and the output corresponding to the valid input is "one-hot", that is, only one master device is granted to the bus; the invalid input (0 vector) corresponds to the invalid output (0 vector). The output of each arbiter will control the input selection of the corresponding slave device (group), and the data/control signal of the authorized master device can drive the data/control bus of the slave device (group). For the same master device, each arbiter will give an authorization signal, and the "OR" operation of all the authorization bits corresponding to the master device is the authorization signal of the master device, which is mainly used to control the storage logic on the bus: Request priority queue 201 , address and control signal memory 203 .

FIG. 4 is an example diagram of a 3-to-3 full interconnection of the Internet 206 in this embodiment. Wherein, the value of the arbitration result register 205 is used to select the selector from the master device to the slave device, and the chip select signal in the request priority queue 201 is used to select the selector from the slave device to the master device. Wherein the address and control signal selector 204 is similar to the selector in the right column in Fig. 4, the difference is that the selection signal of the address and control signal selector 204 is not the arbitration result after registration, but is currently generated by the arbitrator Arbitration results.

FIG. 5 is a structural diagram of the request priority queue 201 in this embodiment. It includes a first memory 501, a second memory 502 and a third memory 503, wherein the first memory 201 is used to store valid address decoding values, and the storage size is m×n bits (m represents the number of master devices, n represents the number of slaves number of device groups, the same below); the second memory 502 is used to store the maximum priority value of the slave device group, and the storage size is n×log ₂ m, that is, each slave device group corresponds to a memory whose width is log ₂ m; the third memory The 503 is used to store the priority value of the master device, and the storage size is m×log ₂ m, that is, each master device corresponds to a log ₂ m memory. The initial value of the memory 502 is 0, which means that the request queue corresponding to the slave device group is empty, and the queue empty signal generated thereby is used to control the first selector 208 and the second selector 209 . The third memory 503 is the priority of each master device. When there is a request that is not immediately authorized and needs to be listed, the "self-increment 1" value of the second memory 502 of the application object is selected as the priority value of the master device. The second memory 502 also needs to "increment by 1". When the queue is output, only the request of the master device whose priority value is equal to "1" is selected as output. When the request for a certain slave device group in the output is unique, and the slave device group gives an effective "SValid" signal, then the corresponding second memory 502 needs to "decrement by 1", and the "self-decrement by 1" signal passes Chip selection signal selection, enabling the priority value of the master device to "decrement by 1". For the second memory 502, when the "self-increment 1" signal is the same as the "self-decrement 1" signal ("exclusive OR"), the original value is maintained.

The usage of this bus, ie its bus protocol, is described below.

From the master device initiating a bus request to using the bus to transmit data, it is divided into two stages. The first stage is the master device initiating the request, and the second stage is the data transmission between the master and slave devices. Phase 1 and phase 2 are two pipeline stages in the bus operation, that is, when the first request is in phase 2, the master device can give the signal of phase 1 of the second request (for the same slave device group) at the same time.

S1 The master device sends request, address and control signals, and at the same time judges the valid signal of the input slave device, which belongs to the first stage;

S2 After the slave device is effectively high, in the next clock cycle, if it is a write operation, the master device sends the write data and gives the master device a valid signal. If it is a read operation, the master device latches the read data when the slave device's valid signal is high. , which belongs to stage two;

While S3 is in progress in S2, the master device can simultaneously perform S1 for the next bus request;

While S4 is in S1, the slave device will receive the address and control signal from the master device to latch, which belongs to phase one;

While S5 is in S2, according to the address and control signal, if it is a write operation, the slave device will write the write data into the corresponding address when the master device valid signal is high, and if it is a read operation, it will send the data of the corresponding address and the slave device is valid signal, which belongs to phase two;

While S6 is in progress in S5, the slave device can proceed to S4 according to the next S1 performed by the master device.

Different from other on-chip bus protocols, other on-chip buses need a separate bus application link. After the bus is authorized, the device occupies the bus, sends address signals, control signals, and reads and writes data; and in the present invention, the bus application and address, control The signal is sent at the same time as phase 1. As long as there is no application vector corresponding to the master device in the current application priority queue, it will automatically enter phase 2 to send write data or receive read data. If the handshake signal between the two parties is valid, the request will end (burst operation except).

The operation cycle of each device is different, and the specific operation time is determined by the transmission time between the master device and the bus control and selection logic. If the time required for the signal transmission of the master device to a specific structure exceeds the period required by the current bus frequency, the device will automatically down-frequency to the corresponding frequency to sample data and handshake signals from the bus. When a slave device receives a burst request from the master device of the multi-cycle path, the slave device also automatically reduces the frequency to the corresponding frequency for data and handshake signal sampling.

Fig. 6 is an interface block diagram of the master device and the slave device in the present invention. The data bit width is determined according to the actual bit width requirements of the device, and the general bit width is 16/32/64/128 bits. The control signal (Ctrl) at least includes control information such as read/write, burst, and timing information of the master device. The chip select signal (Sel) of the slave device is used in the slave device group. If a certain arbiter corresponds to a single slave device, the slave device does not need this signal.

Table 1 is a specific description of the master-slave device interface signals.

Table 1

The timing diagram shown in FIG. 7 is a timing diagram for accessing the slave device (group) by a certain master device when the corresponding request queue is empty for a certain slave device (group). In the figure, the master device continuously sends out four non-burst read/write requests, in which the SValid signal is a handshake signal sent by the slave device, and the bus and the master device determine whether the current data ends the current operation or maintains the previous cycle by reading the signal The data. Wherein the Req signal indicates that the current master device proposes a valid bus application, and this signal is mainly used as one of the enqueue enabling signals of the application priority queue 201, if the request is not authorized, it will enter the request queue. In the figure, since the request for address C cannot be responded in time, the master device needs to maintain its request for address D while maintaining the write data output, because the current request cannot enter the queue when the SValid signal is low.

FIG. 8 is a schematic diagram of a timing sequence of two master devices handing over the bus for a certain slave device (group) and the corresponding request queue is empty. In the figure, the two master devices issue bus requests respectively in two consecutive cycles, and successfully obtain the right to use the bus without waiting.

FIG. 9 is a timing diagram of master devices of a double-cycle path and a single-cycle path using the bus to read and write each other. The signal with the suffix "_p1" indicates the value of the signal close to the output terminal, and "_p2" indicates the value close to the input terminal. "WData#1_p1" indicates the write data line close to the master device 1. After the data enters the second cycle, the selector of the arbitrator drives the "WData" bus; "RData#1_p2" indicates the read data line close to the master device 1. It is an extension of the "RData" bus in the master-only segment 1. It can be seen from the figure that when the master device of the double-cycle path initiates a non-burst request, the occupation time of the slave device and the bus is the same as that of the master device of the single-cycle path. However, the master device of the multi-cycle path needs to use four bus cycles to confirm the end of the bus access, and then proceed to the next bus application.

FIG. 10 is a schematic diagram of a burst write sequence and bus handover. In the figure, the master device 1 initiates a burst write request and is responded to, and the master device sends a burst end signal "BLast" to end the burst. During burst transmission, both the master device and the slave device need to give a handshake signal, that is, the "MValid" and "SValid" signals in the figure. As long as one of the signals is low, it means that the current transmission data is invalid, and the current data needs to be transmitted again . The figure also shows a simple bus competition. During the burst transmission process of the master device 1, the master device 2 makes a bus request. Since the bus is busy, the handshake signal from the bus to the master device 2 is low, so the master device needs to maintain the data , until the handshake signal is high. When the master device 1 gives the burst end signal, the master device can send another request for the slave device at the same time. In the present invention, due to the request priority queue 201, the bus will give priority to the request of the corresponding master device 2, and then Respond to the second request of master device 1.

Figure 11 is a burst transfer timing diagram for a two-cycle path. It can be seen from the figure that there is basically no two bus cycles to transmit a data, but the application signal, handshake signal, and burst end signal are all given in the form of a single cycle, so after a data is sent, it starts from the second clock cycle (Included) Start sampling the handshake signal, and if it is valid, new data will be sent in the next cycle. Therefore, the transmission time of a data is greater than or equal to 2 cycles, not a positive integer multiple of 2. It is worth mentioning that if the slave device is a high-speed device among the two devices transmitted by the multi-cycle path, it is not recommended to use the burst transfer method for transmission. It is recommended to use the non-burst bus access method, which will not affect the slave device. impact on operating efficiency.

Fig. 12 is a timing diagram of multiple masters contending for a bus at the same time. The figure shows the competition of three master devices for the same slave device group. For the simultaneous applications of the masters 1, 2, 3, the bus first responds to the request of the master 1, and then the requests of the masters 2, 3 will enter the request priority queue 201 . Although the master device 1 sends another application in the second operation cycle, because there are still applications from the master devices 2 and 3 in the application queue, the second application of the master device 1 will enter the request queue. The right to use the second cycle of the bus is granted to the master device 2 after request arbitration to the master device 2 and 3 . In the case where the master device is waiting for the bus authorization, if it is a write operation, the master device is required to maintain the data of the write data port, and know that a valid handshake signal from the bus is sampled.

The above specific embodiments have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention, and are not intended to limit the present invention. Within the spirit and principles of the present invention, any modifications, equivalent replacements, improvements, etc., shall be included within the protection scope of the present invention.

Claims (11)

1. a system-on-chip bus (10), used for communication between master equipment and slave equipment, is characterized in that, comprises request priority queue (201), arbitrator group (202), address and control signal selector ( 204), Internet (206) and address decoder (207); wherein, The master device sends a bus request signal to the address decoder (207), and sends a corresponding address signal and control signal to the address and control signal selector (204); The address decoder (207) sends the immediate request vector to the arbitrator group according to the bus request signal, and simultaneously sends the immediate request vector to the request priority queue (201); The request priority queue (201) latches the instant application vector, generates a chip selection signal, and sends the chip selection signal to the Internet (206), and at the same time, generates a queue application vector and sends it to the arbitrator group (202); The arbitrator group (202) sends an arbitration result signal to the address and control signal selector (204) and the Internet according to the application signal; The address and control signal selector (204) selects the address signal and control signal of the master device according to the arbitration result signal, and transmits them to the slave device; The interconnection network (206) selects data and handshake signals from the master device to the slave device direction according to the arbitration result signal, and controls data and handshake signals from the slave device to the master device direction according to the chip selection signal. 2. system-on-chip bus (10) according to claim 1, is characterized in that, also comprises an address and control signal memory (203), and described arbitrator group (202) also returns a grant signal to request priority queue (201), making the bus request signal of the master device enter the request priority queue according to the authorization signal (201), and simultaneously make the address signal and the control signal of the master device enter the address and control signal memory (203). 3. The system-on-chip bus (10) according to claim 2, further comprising a first selector (208), when the request priority queue (201) was empty, the request priority The queue (201) sends a queue empty signal to the control terminal of the first selector, and the first selector directly selects the address signal and the control signal sent by the master device to the address and control signal selector (204) , otherwise, the first selector selects the address signal and control signal in the address and control signal memory (203) to the address and control signal selector (204). 4. system on chip bus (10) according to claim 1, is characterized in that, also comprises a second selector, when described request priority queue (201) is empty, described request priority queue (201 ) sends a queue empty signal to the control end of the second selector, and the second selector directly selects the immediate request vector sent by the address decoder (207) to the arbiter group (202), otherwise, the The second selector selects the queue request vector sent by the request priority queue (201) to the arbitrator group (202). 5. The system-on-chip bus (10) according to claim 1, characterized in that the arbiter group (202) comprises at least one arbiter, and the number of the arbitrators is the same as the number of the slave devices. 6. The system-on-chip bus (10) according to claim 5, characterized in that, the arbitration logic in the arbiter is a priority encoder. 7. system on chip bus (10) according to claim 1, is characterized in that, also comprises arbitration result register (205), and described arbitrator group (202) sends described arbitration result signal to described arbitration result register earlier (205), and then send an arbitration result signal to the Internet (206) through the arbitration result register (205). 8. The system-on-chip bus (10) according to claim 1, characterized in that, the request priority queue (201) comprises: a first memory (501), a second memory (502) and a third memory (503) ), wherein the first memory (501) is used to store an effective address decoding value, the second memory (502) is used to store the maximum priority value of the slave device group, and the third memory (503) is used for Stores the master priority value. 9. system on chip bus (10) according to claim 1, is characterized in that, it carries out signal transmission by following agreement: After sending the signal in this cycle, the master device directly sends write data to the slave device in the next cycle without waiting for the authorization signal, and monitors the handshake signal sent by the slave device. 10. The system-on-chip bus (10) according to claim 1, characterized in that, it enables the signal sent by the master device to be transmitted to the slave device through one or more clock cycles. 11. The system-on-chip bus (10) according to claim 1, wherein the control signal sent by the master device has master device timing information, and the response of the slave device is controlled by the master device timing information period to match the transfer rate between the master and the slave.