[go: up one dir, main page]

CN105048966A - Multi-phase digital down conversion method for GHz high-speed sampling signal - Google Patents

Multi-phase digital down conversion method for GHz high-speed sampling signal Download PDF

Info

Publication number
CN105048966A
CN105048966A CN201510324924.1A CN201510324924A CN105048966A CN 105048966 A CN105048966 A CN 105048966A CN 201510324924 A CN201510324924 A CN 201510324924A CN 105048966 A CN105048966 A CN 105048966A
Authority
CN
China
Prior art keywords
sigma
infin
signal
signals
delta
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510324924.1A
Other languages
Chinese (zh)
Inventor
赵孔瑞
张超
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CETC 41 Research Institute
Original Assignee
CETC 41 Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CETC 41 Research Institute filed Critical CETC 41 Research Institute
Priority to CN201510324924.1A priority Critical patent/CN105048966A/en
Publication of CN105048966A publication Critical patent/CN105048966A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

本发明涉及信号处理技术领域,具体涉及一种千兆赫高速采样信号的多相数字下变频方法,利用多相分解思想,将GHz及其以上高速采样信号多相分解为多个低采样率的子信号序列,并对每个子序列分别进行正交混频和多相滤波处理,最后在低工作频率上通过数值计算实现了高速采样信号的正交数字下变频处理,显著降低了高速采样信号正交数字下变频处理的复杂度;另外,本发明通过结构扩展和参数灵活设置,可以实现任意带宽、任意中频信号的数字下变频处理。

The present invention relates to the technical field of signal processing, in particular to a multi-phase digital down-conversion method for gigahertz high-speed sampling signals, which uses the idea of multi-phase decomposition to multi-phase decompose high-speed sampling signals of GHz and above into multiple low-sampling-rate sub- Signal sequence, and each sub-sequence is processed by quadrature frequency mixing and polyphase filtering. Finally, the quadrature digital down-conversion processing of high-speed sampling signal is realized through numerical calculation at low operating frequency, which significantly reduces the high-speed sampling signal quadrature The complexity of digital down-conversion processing; in addition, the present invention can realize digital down-conversion processing of any bandwidth and any intermediate frequency signal through structure expansion and flexible setting of parameters.

Description

一种千兆赫高速采样信号的多相数字下变频方法A multi-phase digital down-conversion method for gigahertz high-speed sampling signals

技术领域technical field

本发明涉及信号处理技术领域,具体涉及一种千兆赫高速采样信号的多相数字下变频方法。The invention relates to the technical field of signal processing, in particular to a multi-phase digital down-conversion method for gigahertz high-speed sampling signals.

背景技术Background technique

数字下变频的基本功能是将速率较高的数字中频信号下变频为数字基带信号,并通过抽取降低信号的采样速率。图1是数字下变频的基本模型。图中将高速A/D转换器的输出信号送入数字下变频器,经两个相乘器所构成的数字正交混频器后,将输入的数字信号和复正弦信号产生器产生的正交正弦信号相乘,相乘结果为I、Q两路信号;再分别经抽取和滤波后输出数据速率降低了的数字基带信号。The basic function of digital down-conversion is to down-convert the high-speed digital intermediate frequency signal into a digital baseband signal, and reduce the sampling rate of the signal by decimation. Figure 1 is the basic model of digital down-conversion. In the figure, the output signal of the high-speed A/D converter is sent to the digital down-converter, and after passing through the digital quadrature mixer composed of two multipliers, the input digital signal and the positive signal generated by the complex sinusoidal signal generator are combined. The quadrature sinusoidal signals are multiplied, and the result of the multiplication is two signals of I and Q; and then the digital baseband signal with a reduced data rate is output after being extracted and filtered respectively.

假定A/D采样后的中频输入信号为,在数字下变频的基本模型中首先与数字本振信号进行乘积,得到同相信号和正交信号,即Assuming that the intermediate frequency input signal after A/D sampling is, in the basic model of digital down-conversion, it is firstly multiplied with the digital local oscillator signal to obtain the in-phase signal and the quadrature signal, namely

xc(n)=x(n)cos(2πf0n)(1)x c (n)=x(n)cos(2πf 0 n)(1)

xs(n)=x(n)sin(2πf0n)(2)x s (n)=x(n)sin(2πf 0 n)(2)

再经过抽取滤波之后,得到I通道和Q通道的输出结果:After decimation and filtering, the output results of the I channel and the Q channel are obtained:

xI(n)=xc(n)h(n)(3)x I (n) = x c (n) h (n) (3)

xQ(n)=xs(n)h(n)(4)x Q (n)=x s (n)h(n)(4)

上述过程便是传统的数字下变频方案。The above process is the traditional digital down-conversion scheme.

对高速采样的宽带信号抽取滤波而言,存在着难以调和的矛盾:For high-speed sampling broadband signal decimation and filtering, there are contradictions that are difficult to reconcile:

(1)高倍抽取与信号高保真度之间的矛盾。对高速采样信号进行高倍抽取,可以降低信号数据速率,进而降低后续滤波等处理的实现难度。但是从信号时域测量角度,被测信号的时域特性要尽可能无失真的接收和存储,要求信号采样率尽可能高。(1) The contradiction between high-power extraction and high-fidelity signal. High-magnification decimation of high-speed sampling signals can reduce the signal data rate, thereby reducing the difficulty of subsequent processing such as filtering. However, from the perspective of signal time domain measurement, the time domain characteristics of the measured signal should be received and stored without distortion as much as possible, and the signal sampling rate is required to be as high as possible.

(2)高倍抽取与大分析带宽之间的矛盾。高倍抽取降低信号采样速率,增加数字下变频在工程上的可实现性,但是高达500MHz的分析带宽要求信号采样速率要尽可能高,从而避免欠采样导致信号混叠失真。(2) The contradiction between high-power extraction and large analysis bandwidth. High decimation reduces the signal sampling rate and increases the engineering feasibility of digital down-conversion, but the analysis bandwidth of up to 500MHz requires the signal sampling rate to be as high as possible to avoid signal aliasing and distortion caused by undersampling.

另外,在FPGA硬件平台上实现图1所示的经典数字下变频会遇到如下几个问题:In addition, implementing the classic digital down-conversion shown in Figure 1 on the FPGA hardware platform will encounter the following problems:

(1)中频信号采样速率较高时(大于200MHz),FPGA无法用普通I/O引脚接收;(1) When the sampling rate of the intermediate frequency signal is high (greater than 200MHz), the FPGA cannot receive it with ordinary I/O pins;

(2)用常用的查表法无法实现高速NCO;(2) High-speed NCO cannot be realized with the commonly used look-up table method;

(3)混频器用到的高速乘法器无法实现;(3) The high-speed multiplier used in the mixer cannot be realized;

(4)抽取滤波器中的高速乘法器和加法器实现困难。(4) It is difficult to realize the high-speed multiplier and adder in the decimation filter.

综上可知,传统数字下变频方法已经不适用与大带宽高速采样信号的处理,必须采用信号处理新结构和新方法。In summary, the traditional digital down-conversion method is no longer applicable to the processing of large-bandwidth and high-speed sampling signals, and new structures and methods for signal processing must be adopted.

发明内容Contents of the invention

针对现有技术存在的缺陷,本发明的目的在于提出一种千兆赫高速采样信号的多相数字下变频方法,通过将输入信号和本振信号进行多相分解,对M组输入信号和本振信号的并行子序列进行混频,以降低每组子序列信号的数据速率,在低工作频率上实现高速采样信号的正交混频处理。In view of the defects in the prior art, the purpose of the present invention is to propose a multi-phase digital down-conversion method for gigahertz high-speed sampling signals. The parallel sub-sequences of the signals are mixed to reduce the data rate of each group of sub-sequence signals, and realize the quadrature mixing processing of high-speed sampling signals at a low operating frequency.

为达上述目的,一方面,本发明提供一种千兆赫高速采样信号的多相数字下变频方法,包括:In order to achieve the above object, on the one hand, the present invention provides a multi-phase digital down-conversion method for gigahertz high-speed sampling signals, including:

将数字混频器的中频输入信号x(n)等延迟分解为M项:Decompose the delay of the IF input signal x(n) of the digital mixer into M terms:

x ( n ) = Σ i = 0 M - 1 x i ( n ) ; M为正整数; x ( no ) = Σ i = 0 m - 1 x i ( no ) ; M is a positive integer;

将所述混频本振信号Lo(n)等延迟分解为M项:The delays such as the mixed frequency local oscillator signal Lo(n) are decomposed into M items:

LoLo (( nno )) == ΣΣ qq == 00 Mm -- 11 LoLo qq (( nno )) ;;

将xi(n)和Loq(n)一一对应进行正交混频,得到M个输出信号yi(n);Carry out quadrature mixing with x i (n) and Lo q (n) in one-to-one correspondence to obtain M output signals y i (n);

将该M个输出信号yi(n)等效为y(n):The M output signals y i (n) are equivalent to y(n):

ythe y (( nno )) == xx (( nno )) ×× LoLo (( nno )) == ΣΣ ii == 00 Mm -- 11 xx ii (( nno )) ×× ΣΣ qq == 00 Mm -- 11 LoLo qq (( nno )) == ΣΣ ii == 00 Mm -- 11 xx ii (( nno )) ×× LoLo ii (( nno )) == ΣΣ ii == 00 Mm -- 11 ythe y ii (( nno )) ..

另一方面,本发明提供一种千兆赫高速采样信号的多相数字下变频电路,包括:On the other hand, the present invention provides a multi-phase digital down-conversion circuit for gigahertz high-speed sampling signals, including:

M组数字下变频电路,用于分别对M组中频输入信号xi(n)与M组混频本振信号Loq(n)一一对应进行正交混频;M为正整数,i∈(0,M-1),q∈(0,M-1);M sets of digital down-conversion circuits are used to perform quadrature mixing on M sets of intermediate frequency input signals x i (n) and M sets of mixed frequency local oscillator signals Lo q (n) in one-to-one correspondence; M is a positive integer, i∈ (0, M-1), q ∈ (0, M-1);

M组多相滤波器,用于分别对M组正交混频后的信号进行抽取和滤波;M sets of polyphase filters are used to extract and filter the M sets of quadrature mixed signals respectively;

其中,每相邻两组中频输入信号xi(n)之间,以及每相邻两组混频本振信号Loq(n)之间,间隔相同的时钟周期。Wherein, the interval between each adjacent two groups of intermediate frequency input signals x i (n) and between each adjacent two groups of mixing local oscillator signals Lo q (n) is the same clock period.

本发明能够达到以下有益效果:The present invention can achieve following beneficial effect:

本发明利用多相分解思想,将GHz及其以上高速采样信号多相分解为多个低采样率的子信号序列,并对每个子序列分别进行正交混频和多相滤波处理,最后在低工作频率上通过数值计算实现了高速采样信号的正交数字下变频处理,显著降低了高速采样信号正交数字下变频处理的复杂度;另外,本发明通过结构扩展和参数灵活设置,可以实现任意带宽、任意中频信号的数字下变频处理。The present invention uses the idea of polyphase decomposition to polyphase decompose GHz and above high-speed sampling signals into a plurality of sub-signal sequences with low sampling rates, and perform quadrature mixing and polyphase filtering on each sub-sequence respectively, and finally On the working frequency, the orthogonal digital down-conversion processing of the high-speed sampling signal is realized through numerical calculation, which significantly reduces the complexity of the high-speed sampling signal orthogonal digital down-conversion processing; in addition, the present invention can realize arbitrary Wide bandwidth, digital down-conversion processing of any intermediate frequency signal.

附图说明Description of drawings

为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

图1是现有技术中数字下变频的基本模型示意图;Fig. 1 is a schematic diagram of a basic model of digital down-conversion in the prior art;

图2是本实施例一种千兆赫高速采样信号的多相数字下变频方法的流程图;Fig. 2 is a flow chart of a multi-phase digital down-conversion method for a gigahertz high-speed sampling signal in this embodiment;

图3是本实施例一种千兆赫高速采样信号的多相数字下变频电路的结构图;Fig. 3 is a structural diagram of a multi-phase digital down-conversion circuit of a gigahertz high-speed sampling signal in the present embodiment;

图4是宽带高速采样信号并行多组多相滤波实现框图。Fig. 4 is a block diagram for implementing parallel multi-group polyphase filtering of broadband high-speed sampling signals.

具体实施方式Detailed ways

下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

本发明利用多相并行处理技术主要解决了高速采样信号的数字混频的以下2个问题:The present invention mainly solves the following two problems of digital mixing of high-speed sampling signals by utilizing multi-phase parallel processing technology:

1、GHz及以上高速采样信号的数字正交混频问题。1. Digital quadrature mixing of GHz and above high-speed sampling signals.

本发明采用多相分解方法改变高速采样信号正交混频结构,在硬件低时钟速率下实现了高速采样信号的正交混频,解决了传统单通道正交混频方法无法对GHz及以上高速采样信号正交混频的问题。The invention adopts the polyphase decomposition method to change the quadrature mixing structure of the high-speed sampling signal, realizes the quadrature mixing of the high-speed sampling signal at a low hardware clock rate, and solves the problem that the traditional single-channel quadrature mixing method cannot perform high-speed sampling at GHz and above. The problem of quadrature mixing of sampled signals.

2、GHz及以上高速采样宽带信号的多相滤波问题2. Polyphase filtering of high-speed sampling broadband signals at GHz and above

本发明的关键在于应用输入信号和本振信号多相分解的思想,将高速采样的输入信号和本振信号表示成M组子序列信号的叠加,其中每一组子序列信号由高速采样输入信号和本振信号每个M个依次延迟的序列值组成,从而将输入信号和本振信号进行多相分解,降低了每组子序列信号的数据速率(与原高速采样信号相比,采样速率降低了M倍)。通过对M组输入信号和本振信号的并行子序列进行混频,在低工作频率上实现高速采样信号的正交混频处理。The key of the present invention is to apply the idea of polyphase decomposition of input signal and local oscillator signal, and express the high-speed sampling input signal and local oscillator signal as the superposition of M groups of sub-sequence signals, wherein each group of sub-sequence signals is composed of high-speed sampling input signal It is composed of each M sequentially delayed sequence values of the local oscillator signal, so that the input signal and the local oscillator signal are polyphase decomposed, and the data rate of each group of sub-sequence signals is reduced (compared with the original high-speed sampling signal, the sampling rate is reduced M times). By mixing M groups of input signals and parallel subsequences of local oscillator signals, quadrature mixing processing of high-speed sampling signals is realized at low operating frequencies.

实施例一Embodiment one

图2为本实施例一种千兆赫高速采样信号的多相数字下变频方法的流程图,如图所示,包括:Fig. 2 is a flow chart of a multi-phase digital down-conversion method for gigahertz high-speed sampling signals in this embodiment, as shown in the figure, including:

步骤201,将数字混频器的中频输入信号x(n)等延迟分解为M项:Step 201, decomposing delays such as the intermediate frequency input signal x(n) of the digital mixer into M items:

x ( n ) = Σ i = 0 M - 1 x i ( n ) ; M为正整数; x ( no ) = Σ i = 0 m - 1 x i ( no ) ; M is a positive integer;

假设数字混频器的输入信号为x(n),混频本振信号为Lo(n)。输入信号和本振信号的采样周期为Ts,采样频率为fs。则输入信号x(n)可以表示为Suppose the input signal of the digital mixer is x(n), and the mixed local oscillator signal is Lo(n). The sampling period of the input signal and the local oscillator signal is T s , and the sampling frequency is f s . Then the input signal x(n) can be expressed as

xx (( nno )) == ΣΣ kk == -- ∞∞ ∞∞ xx cc (( kTkT sthe s )) δδ [[ (( nno -- kk )) TT sthe s ]] -- -- -- (( 11 ))

其中,xc(kTs)为连续时间信号xc(t)的采样;δ(·)为狄拉克函数。Among them, x c (kT s ) is the sampling of the continuous time signal x c (t); δ(·) is the Dirac function.

为降低输入信号的数据速率,将输入信号x(n)进行多相分解,分解为M组子序列信号的叠加。令k=mM+i,x(n)通过分解可以表为以下形式In order to reduce the data rate of the input signal, the input signal x(n) is decomposed into multiple phases, and decomposed into the superposition of M groups of sub-sequence signals. Let k=mM+i, x(n) can be expressed as the following form through decomposition

xx (( nno )) == ΣΣ kk == -- ∞∞ ∞∞ xx cc (( kTkT sthe s )) δδ [[ (( nno -- kk )) TT sthe s ]] == ΣΣ ii == 00 Mm -- 11 ΣΣ mm == -- ∞∞ ∞∞ xx cc [[ mMTMMT sthe s ++ iTi sthe s ]] δδ [[ (( nno -- mMmM -- ii )) TT sthe s ]] == ΣΣ ii == 00 Mm -- 11 xx ii (( nno )) -- -- -- (( 22 ))

其中,in,

xx ii (( nno )) == ΣΣ mm == -- ∞∞ ∞∞ xx cc [[ mMTMMT sthe s ++ iTi sthe s ]] δδ [[ (( nno -- mMmM -- ii )) TT sthe s ]] == ΣΣ mm == -- ∞∞ ∞∞ xx cc [[ mm (( mTmT sthe s )) ++ iTi sthe s ]] δδ [[ (( nno -- mMmM )) TT sthe s -- iTi sthe s ]] ii == 0,20,2 ,, L ML M -- 11 -- -- -- (( 33 ))

由xi(n)的表达式可见,xi(n)可以看作采样周期为MTs、时间偏移为iTs的信号,xi(n)可以看做xi+1(n)的延迟。因此,公式(2)可以看作是信号x(n)的多相分解。此外,与信号x(n)相比,xi(n)的采样速率降低了M倍,即fs/M。From the expression of xi (n), it can be seen that xi (n) can be regarded as a signal with a sampling period of MT s and a time offset of iT s , and xi (n) can be regarded as the signal of xi+1 (n) Delay. Therefore, formula (2) can be regarded as a polyphase decomposition of signal x(n). In addition, compared with the signal x(n), the sampling rate of x i (n) is reduced by M times, ie f s /M.

步骤202,将所述混频本振信号Lo(n)等延迟分解为M项:Step 202, decomposing delays such as the mixed frequency local oscillator signal Lo(n) into M items:

LoLo (( nno )) == ΣΣ qq == 00 Mm -- 11 LoLo qq (( nno )) ;;

同理,假设本振信号Lo(n)的频率为f0,初始相位为本振信号也可以多相分解表示为Similarly, suppose the frequency of the local oscillator signal Lo(n) is f 0 , and the initial phase is The local oscillator signal can also be decomposed into multiple phases and expressed as

LoLo (( nno )) == ΣΣ ll == -- ∞∞ ∞∞ LoLo cc (( lTlT sthe s )) δδ [[ (( nno -- ll )) TT sthe s ]] == ΣΣ qq == 00 Mm -- 11 ΣΣ pp == -- ∞∞ ∞∞ LoLo cc [[ pMTpMT sthe s ++ qTwxya sthe s ]] δδ [[ (( nno -- pMpM -- qq )) TT sthe s ]] == ΣΣ qq == 00 Mm -- 11 LoLo qq (( nno )) -- -- -- (( 44 ))

其中,in,

LoLo qq (( nno )) == ΣΣ pp == -- ∞∞ ∞∞ LoLo cc [[ pMTpMT sthe s ++ qTwxya sthe s ]] δδ [[ (( nno -- pMpM -- qq )) TT sthe s ]] == ΣΣ pp == -- ∞∞ ∞∞ LoLo cc [[ pp (( MTMT sthe s )) ++ qTwxya sthe s ]] δδ [[ (( nno -- pMpM )) TT sthe s -- qq TT sthe s ]] -- -- -- (( 55 ))

公式(4)表示本振信号Lo(n)经多相分解为M组子序列本振信号的叠加。Loq(n)可以看作采样周期为MTs、初始相位偏移为2πf0qTs的信号,Loq(n)的数据采样频率降低了M倍。因此,Loq(n),q=0,2,LM-1之间可以看作采样周期(或频率),初始相位差为2πf0TsFormula (4) expresses that the local oscillator signal Lo(n) is decomposed into M groups of subsequence superposition of local oscillator signals after polyphase decomposition. Lo q (n) can be regarded as a signal with a sampling period of MT s and an initial phase offset of 2πf 0 qT s , and the data sampling frequency of Lo q (n) is reduced by M times. Therefore, Lo q (n), q=0, 2, and LM-1 can be regarded as the sampling period (or frequency), and the initial phase difference is 2πf 0 T s .

步骤203,将xi(n)和Loq(n)一一对应进行正交混频,得到M个输出信号yi(n);Step 203, perform quadrature mixing with x i (n) and Lo q (n) one by one, to obtain M output signals y i (n);

步骤204,将该M个输出信号yi(n)等效为y(n):Step 204, the M output signals y i (n) are equivalent to y (n):

数字正交混频处理可以看作输入信号与本振信号相乘处理,则正交混频后的输出信号y(n)可以表示为:The digital quadrature mixing process can be regarded as the multiplication process of the input signal and the local oscillator signal, then the output signal y(n) after quadrature mixing can be expressed as:

ythe y (( nno )) == xx (( nno )) ×× LoLo (( nno )) == ΣΣ ii == 00 Mm -- 11 xx ii (( nno )) ×× ΣΣ qq == 00 Mm -- 11 LoLo qq (( nno )) == ΣΣ ii == 00 Mm -- 11 xx ii (( nno )) ×× LoLo ii (( nno )) == ΣΣ ii == 00 Mm -- 11 ythe y ii (( nno )) -- -- -- (( 77 ))

其中,in,

由公式(7)可见,正交混频后的输出信号可以看作M组子序列yi(n)的叠加,而公式(8)表示yi(n)是由子序列xi(n)和Loi(n)正交混频得到。而xi(n)和Loi(n)的数据速率与x(n)和Lo(n)相比,降低了M倍。因此,公式(8)表明高速采样信号的正交混频可以通过多相分解在低数据速率上实现。It can be seen from formula (7) that the output signal after quadrature mixing can be regarded as the superposition of M groups of subsequences y i (n), and formula (8) indicates that y i (n) is composed of subsequences xi (n) and Lo i (n) is obtained by quadrature mixing. Compared with x(n) and Lo(n), the data rates of x i (n) and Lo i (n) are reduced by M times. Therefore, Equation (8) shows that quadrature mixing of high-speed sampled signals can be realized at low data rates by polyphase decomposition.

ythe y (( nno )) == xx (( nno )) ×× LoLo (( nno )) == ΣΣ ii == 00 Mm -- 11 xx ii (( nno )) ×× ΣΣ qq == 00 Mm -- 11 LoLo qq (( nno )) == ΣΣ ii == 00 Mm -- 11 xx ii (( nno )) ×× LoLo ii (( nno )) == ΣΣ ii == 00 Mm -- 11 ythe y ii (( nno )) ..

实施例二Embodiment two

图3是本实施例一种千兆赫高速采样信号的多相数字下变频电路的结构图,其中,DDS为直接数字式频率合成器,如图3所示,以1.6GHz高速采样信号为例,包括:Fig. 3 is a structural diagram of a polyphase digital down-conversion circuit of a gigahertz high-speed sampling signal in this embodiment, wherein, DDS is a direct digital frequency synthesizer, as shown in Fig. 3 , taking a 1.6GHz high-speed sampling signal as an example, include:

M组数字下变频电路,用于分别对M组中频输入信号xi(n)与M组混频本振信号Loq(n)一一对应进行正交混频;M为正整数,i∈(0,M-1),q∈(0,M-1);M sets of digital down-conversion circuits are used to perform quadrature mixing on M sets of intermediate frequency input signals x i (n) and M sets of mixed frequency local oscillator signals Lo q (n) in one-to-one correspondence; M is a positive integer, i∈ (0, M-1), q ∈ (0, M-1);

M组多相滤波器,用于分别对M组正交混频后的信号进行抽取和滤波;M groups of polyphase filters are used to extract and filter the M groups of quadrature-mixed signals respectively;

其中,每相邻两组中频输入信号xi(n)之间,以及每相邻两组混频本振信号Loq(n)之间,间隔相同的时钟周期。Wherein, the interval between each adjacent two groups of intermediate frequency input signals x i (n) and between each adjacent two groups of mixing local oscillator signals Lo q (n) is the same clock period.

优选的,还包括多相滤波器配置模块,用于根据用户指令调整所述M组多相滤波器的宽度。Preferably, it also includes a polyphase filter configuration module, configured to adjust the width of the M sets of polyphase filters according to user instructions.

其中,在抽取和滤波阶段,本发明采用多组多相滤波器并行处理技术,在200MHz时钟上实现1.6GHz采样信号的2倍抽取。如图4所示,为宽带高速采样信号并行多组多相滤波实现框图。Among them, in the stage of extraction and filtering, the present invention adopts the parallel processing technology of multiple groups of polyphase filters to realize the double extraction of the 1.6GHz sampling signal on the 200MHz clock. As shown in Figure 4, it is a block diagram for implementing parallel multi-group polyphase filtering for broadband high-speed sampling signals.

在本发明中,数字正交混频之后的1.6GHz采样信号分成8路,直接作为第一个多相滤波器的输入,对高速采样信号进行8倍抽取,输出200MHz采样率的信号;第二个多相滤波器的输入是第一个多相滤波器输入信号延迟2个时钟周期后的信号,输出也是200MHz采样的信号;以此类推,第4个多相滤波器的输入是第一个多相滤波器输入信号延迟6个时钟周期后的信号。输出的4路信号等效为2倍抽取后的800MHz采样信号。为使多相滤波带宽根据需要调整,增加多相滤波器带宽设置的灵活性,本项目增加多相滤波器配置功能,使用户在控制界面上可以根据实际情况调整滤波器宽度。In the present invention, the 1.6GHz sampling signal after the digital quadrature mixing is divided into 8 paths, directly used as the input of the first polyphase filter, the high-speed sampling signal is extracted by 8 times, and the signal of the output 200MHz sampling rate is output; The input of the first polyphase filter is the signal after the input signal of the first polyphase filter is delayed by 2 clock cycles, and the output is also a signal sampled at 200MHz; and so on, the input of the fourth polyphase filter is the first The polyphase filter input signal is delayed by 6 clock cycles. The output 4 signals are equivalent to 800MHz sampling signals after decimation by 2 times. In order to adjust the polyphase filter bandwidth according to needs and increase the flexibility of polyphase filter bandwidth setting, this project adds a polyphase filter configuration function, so that users can adjust the filter width according to the actual situation on the control interface.

本发明能够达到以下有益效果:The present invention can achieve following beneficial effect:

本发明利用多相分解思想,将GHz及其以上高速采样信号多相分解为多个低采样率的子信号序列,并对每个子序列分别进行正交混频和多相滤波处理,最后在低工作频率上通过数值计算实现了高速采样信号的正交数字下变频处理,显著降低了高速采样信号正交数字下变频处理的复杂度;另外,本发明通过结构扩展和参数灵活设置,可以实现任意带宽、任意中频信号的数字下变频处理。The present invention uses the idea of polyphase decomposition to polyphase decompose GHz and above high-speed sampling signals into a plurality of sub-signal sequences with low sampling rates, and perform quadrature mixing and polyphase filtering on each sub-sequence respectively, and finally On the working frequency, the orthogonal digital down-conversion processing of the high-speed sampling signal is realized through numerical calculation, which significantly reduces the complexity of the high-speed sampling signal orthogonal digital down-conversion processing; in addition, the present invention can realize arbitrary Wide bandwidth, digital down-conversion processing of any intermediate frequency signal.

本领域技术人员还可以了解到本发明实施例列出的各种说明性逻辑块(illustrativelogicalblock),单元,和步骤可以通过电子硬件、电脑软件,或两者的结合进行实现。为清楚展示硬件和软件的可替换性(interchangeability),上述的各种说明性部件(illustrativecomponents),单元和步骤已经通用地描述了它们的功能。这样的功能是通过硬件还是软件来实现取决于特定的应用和整个系统的设计要求。本领域技术人员可以对于每种特定的应用,可以使用各种方法实现所述的功能,但这种实现不应被理解为超出本发明实施例保护的范围。Those skilled in the art can also understand that various illustrative logical blocks (illustrativelogical blocks), units, and steps listed in the embodiments of the present invention can be implemented by electronic hardware, computer software, or a combination of the two. To clearly demonstrate the interchangeability of hardware and software, the various illustrative components, units and steps above have generally described their functions. Whether such functions are implemented by hardware or software depends on the specific application and overall system design requirements. Those skilled in the art may use various methods to implement the described functions for each specific application, but such implementation should not be understood as exceeding the protection scope of the embodiments of the present invention.

以上所述的具体实施方式,对本发明的目的、技术方案和有益效果进行了进一步详细说明,所应理解的是,以上所述仅为本发明的具体实施方式而已,并不用于限定本发明的保护范围,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the scope of the present invention. Protection scope, within the spirit and principles of the present invention, any modification, equivalent replacement, improvement, etc., shall be included in the protection scope of the present invention.

Claims (6)

1.一种千兆赫高速采样信号的多相数字下变频方法,其特征在于,包括:1. a polyphase digital down-conversion method of a gigahertz high-speed sampling signal, characterized in that, comprising: 将数字混频器的中频输入信号x(n)等延迟分解为M项:Decompose the delay of the IF input signal x(n) of the digital mixer into M terms: x ( n ) = Σ i = 0 M - 1 x i ( n ) ; M为正整数; x ( no ) = Σ i = 0 m - 1 x i ( no ) ; M is a positive integer; 将所述混频本振信号Lo(n)等延迟分解为M项:The delays such as the mixed frequency local oscillator signal Lo(n) are decomposed into M items: LoLo (( nno )) == ΣΣ qq == 00 Mm -- 11 LoLo qq (( nno )) ;; 将xi(n)和Loq(n)一一对应进行正交混频,得到M个输出信号yi(n);Carry out quadrature mixing with x i (n) and Lo q (n) in one-to-one correspondence to obtain M output signals y i (n); 将该M个输出信号yi(n)等效为y(n):The M output signals y i (n) are equivalent to y(n): ythe y (( nno )) == xx (( nno )) ×× LoLo (( nno )) == ΣΣ ii == 00 Mm -- 11 xx ii (( nno )) ×× ΣΣ qq == 00 Mm -- 11 LoLo qq (( nno )) == ΣΣ ii == 00 Mm -- 11 xx ii (( nno )) ×× LoLo ii (( nno )) == ΣΣ ii == 00 Mm -- 11 ythe y ii (( nno )) .. 2.根据权利要求1所述的方法,其特征在于,所述将数字混频器的中频输入信号x(n)进行多项分解,等延迟分解为M项具体包括:2. method according to claim 1, it is characterized in that, described the intermediate frequency input signal x (n) of digital mixer is carried out polynomial decomposition, etc. delay is decomposed into M item and specifically comprises: 获取所述中频输入信号x(n)和混频本振信号Lo(n)的采样周期Ts,以及采样频率fsObtain the sampling period T s and sampling frequency f s of the intermediate frequency input signal x(n) and the mixed frequency local oscillator signal Lo(n); 将所述中频输入信号x(n)根据以下计算过程分解:The intermediate frequency input signal x(n) is decomposed according to the following calculation process: 其中,xc(kTs)为连续时间信号xc(t)的采样;δ(·)为狄拉克函数; Among them, x c (kT s ) is the sampling of continuous time signal x c (t); δ(·) is the Dirac function; 令k=mM+i则:Let k=mM+i then: xx (( nno )) == ΣΣ kk == -- ∞∞ ∞∞ xx cc (( kTkT sthe s )) δδ [[ (( nno -- kk )) TT sthe s ]] == ΣΣ ii == 00 Mm -- 11 ΣΣ mm == -- ∞∞ ∞∞ xx cc [[ mMmM TT sthe s ++ ii TT sthe s ]] δδ [[ (( nno -- mMmM -- ii )) TT sthe s ]] == ΣΣ ii == 00 Mm -- 11 xx ii (( nno )) ;; 其中,in, xx ii (( nno )) == ΣΣ mm == -- ∞∞ ∞∞ xx cc [[ mMmM TT sthe s ++ ii TT sthe s ]] δδ [[ (( nno -- mMmM -- ii )) TT sthe s ]] == ΣΣ mm == -- ∞∞ ∞∞ xx cc [[ mm (( MTMT sthe s )) ++ ii TT sthe s ]] δδ [[ (( nno -- mMmM )) TT sthe s -- ii TT sthe s ]] .. 3.根据权利要求2所述的方法,其特征在于,所述将所述混频本振信号Lo(n)进行多项分解,等延迟分解为M项具体包括:3. method according to claim 2, is characterized in that, described described mixed frequency local oscillator signal Lo (n) is carried out polynomial decomposition, waits for delay and is decomposed into M item and specifically comprises: 获取所述混频本振信号Lo(n)的频率f0,以及初始相位 Obtain the frequency f 0 of the mixed frequency local oscillator signal Lo(n), and the initial phase 将所述混频本振信号Lo(n)根据以下计算过程分解:The mixed frequency local oscillator signal Lo(n) is decomposed according to the following calculation process: LoLo (( nno )) == ΣΣ ll == -- ∞∞ ∞∞ LoLo cc (( lTlT sthe s )) δδ [[ (( nno -- ll )) TT sthe s ]] == ΣΣ qq == 00 Mm -- 11 ΣΣ pp == -- ∞∞ ∞∞ LoLo cc [[ pMpM TT sthe s ++ qq TT sthe s ]] δδ [[ (( nno -- pMpM -- qq )) TT sthe s ]] == ΣΣ qq == 00 Mm -- 11 LoLo qq (( nno )) ;; 其中,in, LoLo qq (( nno )) == ΣΣ pp == -- ∞∞ ∞∞ LoLo cc [[ pMpM TT sthe s ++ qq TT sthe s ]] δδ [[ (( nno -- pMpM -- qq )) TT sthe s ]] == ΣΣ pp == -- ∞∞ ∞∞ LoLo cc [[ pp (( MTMT sthe s )) ++ qq TT sthe s ]] δδ [[ (( nno -- pMpM )) TT sthe s -- qq TT sthe s ]] ;; 4.根据权利要求3所述的方法,其特征在于:4. The method according to claim 3, characterized in that: 将xi(n)和Loq(n)正交混频得到输出信号:The output signal is obtained by quadrature mixing xi (n) and Lo q (n): 5.一种千兆赫高速采样信号的多相数字下变频电路,其特征在于,包括:5. A polyphase digital down-conversion circuit of a gigahertz high-speed sampling signal, characterized in that it comprises: M组数字下变频电路,用于分别对M组中频输入信号xi(n)与M组混频本振信号Loq(n)一一对应进行正交混频;M为正整数,i∈(0,M-1),q∈(0,M-1);M sets of digital down-conversion circuits are used to perform quadrature mixing on M sets of intermediate frequency input signals x i (n) and M sets of mixed frequency local oscillator signals Lo q (n) in one-to-one correspondence; M is a positive integer, i∈ (0, M-1), q ∈ (0, M-1); M组多相滤波器,用于分别对M组正交混频后的信号进行抽取和滤波;M sets of polyphase filters are used to extract and filter the M sets of quadrature mixed signals respectively; 其中,每相邻两组中频输入信号xi(n)之间,以及每相邻两组混频本振信号Loq(n)之间,间隔相同的时钟周期。Wherein, the interval between each adjacent two groups of intermediate frequency input signals x i (n) and between each adjacent two groups of mixing local oscillator signals Lo q (n) is the same clock period. 6.根据权利要求5所述的电路,其特征在于,还包括多相滤波器配置模块,用于根据用户指令调整所述M组多相滤波器的宽度。6. The circuit according to claim 5, further comprising a polyphase filter configuration module, configured to adjust the width of the M groups of polyphase filters according to user instructions.
CN201510324924.1A 2015-06-12 2015-06-12 Multi-phase digital down conversion method for GHz high-speed sampling signal Pending CN105048966A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510324924.1A CN105048966A (en) 2015-06-12 2015-06-12 Multi-phase digital down conversion method for GHz high-speed sampling signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510324924.1A CN105048966A (en) 2015-06-12 2015-06-12 Multi-phase digital down conversion method for GHz high-speed sampling signal

Publications (1)

Publication Number Publication Date
CN105048966A true CN105048966A (en) 2015-11-11

Family

ID=54455224

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510324924.1A Pending CN105048966A (en) 2015-06-12 2015-06-12 Multi-phase digital down conversion method for GHz high-speed sampling signal

Country Status (1)

Country Link
CN (1) CN105048966A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106291501A (en) * 2016-08-26 2017-01-04 上海无线电设备研究所 High-speed Parallel Signal Processing Systems and processing method thereof
CN111431484A (en) * 2020-04-01 2020-07-17 济南浪潮高新科技投资发展有限公司 Image frequency suppression mixer
CN113271066A (en) * 2021-05-18 2021-08-17 西南科技大学 Data stream digital down-conversion method based on packet parallel

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1049588A (en) * 1989-06-26 1991-02-27 莫托罗拉公司 Predetection bandwidth is according to desired data rate and variable receiver
CN1706109A (en) * 2002-06-07 2005-12-07 美商内数位科技公司 System and method for a direct conversion multi-carrier processor
CN101567701A (en) * 2009-05-11 2009-10-28 深圳市统先科技股份有限公司 High efficient multi-path digital down converter system
CN101707473A (en) * 2009-09-25 2010-05-12 中国科学院上海天文台 GHz ultra wide band digital down converter method
US20120008717A1 (en) * 2010-07-12 2012-01-12 Nxp B.V. Conversion system
CN103873082A (en) * 2009-02-04 2014-06-18 高通股份有限公司 Adjustable receive filter responsive to frequency spectrum information

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1049588A (en) * 1989-06-26 1991-02-27 莫托罗拉公司 Predetection bandwidth is according to desired data rate and variable receiver
CN1706109A (en) * 2002-06-07 2005-12-07 美商内数位科技公司 System and method for a direct conversion multi-carrier processor
CN103873082A (en) * 2009-02-04 2014-06-18 高通股份有限公司 Adjustable receive filter responsive to frequency spectrum information
CN101567701A (en) * 2009-05-11 2009-10-28 深圳市统先科技股份有限公司 High efficient multi-path digital down converter system
CN101707473A (en) * 2009-09-25 2010-05-12 中国科学院上海天文台 GHz ultra wide band digital down converter method
US20120008717A1 (en) * 2010-07-12 2012-01-12 Nxp B.V. Conversion system

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
廉昕等: ""基于并行NCO的宽带数字下变频器"", 《电子测量技术》 *
郭连平等: ""并行数字下变频中的NCO实现研究"", 《仪器仪表学报》 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106291501A (en) * 2016-08-26 2017-01-04 上海无线电设备研究所 High-speed Parallel Signal Processing Systems and processing method thereof
CN106291501B (en) * 2016-08-26 2019-01-08 上海无线电设备研究所 High-speed Parallel Signal Processing Systems and its processing method
CN111431484A (en) * 2020-04-01 2020-07-17 济南浪潮高新科技投资发展有限公司 Image frequency suppression mixer
CN113271066A (en) * 2021-05-18 2021-08-17 西南科技大学 Data stream digital down-conversion method based on packet parallel

Similar Documents

Publication Publication Date Title
CN102346245B (en) Digital down-conversion method of broadband IF (intermediate frequency) signals
Datta et al. FPGA implementation of high performance digital down converter for software defined radio
CA2977894C (en) High speed low power digital to analog upconverter
CN105048966A (en) Multi-phase digital down conversion method for GHz high-speed sampling signal
Dinis et al. Improving the performance of all-digital transmitter based on parallel delta-sigma modulators through propagation of state registers
CN106100588A (en) A kind of restructural multi-channel digital down conversion system based on FPGA and method
CN111786690B (en) Digital down-conversion method of parallel structure
ITRM20070025A1 (en) MULTI-CHANNEL DIGITAL SYSTEM FOR THE DEVELOPMENT OF RADIO SIGNALS, IN PARTICULAR TO EXTREMELY WIDE BAND.
CN114966564B (en) A Multi-channel Parallel De-skewing Method for Wideband Linear Frequency Modulation Signals
CN103546099A (en) Harmonic suppression frequency mixer
Podsiadlik et al. Time-Interleaved $\Sigma\Delta $ Modulators for FPGAs
Zhang et al. Generalized FRM-based PL band multi-channel channelizers for array signal processing system
Santhosh et al. Design and VLSI Implementation of interpolators/decimators for DUC/DDC
Saravanan et al. Design and implementation of efficient CIC filter structure for decimation
Beygi et al. An FPGA-based irrational decimator for digital receivers
Amulya et al. Design and implementation of a reconfigurable digital down converter for 4G systems using MATLAB and FPGA-a review
Thiel et al. Digital Fractional and Asynchronous Oversampling for High Speed Delta-Sigma Modulators
Maruthi et al. implementation of High performance DUC and DDC for Software Defined Radio Applications
CN103066949A (en) Multi-channel comb filter
CN113271066A (en) Data stream digital down-conversion method based on packet parallel
CN101207598B (en) Frequency synthesizer and frequency synthesis method
Gupta et al. Analysis & implementation of high cascaded integrated comb for software defined radios application
Madheswaran et al. Implementation and comparison of different CIC filter structure for decimation
Sheikh et al. Review of polyphase filtering technique in signal processing
CN205883168U (en) Restructural multichannel digital down conversion system based on FPGA

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20151111

RJ01 Rejection of invention patent application after publication