CN105047614A - Manufacturing method of semiconductor memory - Google Patents
Manufacturing method of semiconductor memory Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
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Abstract
The invention provides a manufacturing method of a semiconductor memory. A patterned integrated mask integrating a conventional floating gate mask and a control grid protective mask is actually utilized, and etching processes and filling processes of a storage unit technical window in a storage area and a connecting hole technical window in a connecting area are merged, such that at the time when a storage window is formed at the position of a storage unit simply through one lithography and etching process at a time, a connecting window is also formed at a wiring position, the storage window is far wider than the connecting window, afterwards, a first dielectric layer is formed through a deposition process, high-temperature backflow is carried out, and the connecting window is directly filled up. According to the invention, the technical steps of masking, etching, filling and grinding at the connecting area by use of an individual mask in a conventional process are omitted, the process time is saved, and the process cost is decreased.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of manufacture method of semiconductor memory.
Background technology
At present, flash memory (FlashMemory), also known as flash memory, has become the main flow memory of non-volatility memorizer.Different according to structure, flash memory can be divided into or non-flash (NORFlash) and with non-flash (NANDFlash).The main feature of flash memory is the information that can keep for a long time when not powering up storing; And have that integrated level is high, access speed is fast, be easy to the advantages such as erasing and rewriting, be thus widely used in the multinomial field such as microcomputer, Automated condtrol.Flash memories (FlashMemory, be called for short flash memory) be the internal memory of a kind of erasing able to programme, non-volatile (non-volatile), namely when without external power source, also the information content can be preserved, this makes device itself not need wastes power in the storage of data, add that flash memory also possesses repetitive read-write, volume is little, capacity is high and portable characteristic, this makes flash memory be particularly suitable for being used on portable device, has become one of main flow of industry research.
Existing flash memory comprises the peripheral control circuits (PeripheralCircuit) being positioned at suprabasil core cell (CellCircuit) region and being positioned at around core memory circuit, memory cell region is for storing information, and the information that peripheral control circuits region is used for memory cell region stores reads.Wherein, typical memory cell mainly by be used for stored charge floating boom (FloatingGate) be used for the control gate (ControlGate) that control data stores and form, control gate to be arranged on floating boom and to be separated by with barrier oxide layer therebetween, is separated by between floating boom and Semiconductor substrate with tunnel oxide (TunnelOxide) simultaneously.At present, a kind of manufacture method of flash memory comprises:
Please refer to Figure 1A, the Semiconductor substrate 100 that one has memory block I (cellarea) and control gate bonding pad II (FLG2area) is provided, be formed with control grid layer (ControlGate successively on a semiconductor substrate 100, CG) 101, silicon nitride cover layer 102 and photoresist layer (not shown), adopt floating boom light shield (FGmask, floating boom mask plate) 103 photoetching, etching photoresist layer and silicon nitride cover layer 102 (i.e. FGPH/SiNetch technique), to form corresponding memory cell process window 104 in each memory cell position of memory block I, remove photoresist layer.
Please refer to Figure 1B, use tetraethoxysilane (TEOS) low pressure (LP) depositing operation in the device surface deposited oxide layer (i.e. SP1DEP technique) forming memory cell process window 104, Self-aligned etching oxide layer (i.e. SP1etch technique), forms side wall 105.
Please refer to Fig. 1 C, with described side wall 105 for mask, continue the control grid layer 101 (i.e. CGPH/etch technique) of etching memory cell process window 104, to form control gate and source electrode line (SL, the SourceLine) process window of memory block I.
Then, please continue to refer to Fig. 1 C, etch (SP2DEP/etch) in whole device surface metallization medium layer, at source electrode line (SL, SourceLine) separator 107 of formation control grid and source electrode line in process window, then to source electrode line (SL, SourceLine) source electrode line (SL is filled in process window, SourceLine) conductive layer, and chemical-mechanical planarization is to silicon nitride surface (i.e. SLDEP/CMP), whole process is SP2etch/SLCMP.
Please refer to Fig. 1 D; adopt the control gate of control gate protection light shield (FLG2mask) 109 protection memory block I; the SiN of etching control gate bonding pad II; form connecting hole 106; then in connection groove 110, HDP oxide layer (i.e. HDPoxideDEP/CMP) is filled, to protect to the control gate (CG) below connecting hole 106.Follow-up can continuation removes SiN, and the control grid layer 101 exposed after continuing the removal SiN to control gate bonding pad II etches (i.e. SiNremove & CG2etch), control grid layer 101 in etching process below connecting hole 106 is not etched, and remain, be used as the connecting line be connected with the control gate of memory block I.Afterwards, the making that other processing steps complete memory block is conventionally carried out.
In summary, in prior art, the fabrication processing of flash memory is: FGPH/SiNetch → SP1dep → SP1etch → CGph/etch → SP2etch/SLCMP → FLG2ph/SiNetch/HDPox/CMP → SiNremove & CG2etch, the formation of the process window of memory block and bonding pad needs two different light shields and twice etching technique, and the filling of two process windows needs corresponding different fill process and chemical mechanical milling tech, therefore, need to simplify existing processing step, to reduce costs.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of semiconductor memory, the light shield used in manufacture process can be reduced, Simplified flowsheet step, reduce process costs.
For solving the problem, the present invention proposes a kind of manufacture method of semiconductor memory, comprising:
The Semiconductor substrate that one has memory block and a bonding pad is provided, is formed with control grid layer and cover layer on the semiconductor substrate;
With one can the integration light shield of the memory cell position of definition memory and the connecting hole position of bonding pad for mask, photoetching also etches described cover layer, memory window is formed in the memory cell position of memory block, be formed with connection window at the tie line position of bonding pad, and memory window is wider than connecting window;
Deposit the first interlayer dielectric layer at formation memory window with the device surface being connected window, and high temperature reflux is carried out to the first interlayer dielectric layer, to be filled up by connection window;
With the first interlayer dielectric layer and cover layer protection bonding pad, and form side wall by Self-aligned etching technique at described memory window sidewall.Further, the temperature of described high temperature reflow processes is more than 800 DEG C.
Further, described first interlayer dielectric layer is for mixing phosphor silicon oxide or phosphorosilicate glass.
Further,
The step being formed side wall by Self-aligned etching technique in described memory window is comprised:
Remove the first interlayer dielectric layer above cover layer;
The first interlayer dielectric layer in Self-aligned etching memory window, removes the first interlayer dielectric layer bottom memory window, and the first interlayer dielectric layer retained by memory window sidewall is as described side wall.
Further, the step forming side wall by Self-aligned etching technique in described memory window comprises:
Remove the first interlayer dielectric layer in memory window and the first interlayer dielectric layer above cover layer;
Redeposited one deck second interlayer dielectric layer in described memory window, Self-aligned etching second interlayer dielectric layer, remove the second interlayer dielectric layer bottom memory window, the second interlayer dielectric layer retained by memory window sidewall is as described side wall, and the Step Coverage ability of described second interlayer dielectric layer is higher than the first interlayer dielectric layer.
Further, wet corrosion technique is adopted to etch the first interlayer dielectric layer in memory window, to remove in memory window the first interlayer dielectric layer needing to remove.
Further, described second interlayer dielectric layer utilizes low-pressure chemical vapor deposition process to make.
Further, after the described side wall of formation, also comprise:
With described side wall for mask, continue to adopt Self-aligned etching technique etching control grid layer, to form subwindow described depositing in control grid layer;
Packing material is adopted to fill described subwindow.
Further, the step adopting packing material to fill described subwindow comprises:
Etch at the whole device surface deposition medium separator forming described subwindow, with to described subwindow filled media separator, and retain source electrode line window in described subwindow;
In source electrode line window, fill source electrode line conductive layer, and source electrode line conductive layer described in chemical-mechanical planarization is to cover surface.
Further, the depth over width ratio scope of described memory window is 1.1 ~ 1.6, and the depth over width ratio of described connection window is not less than 2.
Compared with prior art, the manufacture method of semiconductor memory provided by the invention, the energy memory cell position of definition memory adopted and the integration light shield of the connecting hole position of bonding pad, in fact that the pattern of traditional floating boom light shield and control gate protection light shield is combined, thus by the etching technics of the memory cell process window of memory block and the connecting hole process window of bonding pad, fill process merges, thus can while memory cell position forms memory window by a photoetching and etching technics, formed at tie line position and connect window, and memory window is much wider than connecting window, depositing operation forms the first interlayer dielectric layer and high temperature reflux afterwards, directly connection window is filled up, thus the control grid layer that protection connects beneath window is not etched away by the etching process of subsequent memory area, thus present invention achieves and utilize a light shield to carry out etching technics, formed and be positioned at the memory block window different with two width dimensions of bonding pad, and incorporate follow-up fill process step, eliminating bonding pad in traditional handicraft uses independent light shield to carry out the processing step of mask, etching, filling and grinding, by reducing by a light shield, save the process time, reduce process costs.
Accompanying drawing explanation
Figure 1A to 1D is the device profile structural representation in the manufacturing process of a kind of control gate of the prior art;
Fig. 2 is the manufacture method flow chart of the control gate of the embodiment of the present invention one;
Fig. 3 A to 3D is the device profile structural representation in the manufacturing process shown in Fig. 2;
Fig. 4 is the manufacture method flow chart of the control gate of the embodiment of the present invention two;
Fig. 5 A to 5D is the device profile structural representation in the manufacturing process shown in Fig. 4.
Embodiment
The manufacture method of semiconductor memory provided by the invention, a mask plate is utilized to carry out etching technics, form the process window that two width dimensions are different: be positioned at the memory cell window of memory block and be positioned at the connection window of bonding pad, and incorporate follow-up filling grinding technics step, reduce process costs.
For making object of the present invention, feature becomes apparent, and be further described, but the present invention can realize by different forms, should just not be confined to described embodiment below in conjunction with accompanying drawing to the specific embodiment of the present invention.
Embodiment one
Please refer to Fig. 2, the present embodiment provides a kind of manufacture method of semiconductor memory, comprising:
S21, provides the Semiconductor substrate that has memory block and a bonding pad, is formed with control grid layer and cover layer on the semiconductor substrate;
S22, with one can the integration light shield of the memory cell position of definition memory and the connecting hole position of bonding pad for mask, photoetching also etches described cover layer, memory window is formed in the memory cell position of memory block, be formed with connection window at the tie line position of bonding pad, and memory window is wider than connecting window;
S23, deposits the first interlayer dielectric layer at formation memory window with the device surface being connected window, and carries out high temperature reflux to the first interlayer dielectric layer, to be filled up by connection window;
S24, with the first interlayer dielectric layer and cover layer protection bonding pad, the first interlayer dielectric layer of memory window sidewall described in Self-aligned etching, forms side wall.
Please refer to Fig. 3 A, step S21 provides the process of Semiconductor substrate 300 to comprise:
First, provide a substrate, by fleet plough groove isolation structure technique, substrate is divided into memory block I and bonding pad (FLG2) II;
Then, substrate deposits floating boom (FG) layer and grid barrier oxide layer successively, and usually, floating gate layer is made up of the floating gate polysilicon layer of the floating gate oxide layers and top thereof that are positioned at substrate surface, floating gate layer is used for floating boom, and grid barrier oxide layer is for isolating floating boom and follow-up control gate.Wherein floating gate oxide layers can be silica, silicon oxynitride or LPTEOS (oxide layer that lower temperature deposition tetraethoxysilance is formed), and grid barrier oxide layer can be silicon nitride layer or ONO separator (being namely formed at silicon oxide layer, silicon nitride layer and the silicon oxide layer on described floating gate polysilicon layer successively).
Wherein, the depositing operation of fleet plough groove isolation structure technique and floating gate layer and grid barrier oxide layer is same as the prior art, do not repeat at this, simultaneously in order to give prominence to emphasis of the present invention better, device profile structural representation embodies inventive concept of the present invention more clearly, and the structures such as fleet plough groove isolation structure, floating boom (FG) layer and grid barrier oxide layer are all not shown.
Please continue to refer to Fig. 3 A, in the step s 21, continue be formed with the Semiconductor substrate 300 of described grid barrier oxide layer on the surface, formation control gate layer 301 and cover layer 302 successively.The material of described control grid layer 301 is polysilicon, cover memory block I and bonding pad II, control grid layer 301 part covered on the I of memory block will form the control gate of memory cell structure by follow-up etching technics, memory window will be formed in cover layer 302 above this part control grid layer 301, control grid layer 301 part covered on the II of bonding pad will form the connecting line be electrically connected with the control gate of memory cell by follow-up etching, connection window will be formed in cover layer 302 above this part control grid layer 301, concrete manufacture craft will be described in subsequent step.As an embodiment, cover layer 302 is silicon nitride, and thickness range is 3700 dust ~ 4700 dusts.In a preferred embodiment, the thickness range of described silicon nitride layer is 4000 dust-4400 dusts.
Then, continue with reference to figure 3A, in step S22, cover layer 302 applies photoresist layer (not shown) as mask, utilize the integration light shield 303 of the memory cell position of an energy definition memory and the connecting hole position of bonding pad, photoetching and etching technics are carried out to cover layer 302, in described cover layer 302 formed expose below control grid layer 301 memory window 304 be connected window 305.Wherein, described memory window 304 is positioned at memory block I, define the process window making each memory cell, for the formation of memory cell structure, namely the control grid layer 301 exposed below described memory window 304 will form the control gate of memory device subsequently through etching technics, memory window 304 region is made to form memory cell, the position that connection window 305 corresponds to the connecting line be electrically connected with memory cell control gate is arranged, define the manufacture craft window of connecting line, the control grid layer 301 connected below window 305 position goes will be retained in step at follow-up etching technics, and above this connection window 305, form corresponding contact hole by follow-up, the control grid layer 301 connected below window 305 can by the memory device of memory block I formation and external electrical connections.Memory window 304 is wider than connecting window 305.In the present embodiment, memory window 304 can be identical than the degree of depth connecting window 305, and the degree of depth of memory window 304 and ratio (depth-to-width ratio) value of width can be 1.1 ~ 1.6, and the depth-to-width ratio connecting window 305 is not less than 2.It should be noted that; integrating light shield 303 is in fact combined by the pattern of traditional floating boom light shield and control gate protection light shield; make in a same photoetching and etching technics; just can be formed simultaneously and connect window 305 and memory window 304; be equivalent to the serial process traditional first making memory window, rear making connects window to be reduced to the parallel process simultaneously making two windows, save process time and cost.The step S22 of the present embodiment and FGPH/SiNetch process of the prior art.
Please refer to Fig. 3 B, in step S23, first, choosing can the interlevel dielectric material of high temperature reflux, such as comprise at least one in phosphorosilicate glass (PSG), Pyrex (BSG), boron-phosphorosilicate glass (BPSG), forming memory window 304 and the device surface deposition being connected window 305, form the first interlayer dielectric layer 306, first interlayer dielectric layer 306 can by side wall follow-up in memory window 304 etching, as the side wall of memory window 304, be preferably phosphorosilicate glass (PSG); Then, more than 800 DEG C high temperature refluxes (reflow) are carried out to the first interlayer dielectric layer 306 of deposition, until the first interlayer dielectric layer 306 deliquescing also can be flowed, utilize the depth-to-width ratio of the first interlayer dielectric layer 306 reflow and memory window and connection window, connection window 305 is filled up by the first interlayer dielectric layer 306 of deposition, and obtains smooth, fine and close deposition surface.Because memory window 304 can require to make according to device specification with the width dimensions being connected window 305, usual memory window 304 is than connecting window 305 wide a lot (such as memory window 304 wide connects wide more than 1.5 times of window), when connecting window 305 and being filled, memory window 304 is filled not yet, but the first interlayer dielectric layer 306 can cover sidewall and the bottom of memory window 304, and ground floor dielectric layer 306 will be etched to side wall and partly retained in follow-up Self-aligned etching processing step in memory window 304, and the first interlayer dielectric layer 306 connected in window 305 will together with cover layer 302, as protective layer, control grid layer 301 below protection bonding pad.As an embodiment, the temperature of high temperature reflux is 800 DEG C ~ 1000 DEG C or 900 DEG C ~ 980 DEG C.The step S23 of the present embodiment is actually SP1 (PSG) dep+SP1reflow process.
Please refer to Fig. 3 C, in step s 24 which, first, chemical-mechanical planarization is carried out to the surface of the first interlayer dielectric layer 306, remove unnecessary first interlayer dielectric layer 306 above cover layer 302; Then, wet corrosion technique or first interlayer dielectric layer 306 of dry etch process to memory block I can be adopted to carry out Self-aligned etching (SP1etch), to form side wall (can be regarded as inside wall) in memory window 304, expose the control grid layer 301 bottom memory window 304, described wet corrosion technique can utilize hydrofluoric acid solution to carry out simultaneously.The step S24 of the present embodiment is actually SP1etch process, first interlayer dielectric layer of the SP1etch process etching of the present embodiment (can high temperature reflux, such as PSG) material that etch with traditional SP1etch process (can not high temperature reflux, be generally LPTEOS) difference.
Please refer to Fig. 3 D, after step S24, can also carry out the subsequent process steps that semiconductor storage unit same as the prior art makes, main purpose is the peripheral control circuits part forming other parts of memory device, connecting line and control storage.The secondarily etched processing step of control gate (SiNremove & CG2etch technique) after subsequent process steps such as comprises source electrode line manufacturing process steps (CGph/etch+SP2etch/SLCMP) and removes cover layer.
Wherein, in source electrode line manufacturing process steps (CGph/etch+SP2etch/SLCMP), first, with the side wall formed for mask, continue the control grid layer 301 (CGph/etch) bottom etching memory window 304, the subwindow (not shown) exposing bottom control grid layer is formed in memory window 304, bottom memory window 304, remaining control grid layer 301 is for the control gate of follow-up formation memory cell, described subwindow may be used for the source electrode line (SL) of follow-up formation semiconductor memory, wherein, in CGph/etch process, the control grid layer 301 of bonding pad is under the protection of the first interlayer dielectric layer 306 and cover layer 302, completely not by the impact of memory block I subwindow etching process, shape does not change.Then, dielectric material and electric conducting material is adopted successively to fill described subwindow, particularly, first, at the whole device surface deposition medium separator 308 of described subwindow, then the unnecessary buffer layer 308 removed above cover layer 302 (can etch the buffer layer 308 removed bottom subwindow further, retain the buffer layer 308 of subwindow sidewall, make buffer layer 308 as the second side wall in memory window), to form one deck buffer layer 308 at subwindow inner surface, and retain source electrode line (SL) window; Then, sedimentary origin polar curve conductive layer 307 is continued at described subwindow, and carry out chemical-mechanical planarization polar curve conductive layer 307 to cover layer 302 surface, remove source electrode line conductive layer 307 unnecessary above cover layer 302, make source electrode line conductive layer 307 just fill and lead up memory window 304.
When performing SiNremove & CG2etch processing step, only can remove the cover layer of bonding pad II, then the control grid layer 301 that bonding pad II comes out is removed, and the control grid layer below bonding pad II first interlayer dielectric layer 306b is retained, as connecting line 301b; Also only can remove the cover layer of memory block I, then etching removes the control grid layer that memory block exposes, and the control grid layer bottom the interlayer dielectric layer 306a of memory block first and bottom subwindow is retained, for the formation of the control gate 301a of memory block.The Semiconductor substrate 300 below the I of memory block can be exposed after the control grid layer that etching removal memory block exposes, at least one in floating boom etching technics, floating boom side wall technique, source/drain region ion implantation technology is carried out to the Semiconductor substrate 300 exposed, and then the making of whole memory device can be completed.Concrete technology step is same as the prior art, does not repeat at this.
From the above mentioned, the manufacturing process of the semiconductor memory of the present embodiment is FGPH/SNetch → SP1 (PSG) dep → SP1reflow → SP1etch → CGph/etch → SP2etch/SLCMP → SINremove/CGetch.Compared with traditional fabrication processing FGPH/SiNetch → SP1dep → SP1etch → CGph/etch → SP2etch/SLCMP → FLG2ph/SiNetch/HDPox/CMP → SiNremove & CG2etch, the present embodiment adopts an integration light shield protecting the pattern of light shield to combine traditional floating boom light shield and control gate, carry out a photoetching and etching technics, memory window can be formed in memory cell position simultaneously, formed at tie line position and connect window, and memory window is much wider than connecting window, and utilize the high temperature reflux of the first interlayer dielectric layer of deposition, directly connection window is filled up, thus by the etching technics of the memory cell process window of memory block and the connecting hole process window of bonding pad, fill process merges, eliminating bonding pad in traditional handicraft uses independent light shield FLG2mask to carry out mask, etching, the processing step of filling and grinding, namely by minimizing light shield, Simplified flowsheet step, save the process time, reduce process costs.
Embodiment two
Please refer to Fig. 4, the present embodiment provides a kind of manufacture method of semiconductor memory, comprising:
S41, provides the Semiconductor substrate that has memory block and a bonding pad, is formed with control grid layer and cover layer on the semiconductor substrate;
S42, with one can the integration light shield of the memory cell position of definition memory and the connecting hole position of bonding pad for mask, photoetching also etches described cover layer, memory window is formed in the memory cell position of memory block, be formed with connection window at the tie line position of bonding pad, and memory window is wider than connecting window;
S43, deposits the first interlayer dielectric layer at formation memory window with the device surface being connected window, and carries out high temperature reflux to the first interlayer dielectric layer, to be filled up by connection window;
S44, removes the first interlayer dielectric layer in memory window and the first interlayer dielectric layer above cover layer;
S45, redeposited one deck second interlayer dielectric layer in described memory window, the second interlayer dielectric layer in Self-aligned etching memory window, forms side wall.。
Please refer to Fig. 5 A, step S41 provides the process of Semiconductor substrate 500 to comprise:
First, provide a substrate, by fleet plough groove isolation structure technique, substrate is divided into memory block I and bonding pad (FLG2) II;
Then, substrate deposits floating boom (FG) layer and grid barrier oxide layer successively, and usually, floating gate layer is made up of the floating gate polysilicon layer of the floating gate oxide layers and top thereof that are positioned at substrate surface, floating gate layer is used for floating boom, and grid barrier oxide layer is for isolating floating boom and follow-up control gate.Wherein floating gate oxide layers can be silica, silicon oxynitride or LPTEOS (oxide layer that lower temperature deposition tetraethoxysilance is formed), and grid barrier oxide layer can be silicon nitride layer or ONO separator (being namely formed at silicon oxide layer, silicon nitride layer and the silicon oxide layer on described floating gate polysilicon layer successively).
Wherein, the depositing operation of fleet plough groove isolation structure technique and floating gate layer and grid barrier oxide layer is same as the prior art, do not repeat at this, simultaneously in order to give prominence to emphasis of the present invention better, device profile structural representation embodies inventive concept of the present invention more clearly, and the structures such as fleet plough groove isolation structure, floating boom (FG) layer and grid barrier oxide layer are all not shown.
Please continue to refer to Fig. 5 A, in step S41, continue be formed with the Semiconductor substrate 500 of described grid barrier oxide layer on the surface, formation control gate layer 501 and cover layer 502 successively.The material of described control grid layer 501 is polysilicon, cover memory block I and bonding pad II, control grid layer 501 part covered on the I of memory block will form the control gate of memory cell structure by follow-up etching technics, memory window will be formed in cover layer 502 above this part control grid layer 501, control grid layer 501 part covered on the II of bonding pad will form the connecting line be electrically connected with the control gate of memory cell by follow-up etching, connection window will be formed in cover layer 502 above this part control grid layer 501, concrete manufacture craft will be described in subsequent step.As an embodiment, cover layer 502 is silicon nitride, and thickness range is 3700 dust ~ 4700 dusts.In a preferred embodiment, the thickness range of described silicon nitride layer is 4000 dust ~ 4400 dusts.
Then, continue with reference to figure 5A, in step S42, cover layer 502 applies photoresist layer (not shown) as mask, utilize the integration light shield 503 of the memory cell position of an energy definition memory and the connecting hole position of bonding pad, photoetching and etching technics are carried out to cover layer 502, in described cover layer 502 formed expose below control grid layer 501 memory window 504 be connected window 505.Wherein, described memory window 504 is positioned at memory block I, for the formation of memory cell structure, namely the control grid layer 501 exposed below described memory window 504 will form the control gate of memory device subsequently through etching technics, memory window 504 region is made to form memory cell, the position that connection window 505 corresponds to the connecting line be electrically connected with memory cell control gate is arranged, the control grid layer 501 connected below window 505 position goes will be retained in step at follow-up etching technics, and above this connection window 505, form corresponding contact hole by follow-up, the control grid layer 501 connected below window 505 can by the memory device of memory block I formation and external electrical connections.Memory window 504 is wider than connecting window 505.In the present embodiment, memory window 504 can be identical than the degree of depth connecting window 505, and the degree of depth of memory window 504 and ratio (depth-to-width ratio) value of width can be 1.1 ~ 1.6, and the depth-to-width ratio connecting window 505 is not less than 2.It should be noted that; integrating light shield 503 is in fact combined by the pattern of traditional floating boom light shield and control gate protection light shield; make in a same photoetching and etching technics; just can be formed simultaneously and connect window and memory window; be equivalent to the serial process traditional first making memory window, rear making connects window to be reduced to the parallel process simultaneously making two windows, save process time and cost.The step S42 of the present embodiment and FGPH/SiNetch process of the prior art.
Please refer to Fig. 5 B, in step S43, first, choosing can the interlevel dielectric material of high temperature reflux, the first interlayer dielectric layer 506 is deposited with the device surface being connected window 505 at formation memory window 504, the material of the first interlayer dielectric layer 506 comprises at least one in phosphorosilicate glass (PSG), Pyrex (BSG), boron-phosphorosilicate glass (BPSG), is preferably phosphorosilicate glass (PSG); Then, more than 800 DEG C high temperature refluxes (reflow) are carried out to the first interlayer dielectric layer 506 of deposition, until the first interlayer dielectric layer 506 deliquescing also can be flowed, utilize the depth-to-width ratio of the first interlayer dielectric layer 506 reflow and memory window and connection window, connection window 505 is filled up by the first interlayer dielectric layer 506 of deposition, and obtains smooth, fine and close deposition surface.Because memory window 504 can require to make according to device specification with the width dimensions being connected window 505, usual memory window 504 is than connecting window wide a lot (such as memory window 504 wide connects wide more than 1.5 times of window), when connecting window 505 and being filled, memory window 504 is filled not yet, but the first interlayer dielectric layer 506 can cover sidewall and the bottom of memory window 504, and ground floor dielectric layer 506 will be etched to side wall and will be retained in follow-up processing step in memory window 504, and the first interlayer dielectric layer 506 connected in window 505 will together with cover layer 502, as protective layer, the control grid layer 501 of protection below.As an embodiment, the temperature of high temperature reflux is 800 DEG C ~ 1000 DEG C or 900 DEG C ~ 980 DEG C.The step S43 of the present embodiment is actually PSGdep+PSGreflow process.
Please refer to Fig. 5 C, step S44 can remove the first interlayer dielectric layer in memory window 504 in two steps, particularly: first, chemical-mechanical planarization (PSGetch) is carried out to the surface of the first interlayer dielectric layer 506, remove unnecessary first interlayer dielectric layer 506 above cover layer 502; Then, wet corrosion technique or first interlayer dielectric layer of dry etch process to memory block I can be adopted to carry out Self-aligned etching (PSGetch), until remove the first interlayer dielectric layer in memory window 504 completely, wet corrosion technique described in the present embodiment can utilize hydrofluoric acid solution to carry out.Step S44 also a step can remove the first interlayer dielectric layer in memory window 504; particularly; wet corrosion technique is adopted to etch (PSGetch) the first all interlayer dielectric layers 506; until remove the first interlayer dielectric layer in memory window 504; expose the control grid layer 501 of below; now; the first interlayer dielectric layer 506 in the connection window 505 of bonding pad II is corroded certain thickness, but is enough to protect the control grid layer below it not by current etching and subsequent etching loss.
Please continue to refer to Fig. 5 C and 5D, in step S45, after removing the first interlayer dielectric layer in memory window 504, second interlayer dielectric layer 506a is deposited to whole device surface, until the second interlayer dielectric layer 506a in memory window 304 reaches certain thickness on memory window sidewall, the Step Coverage ability of described second interlayer dielectric layer 506a is higher than the first interlayer dielectric layer 506, not there is the characteristic of high temperature reflux simultaneously, can be silicon dioxide, silicon nitride, silicon oxynitride, ONO lamination, LPTEOS, be preferably LPTEOS; Then the second interlayer dielectric layer 506a above chemical mechanical planarization method removal cover layer 502 is adopted; Then, wet corrosion technique or dry etch process is adopted to carry out Self-aligned etching to the second interlayer dielectric layer 506a, remove dielectric layer segments between the second layer bottom memory window 504, dielectric layer segments between the second layer of reservation memory window 50 sidewall, to form side wall in memory window 504, the part control grid layer 501 bottom memory window 504 after Self-aligned etching, can be exposed.The step S44+S45 of the present embodiment is actually the process of PSGwet+SP1 (LPTEOS) dep+SP1etch, the object the first interlayer dielectric layer in memory window 504 being replaced with the second interlayer dielectric layer 506a is the Step Coverage ability of the interlayer dielectric layer ensureing memory window 504 sidewall, improves the film quality of side wall.
Please refer to Fig. 5 D, after step S45, can also carry out specific embodiment same as the prior art, be the subsequent process steps that semiconductor storage unit makes, and main purpose is the peripheral control circuits part forming other parts of memory device, connecting line and control storage.The secondarily etched processing step of control gate (SiNremove & CG2etch technique) after subsequent process steps such as comprises source electrode line manufacturing process steps (CGph/etch+SP2etch/SLCMP) and removes cover layer.
Wherein, when performing source electrode line manufacturing process steps (CGph/etch+SP2etch/SLCMP); first; with the side wall formed for mask; continue the control grid layer 501 that etching (CGph/etch) memory window 504 bottom-exposed goes out; form subwindow (not shown) for making source electrode line, by the control gate of the residue control grid layer 501 of side wall and the second interlayer dielectric layer and cover layer protection for follow-up formation memory cell bottom memory window 504.The step S45 of the present embodiment is actually CGph/etch process; wherein; the control grid layer 501 of bonding pad II is under the protection of the second interlayer dielectric layer 506b, the first interlayer dielectric layer 506 and cover layer 502, and completely not by the impact of each etching process, shape does not change.Then packing material is adopted to fill described subwindow.Wherein, when adopting packing material to fill described subwindow (SP2etch/SLCMP), two step packing materials can be adopted to fill described subwindow (SP2etch/SLCMP), particularly, first at the whole device surface deposition medium separator 508 of described subwindow, and etching removes the unnecessary buffer layer 508 above cover layer 502, to form one deck buffer layer 508 on subwindow surface, and retain source electrode line (SL) window; And then described subwindow continues sedimentary origin polar curve conductive layer 507, and carry out chemical-mechanical planarization to cover layer 502 surface, remove source electrode line conductive layer 507 unnecessary above cover layer 502, make source electrode line conductive layer 507 just fill and lead up memory window 504.
When performing the secondarily etched processing step of control gate (the SiNremove & CG2etch) after removing cover layer, only can remove the cover layer of bonding pad II, then etching removes the control grid layer that bonding pad II exposes, control grid layer below first interlayer dielectric layer 506 is retained, and forms connecting line; Also only can remove the cover layer of memory block I, then etching removes the control grid layer that memory block I exposes, and the control grid layer below the second interlayer dielectric layer 506a of memory block I is retained, and forms the control gate of memory block.The Semiconductor substrate 500 below control grid layer 501 can be exposed after performing SiNremove & CG2etch technique, then carry out at least one in floating boom etching technics, floating boom side wall technique, source/drain region ion implantation technology, form memory device.Concrete technology step is same as the prior art, does not repeat at this.
From the above mentioned, the manufacturing process of the semiconductor memory of the present embodiment is FGPH/SNetch → PSGdep → PSGreflow → PSGwetetch → SP1 (LPTEOS) dep → SP1etch → CGph/etch → SP2etch/SLCMP → SINremove/CGetch.Compared with traditional fabrication processing FGPH/SiNetch → SP1dep → SP1etch → CGph/etch → SP2etch/SLCMP → FLG2ph/SiNetch/HDPox/CMP → SiNremove & CG2etch, the present embodiment adopts an integration light shield protecting the pattern of light shield to combine traditional floating boom light shield and control gate, carry out a photoetching and etching technics, memory window can be formed in memory cell position simultaneously, formed at tie line position and connect window, and memory window is much wider than connecting window, and utilize the high temperature reflux of the first interlayer dielectric layer of deposition, directly connection window is filled up, thus by the etching technics of the memory cell process window of memory block and the connecting hole process window of bonding pad, fill process merges, eliminating bonding pad in traditional handicraft uses independent light shield FLG2mask to carry out mask, etching, the processing step of filling and grinding, namely by minimizing light shield, save the process time, reduce process costs, and further the first interlayer dielectric layer in memory window is replaced with the second higher interlayer dielectric layer of side wall film quality, improve the memory device performance of follow-up formation.
Obviously, those skilled in the art can carry out various change and modification to invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. a manufacture method for semiconductor memory, is characterized in that, comprising:
The Semiconductor substrate that one has memory block and a bonding pad is provided, is formed with control grid layer and cover layer on the semiconductor substrate;
With one can the integration light shield of the memory cell position of definition memory and the connecting hole position of bonding pad for mask, photoetching also etches described cover layer, memory window is formed in the memory cell position of memory block, be formed with connection window at the tie line position of bonding pad, and memory window is wider than connecting window;
Deposit the first interlayer dielectric layer at formation memory window with the device surface being connected window, and high temperature reflux is carried out to the first interlayer dielectric layer, to be filled up by connection window;
With the first interlayer dielectric layer and cover layer protection bonding pad, and form side wall by Self-aligned etching technique at described memory window sidewall.
2. manufacture method as claimed in claim 1, it is characterized in that, the temperature of described high temperature reflow processes is more than 800 DEG C.
3. manufacture method as claimed in claim 1, it is characterized in that, described first interlayer dielectric layer comprises at least one in phosphorosilicate glass, Pyrex and boron-phosphorosilicate glass.
4. manufacture method as claimed in claim 1, it is characterized in that, the step being formed side wall by Self-aligned etching technique in described memory window is comprised:
Remove the first interlayer dielectric layer above cover layer;
The first interlayer dielectric layer in Self-aligned etching memory window, removes the first interlayer dielectric layer bottom memory window, and the first interlayer dielectric layer retained by memory window sidewall is as described side wall.
5. manufacture method as claimed in claim 1, it is characterized in that, the step being formed side wall by Self-aligned etching technique in described memory window is comprised:
Remove the first interlayer dielectric layer in memory window and the first interlayer dielectric layer above cover layer;
Redeposited one deck second interlayer dielectric layer in described memory window, Self-aligned etching second interlayer dielectric layer, remove the second interlayer dielectric layer bottom memory window, the second interlayer dielectric layer retained by memory window sidewall is as described side wall, and the Step Coverage ability of described second interlayer dielectric layer is higher than the first interlayer dielectric layer.
6. the manufacture method as described in claim 4 or 5, is characterized in that, adopts wet corrosion technique to etch the first interlayer dielectric layer in memory window, to remove in memory window the first interlayer dielectric layer needing to remove.
7. manufacture method as claimed in claim 5, it is characterized in that, described second interlayer dielectric layer utilizes low-pressure chemical vapor deposition process to make.
8. manufacture method as claimed in claim 1, is characterized in that, after the described side wall of formation, also comprises:
With described side wall for mask, continue to adopt Self-aligned etching technique etching control grid layer, to form subwindow described depositing in control grid layer;
Packing material is adopted to fill described subwindow.
9. manufacture method as claimed in claim 8, is characterized in that, the step adopting packing material to fill described subwindow comprises:
Etch at the whole device surface deposition medium separator forming described subwindow, with to described subwindow filled media separator, and retain source electrode line window in described subwindow;
In source electrode line window, fill source electrode line conductive layer, and source electrode line conductive layer described in chemical-mechanical planarization is to cover surface.
10. manufacture method as claimed in claim 1, it is characterized in that, the depth over width ratio scope of described memory window is 1.1 ~ 1.6, and the depth over width ratio of described connection window is not less than 2.
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