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CN105047532B - The method that two-dimensional electron gas is obtained in SiC material - Google Patents

The method that two-dimensional electron gas is obtained in SiC material Download PDF

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CN105047532B
CN105047532B CN201510366654.0A CN201510366654A CN105047532B CN 105047532 B CN105047532 B CN 105047532B CN 201510366654 A CN201510366654 A CN 201510366654A CN 105047532 B CN105047532 B CN 105047532B
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申占伟
张峰
赵万顺
王雷
闫果果
刘兴昉
孙国胜
曾平
曾一平
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Xiamen Purple Silicon Semiconductor Technology Co ltd
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Abstract

本发明提供一种在SiC材料中获取二维电子气的方法,包括如下步骤:步骤1:取一晶面为(0001)的SiC衬底;步骤2:在晶面为(0001)的SiC衬底上制作晶面为(0001)的AlN层。本发明可以用在SiC基开关器件的制造,与已有的SiC基场效应晶体管相比,提高了沟道载流子的迁移率,从而降低器件的通态电阻,减小功耗。

The invention provides a method for obtaining two-dimensional electron gas in a SiC material, comprising the following steps: Step 1: take a SiC substrate with a (0001) crystal plane; Step 2: take a SiC substrate with a (0001) crystal plane An AlN layer with a crystal plane of (0001) is fabricated on the bottom. The invention can be used in the manufacture of SiC-based switching devices. Compared with existing SiC-based field effect transistors, the invention improves the mobility of channel carriers, thereby reducing the on-state resistance of devices and reducing power consumption.

Description

在SiC材料中获取二维电子气的方法A method for obtaining two-dimensional electron gas in SiC materials

技术领域technical field

本发明涉及一种二维电子气的获取方法,尤其是涉及一种用于SiC材料二维电子气的获取方法。The invention relates to a method for obtaining a two-dimensional electron gas, in particular to a method for obtaining a two-dimensional electron gas for SiC materials.

背景技术Background technique

第三代半导体碳化硅(SiC)是一种具有优良的物理特性、电学特性的宽禁带半导体材料。它具有宽带隙、高击穿场强、高热导率等特点,因此非常适合于研制高温、大功率、高频电力电子器件。The third-generation semiconductor silicon carbide (SiC) is a wide bandgap semiconductor material with excellent physical and electrical properties. It has the characteristics of wide band gap, high breakdown field strength, high thermal conductivity, etc., so it is very suitable for the development of high temperature, high power, high frequency power electronic devices.

SiC是目前唯一可以氧化形成SiO2的化合物半导体,然而在SiC和SiO2界面存在着很高的界面态密度。这主要是由于器件栅氧化物是通过氧化SiC形成的,在氧化过程中,SiC中的C元素部分氧化形成CO和CO2,在栅氧化物与SiC基底之间留下较多界面态,剩余一些C元素未能氧化,形成了C团簇,使得栅氧化物与SiC基底界面质量不如SiO2与SiC高。这些界面态不仅减少了SiC基MOS器件沟道中导电载流子,同时会形成散射中心进一步降低沟道迁移率,使得器件的导通电阻高,工作频率低。即使存在如JFET类的器件来避免MOS界面,但由于SiC中杂质的扩散系数非常低,多采用离子注入的方法对其掺杂,注入离子的激活温度相当高,这都会造成较大的晶体损伤因而迁移率并不是足够高。这就需要寻找一种新的基于SiC的载流子导电界面,使得能产生高密度、高迁移率的沟道载流子。SiC is currently the only compound semiconductor that can be oxidized to form SiO 2 , but there is a high interface state density at the interface between SiC and SiO 2 . This is mainly because the device gate oxide is formed by oxidizing SiC. During the oxidation process, the C element in SiC is partially oxidized to form CO and CO 2 , leaving more interface states between the gate oxide and the SiC substrate, and the remaining Some C elements failed to oxidize, forming C clusters, making the interface quality between gate oxide and SiC substrate not as high as SiO 2 and SiC. These interface states not only reduce the conductive carriers in the channel of SiC-based MOS devices, but also form scattering centers to further reduce the channel mobility, resulting in high on-resistance and low operating frequency of the device. Even if there are devices such as JFETs to avoid MOS interfaces, since the diffusion coefficient of impurities in SiC is very low, it is often doped by ion implantation, and the activation temperature of implanted ions is quite high, which will cause large crystal damage. Thus the mobility is not high enough. This requires the search for a new SiC-based carrier-conducting interface that enables the generation of high-density, high-mobility channel carriers.

发明内容Contents of the invention

本发明的目的在于,提供一种在SiC材料中获取二维电子气的方法,其是针对目前传统的SiC基MOS器件界面态密度高,载流子迁移率低的特点,提出在SiC表面沉积一种具有高介电常数、高自发极化、高临界电场和晶格匹配的电介质。使得该电介质与SiC之间通过极化产生高密度的二维电子气。The purpose of the present invention is to provide a method for obtaining two-dimensional electron gas in SiC materials, which is aimed at the characteristics of high interface state density and low carrier mobility of traditional SiC-based MOS devices, and proposes to deposit A dielectric with high dielectric constant, high spontaneous polarization, high critical electric field, and lattice matching. A high-density two-dimensional electron gas is generated between the dielectric and SiC through polarization.

本发明的第一实施例提供一种在SiC材料中获取二维电子气的方法,包括如下步骤:The first embodiment of the present invention provides a method for obtaining a two-dimensional electron gas in a SiC material, comprising the following steps:

步骤1:取一晶面为(0001)的SiC衬底;Step 1: Take a SiC substrate whose crystal plane is (0001);

步骤2:在晶面为(0001)的SiC衬底上制作晶面为(0001)的AlN层。Step 2: Fabricate an AlN layer with (0001) crystal plane on the SiC substrate with (0001) crystal plane.

本发明的第二实施例提供一种在SiC材料中获取二维电子气的方法,包括如下步骤:The second embodiment of the present invention provides a method for obtaining a two-dimensional electron gas in a SiC material, comprising the following steps:

步骤1:取一晶面为的SiC衬底;Step 1: Take a crystal plane as SiC substrate;

步骤2:在晶面为的SiC衬底上制作晶面为(0001)的AlN层。Step 2: On the crystal face for An AlN layer with crystal plane (0001) was fabricated on the SiC substrate.

本发明的第三实施例提供一种在SiC材料中获取二维电子气的方法,包括如下步骤:The third embodiment of the present invention provides a method for obtaining a two-dimensional electron gas in a SiC material, comprising the following steps:

步骤1:取一晶面为(0001)的SiC衬底;Step 1: Take a SiC substrate whose crystal plane is (0001);

步骤2:在晶面为(0001)的SiC衬底上制作晶面为(0001)的AlN层;Step 2: making an AlN layer with a crystal plane of (0001) on a SiC substrate with a crystal plane of (0001);

步骤3:在晶面为(0001)的AlN层上制作晶面为(0001)的AlxGa1-xN层。Step 3: Fabricate an AlxGa1 - xN layer with a (0001) crystal plane on the AlN layer with a (0001) crystal plane.

本发明的第四实施例提供一种在SiC材料中获取二维电子气的方法,包括如下步骤:The fourth embodiment of the present invention provides a method for obtaining a two-dimensional electron gas in a SiC material, comprising the following steps:

步骤1:取一晶面为(0001)的SiC衬底;Step 1: Take a SiC substrate whose crystal plane is (0001);

步骤2:在晶面为(0001)的SiC衬底上制作晶面为的AlN层;Step 2: Fabricate a crystal plane of (0001) on a SiC substrate with a crystal plane of AlN layer;

步骤3:在晶面为的AlN层上制作晶面为的AlxGa1-xN层。Step 3: On the crystal plane for The AlN layer is fabricated on crystal planes as AlxGa1 - xN layer.

本发明的第五实施例提供一种在SiC材料中获取二维电子气的方法,包括如下步骤:The fifth embodiment of the present invention provides a method for obtaining a two-dimensional electron gas in a SiC material, comprising the following steps:

步骤1:取一晶面为的SiC衬底;Step 1: Take a crystal plane as SiC substrate;

步骤2:在晶面为的SiC衬底上制作晶面为(0001)的AlN层;Step 2: On the crystal face for Fabricate an AlN layer whose crystal plane is (0001) on the SiC substrate;

步骤3:在晶面为(0001)的AlN层上制作晶面为(0001)的AlxGa1-xN层。Step 3: Fabricate an AlxGa1 - xN layer with a (0001) crystal plane on the AlN layer with a (0001) crystal plane.

本发明可以用在SiC基开关器件的制造,与已有的SiC基场效应晶体管相比,提高了沟道载流子的迁移率,从而降低器件的通态电阻,减小功耗。The invention can be used in the manufacture of SiC-based switching devices. Compared with existing SiC-based field effect transistors, the invention improves the mobility of channel carriers, thereby reducing the on-state resistance of devices and reducing power consumption.

附图说明Description of drawings

为进一步说明本发明的技术内容,以下结合附图和实施例对本发明做进一步详细描述,其中:In order to further illustrate the technical content of the present invention, the present invention is described in further detail below in conjunction with accompanying drawing and embodiment, wherein:

图1是本发明实施例1的结构示意图;Fig. 1 is the structural representation of embodiment 1 of the present invention;

图2是本发明实施例2的结构示意图;Fig. 2 is the structural representation of embodiment 2 of the present invention;

图3是本发明实施例3的结构示意图;Fig. 3 is the structural representation of embodiment 3 of the present invention;

图4是本发明实施例4的结构示意图;Fig. 4 is the structural representation of embodiment 4 of the present invention;

图5是本发明实施例5的结构示意图。Fig. 5 is a schematic structural diagram of Embodiment 5 of the present invention.

具体实施方式Detailed ways

(1)在SiC衬底材料之上可以有以下几种薄膜组合:(a)AlN(b)AlN/AlxGa1-xN薄膜。根据纤锌矿结构自发极化和压电极化特性,AlxGa1-xN材料的晶格常数小于SiC衬底的,即AlxGa1-xN材料生长在SiC材料上受到压应力产生与本身自发极化相反向的压电极化,而衬底材料的压电极化为0。两种材料在界面处会由于极化强度的变化产生极化感应电荷,其计算公式如下:(1) There can be the following film combinations on the SiC substrate material: (a) AlN (b) AlN/Al x Ga 1-x N film. According to the spontaneous polarization and piezoelectric polarization characteristics of the wurtzite structure, the lattice constant of the Al x Ga 1-x N material is smaller than that of the SiC substrate, that is, the Al x Ga 1-x N material grown on the SiC material is subjected to compressive stress The piezoelectric polarization opposite to its own spontaneous polarization is generated, and the piezoelectric polarization of the substrate material is 0. The two materials will generate polarization-induced charges at the interface due to the change of polarization intensity, and the calculation formula is as follows:

ρ=-{[Psp(AlxGa1-xN)+Ppe(AlxGa1-xN)]-[Psp(SiC)+Ppe(SiC)]}ρ=-{[P sp (Al x Ga 1-x N)+P pe (Al x Ga 1-x N)]-[P sp (SiC)+P pe (SiC)]}

Psp和Ppe分别是相应材料的自发极化和压电极化。Psp and Ppe are the spontaneous and piezoelectric polarizations of the corresponding materials, respectively.

(2)根据(1)中的计算公式,两种材料的界面处需形成正的极化面电荷才能吸引二维电子气到异质结的势阱中,由于材料之间的极化方向和大小不同,材料的生长需满足一定的晶面取向。即Al(Ga)面的AlxGa1-xN材料生长在(0001)面的SiC衬底上;或者Al组份小于0.6左右的N面的AlxGa1-xN材料生长在(0001)面SiC衬底上;或者Al组份大于0.6左右的Al(Ga)面的AlxGa1-xN材料生长在面SiC衬底上。(2) According to the calculation formula in (1), positive polarized surface charges need to be formed at the interface of the two materials to attract the two-dimensional electron gas to the potential well of the heterojunction. Due to the polarization direction and The size of the material is different, and the growth of the material needs to meet a certain crystal plane orientation. That is, the Al x Ga 1-x N material of the Al(Ga) surface is grown on the (0001) SiC substrate; or the Al x Ga 1-x N material of the N surface with an Al composition less than about 0.6 is grown on the (0001 ) surface SiC substrate; or the Al x Ga 1-x N material on the Al (Ga) surface with an Al composition greater than 0.6 is grown on on the SiC substrate.

现结合附图和实施例对本发明做进一步陈述:Now in conjunction with accompanying drawing and embodiment the present invention is further stated:

实施例1Example 1

请参阅图1所示,本发明提供一种在SiC材料中获取二维电子气的方法,包括如下步骤:Please refer to Fig. 1, the present invention provides a method for obtaining two-dimensional electron gas in SiC material, comprising the following steps:

步骤1:取一晶面为(0001)的SiC衬底1,该晶面为(0001)的SiC衬底1是具有六方纤锌矿的晶体结构,所述晶面为(0001)的衬底1是零偏角的晶面;Step 1: Take a SiC substrate 1 with a crystal plane of (0001), the SiC substrate 1 with a crystal plane of (0001) has a hexagonal wurtzite crystal structure, and the crystal plane is a substrate of (0001) 1 is the crystal plane with zero off angle;

步骤2:在晶面为(0001)的SiC衬底1上制作晶面为(0001)的AlN层2。Step 2: Fabricate an AlN layer 2 with a (0001) crystal plane on a SiC substrate 1 with a (0001) crystal plane.

其中SiC衬底1为半绝缘的材料,厚度为3-10μm,AlN层2厚度为5nm-50nm,可作适当的n型掺杂来补偿两种材料界面处二维电子的损失。沉积材料采用的生长方法可以是化学气相沉积、物理气相沉积、原子层沉积的一种。Wherein the SiC substrate 1 is a semi-insulating material with a thickness of 3-10 μm, and the thickness of the AlN layer 2 is 5nm-50nm, which can be properly n-type doped to compensate for the loss of two-dimensional electrons at the interface of the two materials. The growth method adopted for the deposited material may be one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

实施例2Example 2

请参阅图2所示,本发明提供一种在SiC材料中获取二维电子气的方法,包括如下步骤:Please refer to Fig. 2, the present invention provides a method for obtaining two-dimensional electron gas in SiC material, comprising the following steps:

步骤1:取一晶面为的SiC衬底1,该晶面为的SiC衬底1,是具有六方纤锌矿的晶体结构,所述晶面为的SiC衬底1,是零偏角的晶面;Step 1: Take a crystal plane as SiC substrate 1, the crystal plane is The SiC substrate 1 has a crystal structure of hexagonal wurtzite, and the crystal planes are The SiC substrate 1 is a crystal plane with zero off-angle;

步骤2:在晶面为的SiC衬底1,上制作晶面为(0001)的AlN层2。Step 2: On the crystal face for An AlN layer 2 with a (0001) crystal plane is fabricated on a SiC substrate 1 .

其中SiC衬底1,为半绝缘的材料,厚度为3-10μm,AlN层2厚度为5nm-50nm,可作适当的n型掺杂来补偿两种材料界面处二维电子的损失。沉积材料采用的生长方法可以是化学气相沉积、物理气相沉积、原子层沉积的一种。Wherein the SiC substrate 1 is a semi-insulating material with a thickness of 3-10 μm, and the thickness of the AlN layer 2 is 5nm-50nm, which can be properly n-type doped to compensate for the loss of two-dimensional electrons at the interface of the two materials. The growth method adopted for the deposited material may be one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

实施例3Example 3

请参阅图3所示,本发明提供一种在SiC材料中获取二维电子气的方法,包括如下步骤:Please refer to Fig. 3, the present invention provides a method for obtaining two-dimensional electron gas in SiC material, comprising the following steps:

步骤1:取一晶面为(0001)的SiC衬底1,该晶面为(0001)的SiC衬底1是具有六方纤锌矿的晶体结构,所述晶面为(0001)的衬底1是零偏角的晶面;Step 1: Take a SiC substrate 1 with a crystal plane of (0001), the SiC substrate 1 with a crystal plane of (0001) has a hexagonal wurtzite crystal structure, and the crystal plane is a substrate of (0001) 1 is the crystal plane with zero off angle;

步骤2:在晶面为(0001)的SiC衬底1上制作晶面为(0001)的AlN层2;Step 2: making an AlN layer 2 with a (0001) crystal plane on a SiC substrate 1 with a (0001) crystal plane;

步骤3:在晶面为(0001)的AlN层2上制作晶面为(0001)的AlxGa1-xN层3,该AlxGa1-xN层3中的Al组份x从0到1变化,即该材料代表AlN、AlGaN、GaN的一种,即x为0是GaN材料,x为1是AlN材料,0<x<1为AlGaN。Step 3: on the AlN layer 2 with a crystal plane of (0001), make an AlxGa1 - xN layer 3 with a crystal plane of (0001), the Al composition x in the AlxGa1 - xN layer 3 is from It varies from 0 to 1, that is, the material represents one of AlN, AlGaN, and GaN, that is, when x is 0, it is a GaN material, when x is 1, it is an AlN material, and if 0<x<1, it is AlGaN.

其中SiC衬底1为半绝缘的材料,厚度为3-10μm。AlN插入层2厚度为0-2nm,即可选择不插入该AlN层2,而1nm左右的厚度是因为AlN层与4H-SiC晶格匹配较好,因而作为缓冲层可以有效降低界面态密度对极化电荷的屏蔽作用,从而提高二维电子气的浓度及电子迁移率。AlxGa1-xN层3厚度为15nm-30nm,可作适当的n型掺杂以提供足够多的二维电子。沉积材料采用的生长方法可以是化学气相沉积、物理气相沉积、原子层沉积的一种。Wherein the SiC substrate 1 is a semi-insulating material with a thickness of 3-10 μm. The thickness of the AlN insertion layer 2 is 0-2nm, so you can choose not to insert the AlN layer 2, and the thickness of about 1nm is because the AlN layer has a better lattice match with 4H-SiC, so as a buffer layer, it can effectively reduce the impact of the interface state density. The shielding effect of polarized charges increases the concentration and electron mobility of the two-dimensional electron gas. The thickness of the AlxGa1 - xN layer 3 is 15nm-30nm, which can be properly n-type doped to provide enough two-dimensional electrons. The growth method adopted for the deposited material may be one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

实施例4Example 4

请参阅图4所示,本发明提供一种在SiC材料中获取二维电子气的方法,包括如下步骤:Please refer to Figure 4, the present invention provides a method for obtaining two-dimensional electron gas in SiC materials, including the following steps:

步骤1:取一晶面为(0001)的SiC衬底1,该晶面为(0001)的SiC衬底1是具有六方纤锌矿的晶体结构,所述晶面为(0001)的衬底1是零偏角的晶面;Step 1: Take a SiC substrate 1 with a crystal plane of (0001), the SiC substrate 1 with a crystal plane of (0001) has a hexagonal wurtzite crystal structure, and the crystal plane is a substrate of (0001) 1 is the crystal plane with zero off angle;

步骤2:在晶面为(0001)的SiC衬底1上制作晶面为的AlN层2;Step 2: Fabricate a SiC substrate 1 with a crystal plane of (0001) as AlN layer 2;

步骤3:在晶面为的AlN层2,上制作晶面为的AlxGa1-xN层3,,该晶面为的AlxGa1-xN层3,中的Al组份x小于0.6左右。Step 3: On the crystal plane for AlN layer 2, on which the crystal plane is fabricated as Al x Ga 1-x N layer 3, the crystal plane is Al composition x in the AlxGa1 - xN layer 3 is less than about 0.6.

其中SiC衬底1为半绝缘的材料,厚度为3-10μm。AlN插入层2,厚度为0-2nm,AlxGa1-xN层3厚度为15nm-30nm,可作适当的n型掺杂以提供足够多的二维电子。沉积材料采用的生长方法可以是化学气相沉积、物理气相沉积、原子层沉积的一种。Wherein the SiC substrate 1 is a semi-insulating material with a thickness of 3-10 μm. The AlN insertion layer 2 has a thickness of 0-2nm, and the AlxGa1 - xN layer 3 has a thickness of 15nm-30nm, which can be properly n-type doped to provide enough two-dimensional electrons. The growth method adopted for the deposited material may be one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

实施例5Example 5

请参阅图5所示,本发明提供一种在SiC材料中获取二维电子气的方法,包括如下步骤:Please refer to Fig. 5, the present invention provides a method for obtaining two-dimensional electron gas in SiC material, comprising the following steps:

步骤1:取一晶面为的SiC衬底1,,该晶面为的SiC衬底1,是具有六方纤锌矿的晶体结构,所述晶面为的SiC衬底1,是零偏角的晶面;Step 1: Take a crystal plane as SiC substrate 1, the crystal plane is The SiC substrate 1 has a crystal structure of hexagonal wurtzite, and the crystal planes are The SiC substrate 1 is a crystal plane with zero off-angle;

步骤2:在晶面为的SiC衬底1,上制作晶面为(0001)的AlN层2;Step 2: On the crystal face for A SiC substrate 1, on which an AlN layer 2 with a crystal plane of (0001) is fabricated;

步骤3:在晶面为(0001)的AlN层2上制作晶面为(0001)的AlxGa1-xN层3,该晶面为(0001)的AlxGa1-xN层3中的Al组份x大于0.6左右。Step 3: Fabricate an AlxGa1 - xN layer 3 with a (0001) crystallographic plane on the AlN layer 2 with a (0001) crystallographic plane, the AlxGa1 - xN layer 3 with a (0001) crystallographic plane The Al composition x in it is greater than about 0.6.

其中SiC衬底1为半绝缘的材料,厚度为3-10μm。AlN插入层2,厚度为0-2nm,AlxGa1-xN层3厚度为15nm-30nm,可作适当的n型掺杂以提供足够多的二维电子。沉积材料采用的生长方法可以是化学气相沉积、物理气相沉积、原子层沉积的一种。Wherein the SiC substrate 1 is a semi-insulating material with a thickness of 3-10 μm. The AlN insertion layer 2 has a thickness of 0-2nm, and the AlxGa1 - xN layer 3 has a thickness of 15nm-30nm, which can be properly n-type doped to provide enough two-dimensional electrons. The growth method adopted for the deposited material may be one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

以上所述的具体实施例,对本发明的目的、技术方案和有益效果进行了进一步详细说明,所应理解的是,以上所述仅为本发明的具体实施例而已,并不用于限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (5)

1. a kind of method obtaining two-dimensional electron gas in SiC material, includes the following steps:
Step 1:It is the SiC substrate of (0001) to take a crystal face, and the SiC substrate of (0001) is the crystalline substance for having hexagonal wurtzite Body structure, and be the crystal face at zero bias angle;
Step 2:The AlN layers that crystal face is (0001) are made in the SiC substrate that crystal face is (0001).
2. a kind of method obtaining two-dimensional electron gas in SiC material, includes the following steps:
Step 1:The crystal face is taken to beSiC substrate, the SiC substrate of (0001) is the crystalline substance for having hexagonal wurtzite Body structure, and be the crystal face at zero bias angle;
Step 2:It is in crystal faceSiC substrate on make crystal face be (0001) AlN layers.
3. a kind of method obtaining two-dimensional electron gas in SiC material, includes the following steps:
Step 1:It is the SiC substrate of (0001) to take a crystal face, and the SiC substrate of (0001) is the crystalline substance for having hexagonal wurtzite Body structure, and be the crystal face at zero bias angle;
Step 2:The AlN layers that crystal face is (0001) are made in the SiC substrate that crystal face is (0001);
Step 3:The Al that crystal face is (0001) is made on the AlN layers that crystal face is (0001)xGa1-xN layers, wherein crystal face is (0001) AlxGa1-x0 < x < 1 of Al components in N layers.
4. a kind of method obtaining two-dimensional electron gas in SiC material, includes the following steps:
Step 1:It is the SiC substrate of (0001) to take a crystal face, and the SiC substrate of (0001) is the crystalline substance for having hexagonal wurtzite Body structure, and be the crystal face at zero bias angle;
Step 2:Making crystal face in the SiC substrate that crystal face is (0001) isAlN layers;
Step 3:It is in crystal faceAlN layers on make crystal face beAlxGa1-xN layers, wherein crystal face is (0001) AlxGa1-xAl components x in N layers is less than 0.6.
5. a kind of method obtaining two-dimensional electron gas in SiC material, includes the following steps:
Step 1:The crystal face is taken to beSiC substrate, the SiC substrate of (0001) is the crystalline substance for having hexagonal wurtzite Body structure, and be the crystal face at zero bias angle;
Step 2:It is in crystal faceSiC substrate on make crystal face be (0001) AlN layers;
Step 3:The Al that crystal face is (0001) is made on the AlN layers that crystal face is (0001)xGa1-xN layers, wherein crystal face is (0001) AlxGa1-xAl components x in N layers is more than 0.6.
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Publication number Priority date Publication date Assignee Title
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104600108A (en) * 2014-12-31 2015-05-06 中国电子科技集团公司第五十五研究所 Nitride high electron mobility transistor epitaxial structure and preparation method thereof

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* Cited by examiner, † Cited by third party
Title
AlGaN/AlN/GaN/SiC HEMT structure with high mobility GaN thin layer as channel grown by MOCVD;Xiaoliang Wang等;《Journal of Crystal Growth》;20061208;第298卷;第835-839页 *

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