CN105045561A - Pseudo-random number generating method - Google Patents

Abstract

The present invention discloses a pseudo-random number generating method which is a method for carrying out operation on more than two pseudo-random number generators to generate high-speed pseudo-random numbers with long sequence periods, wherein generation of each pseudo-random number is based on a parallel structure longest linear feedback shift register circuit; the pseudo-random numbers generated by the pseudo-random number generators which are requested to participate in operation are not related mutually; the uniformly distributed pseudo-random numbers with a plurality of data bits can be generated in real time, the pseudo-random numbers which are of other distribution structures also can be generated, and digital white noise signals with wide bands also can be generated; and parameters of the pseudo-random numbers, such as a mean value, variances and the like, are adjustable.

Description

A Pseudo-Random Number Generation Method

technical field

The invention relates to the field of signal generation, in particular to a pseudo-random number generation method.

Background technique

The power spectral density function of an ideal white noise signal is a constant at all frequencies, and its power is infinite, so it cannot be realized physically. A noise signal whose power spectral density function is approximately a constant in the frequency range of interest is called a band-limited white noise signal, which can be realized physically. Band-limited white noise signals have properties similar to ideal white noise signals. The bandwidth of the actual circuit system is limited. As long as the frequency range of the band-limited white noise signal generated is wider than the bandwidth of the actual circuit, its influence on the signal system is the same as that of the ideal white noise signal with the same spectral density and the same probability distribution. of. After the voltage of the analog white noise signal is digitized, a more ideal random number can be formed.

Noise signal generation is traditionally based on physical techniques. For example, using the radioactivity of radioactive substances, using detectors to count them to generate random numbers. The noise signal is generated by the discharge of the gas discharge tube. In the 1960s and 1970s, gas discharge tubes were widely used as noise standards at home and abroad. The above methods of generating noise are technically complex and not very safe, so a solid-state noise generation technology based on circuit noise was born. For example, the thermal noise of resistors or the noise of semiconductor devices can be used to generate broadband noise signals, as shown in Figure 1.

The fluctuating noise generated by the random thermal movement of carriers in the conductor is called thermal noise, and the thermal noise voltage is related to temperature, and its mean square value is:

V ² =4kTBR

Where R is the resistance of the conductor, B is the bandwidth of the circuit, k is Boltzmann's constant, and T is the absolute temperature. Because thermal noise originates from the movement of majority carriers, its instantaneous amplitude obeys a Gaussian distribution with a mean value of zero. When the temperature and resistance are constant, the spectral density of thermal noise voltage has nothing to do with frequency. Therefore, the thermal noise of a resistor is Gaussian white noise.

A semiconductor diode is reverse-biased and works in an avalanche breakdown state. In the avalanche region, avalanche shot noise is generated due to the random fluctuation of the electron-hole pair generation rate. At a certain avalanche frequency, avalanche shot noise is similar to white noise, and its noise power spectral density is uniformly distributed. Therefore, a diode operating in reverse in the avalanche breakdown state can be an ideal noise source. The avalanche breakdown of Zener diode or PIN diode is used to generate noise signal, and then amplified by broadband to generate broadband noise signal.

The solid-state noise generator has a wide frequency range and can cover the microwave frequency band. The probability density of the output signal conforms to the Gaussian distribution, which belongs to the Gaussian white noise signal. The disadvantage of the traditional noise signal generator is that the probability distribution of the output signal cannot be adjusted, and the adjustment of the spectral density is difficult. In practical applications, digital random numbers or noise signals are often required. The output of the solid-state noise generator is quantized to generate a digital noise signal.

The method for generating true random numbers based on physical technology is described below. Using the noise generated by the avalanche breakdown of the Zener diode, the analog broadband white noise signal can be generated through DC blocking and broadband amplification, and the noise signal is Gaussian distributed. Using a high-speed A/D converter to digitize the analog noise signal can produce a Gaussian-distributed digital noise signal. The block diagram is shown in Figure 2. In the figure, Vcc is a DC voltage source, and R is a current-limiting resistor, so that the diode D works in the avalanche breakdown region. L provides a DC path and isolates the AC signal at the same time, C is a DC blocking capacitor, and couples the noise signal to the output at the same time, N is an amplifier circuit. The quantized noise signal is compared with the value 0. If the value is greater than or equal to 0, it will output 1, and if it is less than 0, it will output 0. In this way, a uniformly distributed binary random number is generated. The block diagram is shown in Figure 3. Of course, a high-speed analog comparator can also be used to convert the analog noise signal into a binary digital noise signal.

A random number with a finite sequence period is called a pseudorandom number, and a random signal with a finite sequence period is called a pseudorandom signal. The longer the sequence period of the pseudo-random number is, the better its statistical properties are, and the closer it is to a true random number. Due to the complexity of the generation circuit of true random numbers, in engineering, pseudo-random numbers are often used instead of true random numbers, because their mathematical properties are similar and can meet engineering needs.

A computer can be used to generate uniformly distributed pseudo-random numbers conveniently. The methods for generating pseudo-random numbers include the square method, the multiplication congruence method, and the linear congruence algorithm. The quality of the pseudo-random numbers generated by the square method and the multiplication congruence method is not high. On computers, the linear congruential algorithm is commonly used to generate pseudorandom numbers. The linear congruence method recursion formula is:

rand(n)=(rand(n-1)*mult+inc) mod M

Where rand(n) is the current random number, rand(n-1) is the random number at the previous moment, mult is the multiplier factor, M=2 and ^L is the modulus value. inc is an increment, usually an odd number smaller than M can be used. The function rand() in the C language compiler can generate random integers between 0 and 32767. The formula for generating pseudo-random numbers in VC is:

rand(n)=((rand(n-1)*214013+2531011)mod65536)&0x7fff

The formula for generating pseudo-random numbers in BC is:

rand(n)=((rand(n-1)*22695477+1)mod65536)&0x7fff

Using digital technology, after generating uniformly distributed pseudo-random numbers, other distributed pseudo-random numbers can be easily generated, such as Gaussian distribution pseudo-random sequences, and pseudo-random digital white noise signals with adjustable mean, variance, and spectral density.

The m-sequence, also known as the longest linear feedback shift register sequence, is a binary pseudo-random sequence that has been studied in depth. Commonly used in spread spectrum communication, ranging, circuit testing and other fields. It is generated by a shift register with linear feedback, as shown in Figure 4. In the figure, the state of a bit shift register is represented by a _i , a _i =0 or a _i =1, and i is an integer. The connection state of the feedback line is represented by C _i , where C _i =0 means that the feedback line is disconnected, and C _i =1 means that the feedback exists.

Under the control of the clock signal, the shift register shifts the output step by step. Due to the existence of feedback, if the initial state is all "0", the result obtained after shifting is still all "0", so the state of all "0" should be avoided; and because n-level shift registers have 2 ⁿ possible Different states, except for all "0" states, there are 2 ⁿ -1 states available. Every time it is shifted, a state will appear. After shifting several times, the previous state must be repeated, and the subsequent process will repeat itself. That is to say, the output signal must be a periodic signal. Different positions of the feedback line will result in different sequences of different periods. It is hoped to find a suitable linear feedback logic that can make the sequence generated by the shift register the longest, that is, the period M=2 ⁿ -1. According to the connection relationship in the figure, the input obtained at the left end of the shift register group can be written as:

a _n ＝c ₁ a _n-1 ⊕c ₂ a _n-2 ⊕c ₃ a _n-3 ⊕...⊕c _n-1 a ₁ ⊕c _n a ₀

Where ⊕ is an XOR operator. When choosing an appropriate linear feedback logic, the output sequence is an m-sequence with a period of 2 ⁿ -1.

The value of C _i determines the feedback connection, sequence structure and period of the specific shift register. In order to facilitate the expression of the state of C _i , a polynomial is introduced:

f(x)＝c ₀ +c ₁ x+c ₂ x ² +...+c _n-1 x ^n-1 +c _n x ⁿ

This formula is called the characteristic polynomial. When the characteristic polynomial of a linear feedback shift register is known, the structure of the linear feedback shift register can be determined. It has been proved that if the characteristic polynomial of the linear feedback shift register is a primitive polynomial, the linear feedback shift register can generate m sequences. This is a necessary and sufficient condition for the linear feedback shift register to generate m-sequences. In practical applications, the length of the m-sequence needs to be determined first according to the number of data bits, and then the feedback logic of the m-sequence generator can be easily obtained by looking up the table. A linear feedback shift register of a certain length has many primitive polynomials corresponding to different m-sequences. Commonly used primitive polynomials have been given in the form of tables. For example, when n=31, f(x)=1+x ³ +x ³¹ is a primitive polynomial, which can generate m sequences. Corresponding to C ₀ =1, C ₃ =1, and C ₃₁ =1 in the formula. The sequence period is 2 ³¹ -1, which is exactly a Mersenne prime. The m-sequence has the following properties:

(1) Balance characteristics. In each 2 ⁿ -1 period of the m sequence, the number of occurrences of "1" symbols is 2 ^n-1 times, and the number of occurrences of "0" symbols is 2 ^n-1 -1 times, that is, the number of occurrences of "0" The number is always one less than the number of "1", which shows that the sequence mean is extremely small.

(2) Run length characteristics. The run length refers to the collective name of symbols that are arranged continuously in a sequence period and take the same value, and the number of symbols in a run length is the run length. There are 2 ^n-1 runs in the m sequence. Among them, the number of runs with length k (1≤k≤n-2) accounts for 2 ^-k of the total number of runs, the number of runs with "0"s of length n-1 is 1, and the number of runs with "1"s with length n The number is 1.

(3) Shift-add feature. An m-sequence {a _n } is added modulo 2 to another different sequence {a _n+k } generated after any number of delayed shifts, and the obtained m-sequence is still the delayed shifted sequence of the m-sequence. For example, shifting 01001l1 to the right once produces another sequence 1010011, and the sequence after adding modulo 2 is 1l10100, which is equivalent to the sequence obtained by shifting the original sequence to the right three times.

(4) The m-sequence has excellent autocorrelation properties, and its autocorrelation function:

$\mathrm{<span\; class="notranslate">\; R</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; \&tau;</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\left\{\begin{array}{cc}\mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; \&tau;</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}\\ <span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; m</span>}& \mathrm{<span\; class="notranslate">\; \&tau;</span>}<span\; class="notranslate">\; \&NotEqual;</span>\mathrm{<span\; class="notranslate">\; 0</span>}\end{array}\right.$

There are usually many m-sequences in the longest linear feedback shift register. For example, there are 2 m-sequences in the 3-bit longest linear feedback shift register, 2 m-sequences in the 4-bit longest linear feedback shift register, 6 m-sequences in the 5-bit longest linear feedback shift register, and 6 There are 6 m-sequences in the longest linear feedback shift register of 7 bits, 18 m-sequences in the longest linear feedback shift register of 7 bits, 16 m-sequences in the longest linear feedback shift register of 8 bits, and 16 m-sequences in the 9-bit longest linear feedback shift register. There are 48 m sequences in the longest linear feedback shift register, 60 m sequences in the longest linear feedback shift register of 10 bits, 176 m sequences in the longest linear feedback shift register of 11 bits, and 176 m sequences in the longest linear feedback shift register of 12 bits. There are 144 m-sequences in the linear feedback shift register, 630 m-sequences in the longest linear feedback shift register of 13 bits, 756 m-sequences in the longest linear feedback shift register of 14 bits, and the longest linear feedback shift register of 15 bits There are 1800 m-sequences in the shift register. With the increase of the number of bits of the longest linear feedback shift register, the number of m-sequences increases rapidly.

There are 158 m-sequences in the 19-bit longest linear feedback shift register with 5 coefficients. Its primitive polynomials are 1+x+x ² +x ⁵ +x ¹⁹ , 1+x+x ² +x ⁶ +x ¹⁹ , 1+x+x ⁴ +x ⁶ +x ¹⁹ , 1+x ³ +x ⁴ +x ⁶ +x ¹⁹ , 1+x+x ⁵ +x ⁶ +x ¹⁹ , 1+x+x ⁴ +x ⁷ +x ¹⁹ , 1+x ⁵ +x ⁶ +x ⁷ +x ¹⁹ , 1+ x+x ⁶ +x ⁸ +x ¹⁹ ,..., 1+x ¹³ +x ¹⁷ +x ¹⁸ +x ¹⁹ , 1+x ¹⁴ +x ¹⁷ +x ¹⁸ +x ¹⁹ . There are 4 m-sequences for the 25-bit longest linear feedback shift register with 3 coefficients. Its primitive polynomials are 1+x ³ +x ²⁵ , 1+x ⁷ +x ²⁵ , 1+x ¹⁸ +x ²⁵ , 1+x ²² +x ²⁵ . A primitive polynomial usually has a mirror primitive polynomial, the number of coefficients of the two primitive polynomials is the same, and the order of the coefficients is symmetrical to the number of bits of the longest linear feedback shift register. For example, the 19th-order primitive polynomial 1+x+x ² +x ⁵ +x ¹⁹ is the mirror image of 1+x ¹⁴ +x ¹⁷ +x ¹⁸ +x ¹⁹ , and 1+x+x ² +x ⁶ +x ¹⁹ is the mirror image of 1+x ¹³ +x ¹⁷ +x ¹⁸ +x ¹⁹ mirrored. The 25th-order primitive polynomial 1+x ³ +x ²⁵ is the mirror image of 1+x ²² +x ²⁵ , and the mirror image of 1+x ⁷ +x ²⁵ is the mirror image of 1+x ¹⁸ +x ²⁵ . The m-sequences generated by the two mirrored primitive polynomials have a strong correlation. The cross-correlation function of m-sequences generated by primitive polynomials without mirror image relationship is almost zero, which can be considered as uncorrelated. For example, primitive polynomials 1+x+x ² +x ⁵ +x ¹⁹ , 1+x+x ² +x ⁶ +x ¹⁹ , 1+x+x ⁴ +x ⁶ +x ¹⁹ , 1+x ³ +x ⁴ +x ⁶ +x ¹⁹ , 1+x+x ⁵ +x ⁶ +x ¹⁹ , 1+x+x ⁴ +x ⁷ +x ¹⁹ , 1+x ⁵ +x ⁶ +x ⁷ +x ¹⁹ , 1+x +x ⁶ +x ⁸ +x ¹⁹ , 1+x ³ +x ²⁵ , 1+x ⁷ +x ²⁵ are not correlated with each other.

The pseudo-randomness of m-sequence is very good, but it can only output one bit at a time. To generate a pseudo-random number with multiple data bits, the natural idea is to directly extract several bits from the longest linear feedback shift register to obtain a multi-bit random number. Fig. 5 is a schematic diagram of a circuit for obtaining a 4-bit pseudo-random number from an 8-bit longest linear feedback shift register. The primitive polynomial corresponding to the linear feedback logic circuit can be selected as 1+x ² +x ³ +x ⁴ +x ⁸ , that is, the feedback lines corresponding to the data bits a6, a5, a4, and a0 are in a connected state. But this method is not good, because the pseudo-random number output at this moment and the pseudo-random number output at the next moment, except for one data bit is newly generated, the other several data bits are the same, but the position is offset one. The pseudo-random number output at this moment is the same as the pseudo-random number output at the next moment, except that the two data bits are newly generated, and the other two data bits are the same, except that the position is shifted by two bits. And so on. That is to say, there is a strong correlation between the pseudo-random numbers generated by this method, so its quality is not good enough.

Contents of the invention

The purpose of the present invention is to provide a pseudo-random number generation method to solve the problems in the prior art.

In order to achieve the above object, the technical scheme adopted in the present invention is:

A kind of pseudo-random number generation method, it is characterized in that: based on the N _a bit pseudo-random number generator A of the longest linear feedback shift register of parallel structure, the evenly distributed pseudo-random number of m bit has been generated, and is denoted as A[k] , represented in binary as A _m-1 [k]A _m-2 [k]...A ₁ [k]A ₀ [k]; _Pseudo -random The number generator B generates a uniformly distributed pseudo-random number of m bits, denoted as B[k], expressed in binary as B _m-1 [k]B _m-2 [k]...B ₁ [k]B ₀ [k]; the pseudo-random number A[k] and the corresponding data bits in the pseudo-random number B[k] are XORed to generate a pseudo-random number D[k], expressed in binary as D _m-1 [k]D _m-2 [k]...D ₁ [k]D ₀ [k]; It is required that the pseudo-random number A[k] generated by pseudo-random number generator A and the pseudo-random number B[k] generated by pseudo-random number generator B[ k] is irrelevant, that is, the primitive polynomial of pseudo-random number generator A and the primitive polynomial of pseudo-random number generator B cannot be mirror primitive polynomials, because the relationship between pseudo-random number generator A and pseudo-random number generator B Irrelevant, each bit in the generated pseudo-random number D[k] is uniformly distributed, so D[k] is an m-bit uniformly distributed pseudo-random number.

The invention is a method for operating two or more pseudo-random number generators to generate high-speed pseudo-random numbers with a long sequence period; wherein each pseudo-random number is generated based on the longest linear feedback shift register circuit in a parallel structure; participation is required The pseudo-random numbers generated by the pseudo-random number generator of the operation are not correlated with each other. The invention can generate evenly distributed pseudo-random numbers with a plurality of data bits in real time, as well as other distributed pseudo-random numbers, and can also generate wide-band digital white noise signals, whose parameters such as mean value and variance can be adjusted.

Description of drawings

Figure 1 Block diagram of solid-state noise signal generator.

Figure 2 Gaussian distribution digital noise signal generator block diagram.

Figure 3 is a block diagram of a digital noise signal generator with binary uniform distribution.

Figure 4. Block diagram of longest linear feedback shift register.

Fig. 5 is a functional block diagram of extracting 4 digits from an 8-bit longest linear feedback shift register.

Figure 6 is a schematic block diagram of a pseudo-random number generating circuit with a parallel structure.

Figure 7 is a schematic block diagram of a long sequence period high-speed pseudo-random number generation circuit invented.

Fig. 8 is a schematic block diagram of a high-speed pseudo-random number generating circuit with three circuit units.

Fig. 9 is a schematic block diagram of a pseudo-random number generation circuit with different distributions.

Fig. 10 is a functional block diagram of a specific implementation of the pseudo-random number generating circuit.

Fig. 11 is a functional block diagram of another specific implementation of the pseudo-random number generating circuit.

Figure 12 Gaussian distribution pseudo-random number probability density curve.

Figure 13 Gaussian distribution pseudo-random number cumulative distribution function curve.

Fig. 14 is the numerical curve in the lookup table when generating Gaussian distributed pseudo-random numbers.

Figure 158 Schematic diagram of a pseudo-random number generator.

Figure 16 mode selection control circuit.

Detailed ways

In the method of extracting several digits from the longest linear feedback shift register, some data bits between adjacent pseudo-random numbers are the same, but the positions are shifted, and the quality of the generated pseudo-random numbers is not good, so it needs to be done out improvement.

For an n-bit longest linear feedback shift register, the value of the internal register represents the state of the circuit {Q[k]}, and the value of the register at the current moment is recorded as Q _n-1 [k], Q _n-2 [k] , Q _n-3 [k]...Q ₁ [k], Q ₀ [k], Q _n [k] is

Q _n [k]＝c ₁ Q _n-1 [k]⊕c ₂ Q _n-2 [k]⊕c ₃ Q _n-3 [k]⊕...⊕c _n-1 Q ₁ [k]⊕ c _n Q ₀ [k]

The state of the circuit at the next moment is recorded as {Q[k+1]}, and the values of the registers are Q _n-1 [k+1], Q _n-2 [k+1], Q _n-3 [k+1]. ..Q ₁ [k+1], Q ₀ [k+1], then

Qn _-1 [k ₊ 1]=Qn[k]

Qn _-2 [k+1]=Qn _-1 [k]

Qn _-3 [k+1]=Qn _-2 [k]

...

Q ₁ [k+1] = Q ₂ [k]

Q ₀ [k+1]=Q ₁ [k]

Q _n [k+1]＝c ₁ Q _n-1 [k+1]⊕c ₂ Q _n-2 [k+1]⊕c ₃ Q _n-3 [k+1]⊕...⊕c _{n -1} Q ₁ [k+1]⊕c _n Q ₀ [k+1]

The state of the circuit at the next moment is recorded as {Q[k+2]}, and the values of the registers are Q _n-1 [k+2], Q _n-2 [k+2], Q _n-3 [k+2] ...Q ₁ [k+2], Q ₀ [k+2], then

Qn _-1 [k+2]=Qn[k ₊ 1]

Qn _-2 [k+2]=Qn _-1 [k+1]

Qn _-3 [k+2]=Qn _-2 [k+1]

...

Q ₁ [k+2] = Q ₂ [k+1]

Q ₀ [k+2]=Q ₁ [k+1]

Q _n [k+2]＝c ₁ Q _n-1 [k+2]⊕c ₂ Q _n-2 [k+2]⊕c ₃ Q _n-3 [k+2]⊕...⊕c _{n -1} Q ₁ [k+2]⊕c _n Q ₀ [k+2]

And so on. If you plan to output m-bit binary data in parallel, in order to overcome the shortcomings of the aforementioned method to generate pseudo-random numbers, m clocks are needed to change the state of the circuit from {Q[k]} to {Q[k+m]}, register The values of Q _n-1 [k+m], Q _n-2 [k+m], Q _n-3 [k+m]...Q ₁ [k+m], Q ₀ [k+m] . The m-bit binary data generated in this way are Q _m-1 [k+m], Q _m-2 [k+m], ..., Q ₁ [k+m], Q ₀ [k+m ]. No data bit is the same before and after the m-bit pseudo-random number generated in this way, the correlation between data is well overcome, and the quality of the pseudo-random number is greatly improved. Since the probability of each binary number "0" and "1" symbols is the same, the generated m-bit pseudo-random numbers are evenly distributed. When the m-bit pseudo-random number is regarded as a complement code, the value range is [-2 ^m-1 , 2 ^m-1 -1]. When the m-bit pseudo-random number is regarded as an unsigned number, the value range is [0,2 ^m -1].

The disadvantage of the above method is that a pseudo-random number can only be obtained every m times of the clock, so the speed of the circuit to generate pseudo-random numbers is reduced by m times. If the state {Q[k]} of the above circuit is deduced recursively, {Q[k+1]}...{Q[k+m]} is obtained in turn, and the logic of the circuit state {Q[k+m]} It is deduced that it only depends on the state of {Q[k]}, then the designed longest linear feedback shift register can output an m-bit pseudo-random number every time a clock comes, and the speed of generating pseudo-random numbers has been greatly improved. It is greatly improved, and its internal state is equivalent to the original state of the longest linear feedback shift register changing m times. The block diagram of the longest linear feedback shift register with this parallel structure is shown in Figure 6.

The present invention proposes a method for generating pseudo-random numbers with a long sequence period by combining a longest linear feedback shift register with a parallel structure and more than one longest linear feedback shift register with a parallel structure. The principle block diagram is shown in FIG. 7 .

If the N _a -bit pseudo-random number generator A based on the longest linear feedback shift register in parallel structure generates a uniformly distributed pseudo-random number of m bits, which is recorded as A[k] and expressed in binary as A _m-1 [k ]A _m-2 [k]...A ₁ [k]A ₀ [k]. Based on the pseudo-random number generator B of N _b -bit longest linear feedback shift register with parallel structure, a uniformly distributed pseudo-random number of m bits is generated, denoted as B[k], expressed in binary as B _m-1 [k ]B _m-2 [k]...B ₁ [k]B ₀ [k]. The pseudo-random number A[k] is XORed with the corresponding data bits in the pseudo-random number B[k] to generate a pseudo-random number D[k], which is expressed in binary as D _m-1 [k]D _m-2 [k ]... D ₁ [k] D ₀ [k]. It is required that the pseudo-random number A[k] generated by pseudo-random number generator A is not related to the pseudo-random number B[k] generated by pseudo-random number generator B, that is, the original polynomial of pseudo-random number generator A and the pseudo-random number The primitive polynomial of generator B cannot be a mirror primitive polynomial. Since there is no correlation between pseudo-random number generator A and pseudo-random number generator B, each bit in the generated pseudo-random number D[k] is uniformly distributed, so D[k] is m-bit uniformly distributed pseudo-random number.

When m is an even number, the sequence period of the parallel structure pseudo-random number generator A is 2 ^Na -1, and the sequence period of the parallel structure pseudo-random number generator B is 2 ^Nb -1. The sequence period of the pseudo-random number D[k] is the least common multiple of the sequence periods of the pseudo-random number generators A and B. Therefore, the sequence period of the pseudo-random number D[k] has been greatly extended.

When the three-stage pseudo-random number generator circuit structure is adopted, the functional block diagram is shown in Figure 8. Based on the N _a -bit pseudo-random number generator A with the longest linear feedback shift register in parallel structure, a uniformly distributed pseudo-random number of m bits is generated, which is denoted as A[k]. Based on the N _b -bit pseudo-random number generator B of the longest linear feedback shift register in parallel structure, a uniformly distributed pseudo-random number of m bits is generated, which is denoted as B[k]. Based on the N _c -bit pseudo-random number generator C of the longest linear feedback shift register in parallel structure, a uniformly distributed pseudo-random number of m bits is generated, which is denoted as C[k]. A[k], B[k] and C[k] perform XOR operation to generate m-bit uniformly distributed pseudo-random number D[k]. It is required that pseudo-random number generator A, pseudo-random number generator B, and pseudo-random number generator C are not correlated with each other.

When m is an even number, the sequence period of the parallel structure pseudo-random number generator A is 2 ^Na -1, the sequence period of the parallel structure pseudo-random number generator B is 2 ^Nb -1, and the sequence period of the parallel structure pseudo-random number generator C is The period is 2 ^Nc -1. The sequence period of the pseudo-random number D[k] is the least common multiple of the sequence periods of the pseudo-random number generators A, B and C. Therefore, the sequence period of the pseudo-random number D[k] has been greatly expanded.

A pseudo-random number generator with more circuit elements can be designed. For example, a pseudo-random number generator with four longest linear feedback shift registers in parallel structure can be designed, and the outputs of these four pseudo-random number generators can be XORed to generate uniformly distributed pseudo-random numbers with multiple data bits. . The four pseudo-random number generators are required to be uncorrelated with each other. The sequence period for generating pseudo-random numbers is the least common multiple of the sequence periods of the four pseudo-random number generators.

After generating uniformly distributed pseudo-random numbers, it is easy to generate pseudo-random numbers and noise signals of various distributions. For example, uniform distribution, Gaussian distribution, and other pseudo-random numbers can be generated, and digital white noise signals with uniform distribution, Gaussian distribution, and other distributions can also be generated. The mean, variance, and spectral density can be adjusted. The block diagram of the circuit for converting uniformly distributed pseudo-random numbers into other distributed pseudo-random numbers is shown in FIG. 9 . When generating pseudo-random numbers with other distributions, the uniformly distributed pseudo-random numbers are converted into pseudo-random numbers of the required distribution through a lookup table. Changing the values in the lookup table can change the distribution, mean and variance of the pseudo-random numbers. It is also possible to generate pseudo-random digital white noise signals with desired distribution, mean, variance, and spectral density. When generating a pseudo-random digital white noise signal, the bandwidth of the output digital noise signal is at most about half of the circuit clock frequency.

Specific examples:

Taking the 8-bit pseudo-random number generated by the 32-bit longest linear feedback shift register as an example, the specific implementation of the high-speed pseudo-random number generation method used in the present invention is described. Take the primitive polynomial 1+x ² +x ⁶ +x ⁷ +x ³² , the circuit state of k at the current moment is {Q[k]}, and its register values are Q ₃₁ [k], Q ₃₀ [k], .. ., Q ₁ [k], Q ₀ [k], Q ₃₂ [k] are

Q ₃₂ [k]＝Q ₃₀ [k]⊕Q ₂₆ [k]⊕Q ₂₅ [k]⊕Q ₀ [k]

Then the circuit state {Q[k+8]} at time k+8 in the recursive formula is

Q ₀ [k+8]=Q ₈ [k]

Q ₁ [k+8] = Q ₉ [k]

...

Q ₂₃ [k+8] = Q ₃₁ [k]

Q ₂₄ [k+8]＝Q ₃₂ [k]＝Q ₃₀ [k]⊕Q ₂₆ [k]⊕Q ₂₅ [k]⊕Q ₀ [k]

Q ₂₅ [k+8]＝Q ₃₂ [k+1]＝Q ₃₀ [k+1]⊕Q ₂₆ [k+1]⊕Q ₂₅ [k+1]⊕Q ₀ [k+1]

=Q ₃₁ [k]⊕Q ₂₇ [k]⊕Q ₂₆ [k]⊕Q ₁ [k]

Q ₂₆ [k+8]＝Q ₃₂ [k+2]＝Q ₃₀ [k+2]⊕Q ₂₆ [k+2]⊕Q ₂₅ [k+2]⊕Q ₀ [k+2]

=Q ₃₂ [k]⊕Q ₂₈ [k]⊕Q ₂₇ [k]⊕Q ₂ [k]

=Q ₃₀ [k]⊕Q ₂₈ [k]⊕Q ₂₇ [k]⊕Q ₂₆ [k]⊕Q ₂₅ [k]⊕Q ₂ [k]⊕Q ₀ [k]

Q ₂₇ [k+8]＝Q ₃₂ [k+3]＝Q ₃₀ [k+3]⊕Q ₂₆ [k+3]⊕Q ₂₅ [k+3]⊕Q ₀ [k+3]

＝Q ₃₂ [k+1]⊕Q ₂₉ [k]⊕Q ₂₈ [k]⊕Q ₃ [k]

=Q ₃₁ [k]⊕Q ₂₉ [k]⊕Q ₂₈ [k]⊕Q ₂₇ [k]⊕Q ₂₆ [k]⊕Q ₃ [k]⊕Q ₁ [k]

Q ₂₈ [k+8]＝Q ₃₂ [k+4]＝Q ₃₀ [k+4]⊕Q ₂₆ [k+4]⊕Q ₂₅ [k+4]⊕Q ₀ [k+4]

=Q ₃₂ [k+2]⊕Q ₃₀ [k]⊕Q ₂₉ [k]⊕Q ₄ [k]＝Q ₃₀ [k]⊕Q ₂₈ [k]⊕Q ₂₇ [k]

⊕Q ₂₆ [k]⊕Q ₂₅ [k]⊕Q ₂ [k]⊕Q ₀ [k]⊕Q ₃₀ [k]⊕Q ₂₉ [k]⊕Q ₄ [k]

=Q ₂₉ [k]⊕Q ₂₈ [k]⊕Q ₂₇ [k]⊕Q ₂₆ [k]⊕Q ₂₅ [k]⊕Q ₄ [k]⊕Q ₂ [k]⊕Q ₀ [k]

Q ₂₉ [k+8]＝Q ₃₂ [k+5]＝Q ₃₀ [k+5]⊕Q ₂₆ [k+5]⊕Q ₂₅ [k+5]⊕Q ₀ [k+5]

＝Q ₃₂ [k+3]⊕Q ₃₁ [k]⊕Q ₃₀ [k]⊕Q ₅ [k]

=Q ₃₀ [k]⊕Q ₂₉ [k]⊕Q ₂₈ [k]⊕Q ₂₇ [k]⊕Q ₂₆ [k]⊕Q ₅ [k]⊕Q ₃ [k]⊕Q ₁ [k]

Q ₃₀ [k+8]＝Q ₃₂ [k+6]＝Q ₃₀ [k+6]⊕Q ₂₆ [k+6]⊕Q ₂₅ [k+6]⊕Q ₀ [k+6]

=Q ₃₂ [k+4]⊕Q ₃₂ [k]⊕Q ₃₁ [k]⊕Q ₆ [k]＝Q ₂₉ [k]⊕Q ₂₈ [k]⊕Q ₂₇ [k]

⊕Q ₂₆ [k]⊕Q ₂₅ [k]⊕Q ₄ [k]⊕Q ₂ [k]⊕Q ₀ [k]⊕Q ₃₀ [k]⊕Q ₂₆ [k]

⊕Q ₂₅ [k]⊕Q ₀ [k]⊕Q ₃₁ [k]⊕Q ₆ [k]

=Q ₃₁ [k]⊕Q ₃₀ [k]⊕Q ₂₉ [k]⊕Q ₂₈ [k]⊕Q ₂₇ [k]⊕Q ₆ [k]⊕Q ₄ [k]⊕Q ₂ [k]

Q ₃₁ [k+8]＝Q ₃₂ [k+7]＝Q ₃₀ [k+7]⊕Q ₂₆ [k+7]⊕Q ₂₅ [k+7]⊕Q ₀ [k+7]

＝Q ₃₀ [k+7]⊕Q ₂₆ [k+7]⊕Q ₂₅ [k+7]⊕Q ₀ [k+7]＝Q ₃₂ [k+5]⊕Q ₃₂ [k+1]

⊕Q ₃₂ [k]⊕Q ₇ [k]＝Q ₃₀ [k]⊕Q ₂₉ [k]⊕Q ₂₈ [k]⊕Q ₂₇ [k]⊕Q ₂₆ [k]

⊕Q ₅ [k]⊕Q ₃ [k]⊕Q ₁ [k]⊕Q ₃₁ [k]⊕Q ₂₇ [k]⊕Q ₂₆ [k]⊕Q ₁ [k]

⊕Q ₃₀ [k]⊕Q ₂₆ [k]⊕Q ₂₅ [k]⊕Q ₀ [k]⊕Q ₇ [k]

=Q ₃₁ [k]⊕Q ₂₉ [k]⊕Q ₂₈ [k]⊕Q ₂₆ [k]⊕Q ₂₅ [k]⊕Q ₇ [k]⊕Q ₅ [k]⊕Q ₃ [k]

⊕Q ₀ [k]

Q ₃₂ [k+8]＝Q ₃₀ [k+8]⊕Q ₂₆ [k+8]⊕Q ₂₅ [k+8]⊕Q ₀ [k+8]

In the deduced above formulas, the state of the circuit at time k+8 only depends on the state of the circuit at time k. Each clock of the longest linear feedback shift register with parallel structure designed in this way is equivalent to the internal state of the original longest linear feedback shift register changing 8 times, and can output an 8-bit pseudo-random Number, improve the shortcoming of the slow speed of the serial output method. Since the 32-bit longest linear feedback shift register has 2 ³² -1 states, which cannot be divisible by 8, the period of the 8-bit pseudo-random number is 2 ³² -1.

The parallel structure feedback logic circuit of the longest linear feedback shift register of 31 bits can be deduced by the same method. Taking the generation of 8-bit pseudo-random numbers as an example, take the primitive polynomial 1+x ³ +x ³¹ , the circuit state of k at the current moment is {Q[k]}, and its register values are Q ₃₀ [k], Q ₂₉ [k ], ..., Q ₁ [k], Q ₀ [k], Q ₃₁ [k] are

Q ₃₁ [k]＝Q ₂₈ [k]⊕Q ₀ [k]

Then the circuit state {Q[k+8]} at time k+8 in the recursive formula is

Q ₀ [k+8]=Q ₈ [k]

Q ₁ [k+8] = Q ₉ [k]

...

Q ₂₂ [k+8] = Q ₃₀ [k]

Q ₂₃ [k+8]＝Q ₃₁ [k]＝Q ₂₈ [k]⊕Q ₀ [k]

Q ₂₄ [k+8]＝Q ₃₁ [k+1]＝Q ₂₈ [k+1]⊕Q ₀ [k+1]

=Q ₂₉ [k]⊕Q ₁ [k]

Q ₂₅ [k+8]＝Q ₃₁ [k+2]＝Q ₂₈ [k+2]⊕Q ₀ [k+2]

=Q ₃₀ [k]⊕Q ₂ [k]

Q ₂₆ [k+8]＝Q ₃₁ [k+3]＝Q ₂₈ [k+3]⊕Q ₀ [k+3]

＝Q ₂₈ [k]⊕Q ₃ [k]⊕Q ₀ [k]

Q ₂₇ [k+8]＝Q ₃₁ [k+4]＝Q ₂₈ [k+4]⊕Q ₀ [k+4]

=Q ₃₁ [k+1]⊕Q ₄ [k]＝Q ₂₈ [k+1]⊕Q ₀ [k+1]⊕Q ₄ [k]

＝Q ₂₉ [k]⊕Q ₄ [k]⊕Q ₁ [k]

Q ₂₈ [k+8]＝Q ₃₁ [k+5]＝Q ₂₈ [k+5]⊕Q ₀ [k+5]

=Q ₃₁ [k+2]⊕Q ₅ [k]＝Q ₂₈ [k+2]⊕Q ₀ [k+2]⊕Q ₅ [k]

=Q ₃₀ [k]⊕Q ₅ [k]⊕Q ₂ [k]

Q ₂₉ [k+8]＝Q ₃₁ [k+6]＝Q ₂₈ [k+6]⊕Q ₀ [k+6]

=Q ₃₁ [k+3]⊕Q ₆ [k]＝Q ₂₈ [k+3]⊕Q ₀ [k+3]⊕Q ₆ [k]

＝Q ₂₈ [k]⊕Q ₀ [k]⊕Q ₃ [k]⊕Q ₆ [k]

＝Q ₂₈ [k]⊕Q ₆ [k]⊕Q ₃ [k]⊕Q ₀ [k]

Q ₃₀ [k+8]＝Q ₃₁ [k+7]＝Q ₂₈ [k+7]⊕Q ₀ [k+7]

=Q ₃₁ [k+4]⊕Q ₇ [k]＝Q ₂₈ [k+4]⊕Q ₀ [k+4]⊕Q ₇ [k]

＝Q ₃₁ [k+1]⊕Q ₄ [k]⊕Q ₇ [k]＝Q ₂₈ [k+1]⊕Q ₀ [k+1]⊕Q ₄ [k]⊕Q ₇ [k]

＝Q ₂₉ [k]⊕Q ₇ [k]⊕Q ₄ [k]⊕Q ₁ [k]

Q ₃₁ [k+8]＝Q ₂₈ [k+8]⊕Q ₀ [k+8]＝Q ₃₀ [k]⊕Q ₈ [k]⊕Q ₅ [k]⊕Q ₂ [k]

In the deduced above formulas, the state of the circuit at time k+8 only depends on the state of the circuit at time k. Each clock of the longest linear feedback shift register with parallel structure designed in this way is equivalent to the internal state of the original longest linear feedback shift register changing 8 times, and can output an 8-bit pseudo-random Number, improve the shortcoming of the slow speed of the serial output method. Since the 31-bit longest linear feedback shift register has 2 ³¹ -1 states, which cannot be divisible by 8, the period of the 8-bit pseudo-random number is 2 ³¹ -1.

A specific implementation of the present invention will be described below by taking a pseudo-random number generator with two circuit units as an example. The block diagram of the circuit is shown in Figure 10. The pseudo-random number generator A is the longest linear feedback shift register with a 32-bit parallel structure, and outputs an 8-bit pseudo-random number A[k] every time a clock comes, and selects the primitive polynomial 1+x ² +x ⁶ +x ⁷ + x ³² , its parallel structure feedback logic has been deduced earlier. The pseudo-random number generator B is the longest linear feedback shift register with a 31-bit parallel structure, and outputs an 8-bit pseudo-random number B[k] every time a clock comes, and selects the primitive polynomial 1+x ³ +x ³¹ , and its parallel structure The feedback logic has been deduced earlier. The pseudo-random number A[k] is XORed with B[k] to generate the pseudo-random number D[k]. The sequence period of the pseudo-random number A[k] is 2 ³² -1. The sequence period of the pseudo-random number B[k] is 2 ³¹ -1, which is a Mersenne prime number. The sequence period of the pseudo-random number D[k] is the least common multiple of the sequence period of the pseudo-random number A[k] and the sequence period of the pseudo-random number B[k], which is (2 ³² -1)(2 ³¹ -1), It is about 2 ⁶³ , which is greatly increased than the sequence period of A[k]. The longer the sequence period of the pseudo-random number is, the closer the performance is to the ideal random number.

Another specific implementation of the present invention will be described below by taking a pseudo-random number generator with three circuit units as an example. The block diagram of the circuit is shown in Figure 11. The pseudo-random number generator A is the longest linear feedback shift register with a 32-bit parallel structure, and outputs an 8-bit pseudo-random number A[k] every time a clock comes, and selects the primitive polynomial 1+x ² +x ⁶ +x ⁷ + ^x32 . Pseudo-random number generator B is the longest linear feedback shift register with 31-bit parallel structure, and outputs an 8-bit pseudo-random number B[k] every clock, and its primitive polynomial is 1+x ³ +x ³¹ . Pseudo-random number generator C is the longest linear feedback shift register with 19-bit parallel structure, and outputs an 8-bit pseudo-random number C[k] every time a clock comes, and its primitive polynomial is 1+x+x ² +x ⁵ + x ¹⁹ , its parallel structure feedback logic can refer to the previous derivation method. Pseudo-random numbers A[k], B[k] and C[k] are XORed to generate 8-bit pseudo-random numbers D[k]. The sequence period of the pseudo-random number A[k] is 2 ³² -1. The sequence period of the pseudo-random number B[k] is 2 ³¹ -1, which is a Mersenne prime number. The sequence period of the pseudo-random number C[k] is 2 ¹⁹ -1, which is a Mersenne prime number. The sequence period of the pseudo-random number D[k] is the least common multiple of the sequence periods of the pseudo-random numbers A[k], B[k] and C[k], which is (2 ³² -1)(2 ³¹ -1)(2 ¹⁹ -1), about 2 ⁸² , which is greatly increased than the sequence period of A[k]. It should be noted that in this example, the selection of the order of pseudo-random number generator A, pseudo-random number generator B, and pseudo-random number generator C is arbitrary, as long as the three are not correlated with each other.

The invention can generate pseudo-random numbers with uniform distribution, pseudo-random numbers with Gaussian distribution, and pseudo-random numbers with other distributions, and the mean value and variance can be adjusted.

To generate a random number with probability density f(x), its cumulative distribution function is F(x), there is

$\mathrm{<span\; class="notranslate">\; the\; y</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{<span\; class="notranslate">\; \&Integral;</span>}_{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; \&infin;</span>}}^{\mathrm{<span\; class="notranslate">\; x</span>}}\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; u</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; d</span>}\mathrm{<span\; class="notranslate">\; u</span>}$

When y is a uniformly distributed pseudo-random number sequence between [0,1.0], x is a pseudo-random number sequence with probability density f(x).

In engineering practice, the range of pseudo-random numbers generated is not from negative infinity to positive infinity, but a pseudo-random number with a limit on the number of digits. Therefore, the random numbers of a certain distribution actually generated are an approximation of the ideal random numbers of this distribution. For example, to generate an 8-bit pseudo-random number, its value range is -128 to 127, and to generate a 16-bit pseudo-random number, its value range is -32768 to 32767. Obtaining the x value from the y value can be realized by a look-up table circuit. A lookup table is a circuit that obtains an output value by looking up an input address value, and is generally implemented with RAM.

When generating uniformly distributed pseudo-random numbers, it can be known from the above method that the numerical curve stored in the lookup table is a straight oblique line.

When the Gaussian distribution pseudo-random number is generated, its probability density curve is shown in Figure 12, its cumulative distribution function curve is shown in Figure 13, and the numerical curve stored in the lookup table is shown in Figure 14.

Using the above method, pseudo-random numbers of other distributions can be generated. To generate different pseudo-random numbers, you only need to calculate the numerical curve in the lookup table as required and load it.

The invention can generate pseudo-random numbers with a long sequence period, and can also generate wide-band digital white noise signals, whose parameters such as mean value and variance can be adjusted. When the pseudo-random number is generated, the external CPU reads the pseudo-random number through the read interface circuit, reads the current pseudo-random number every time, and generates the next pseudo-random number. When generating a digital white noise signal, a clock is needed to generate a high-speed digital noise signal under the excitation of the clock.

The following takes the generation of 8-bit pseudo-random numbers and digital noise signals as an example to illustrate its working principle. When the pseudo-random number generation circuit is shown in FIG. 15 , the pseudo-random number and digital noise signal generation control circuit is shown in FIG. 16 . In the circuit, MODE_SEL is the mode selection input signal. When it is 0, it selects to generate a noise signal, and when it is 1, it selects to generate a pseudo-random number. CLK is the input clock signal. /CS is the chip select input signal, when it is 0, it means that the circuit is operated. /RD is the read input signal sent by the CPU. When it is 0, it means that the read operation is performed. RNG[7..0] is a pseudo-random number input signal, which comes from a pseudo-random number generation circuit. RNGCLK is the clock output signal, which is connected to the above figure as the clock of the pseudo-random number generator circuit. Q[7..0] is the digital noise output signal. When the noise signal generation mode is selected, a digital noise signal is output at each rising edge of the clock, and the bandwidth of the output digital white noise signal is at most about half of the clock frequency. DB[7..0] is a pseudo-random number output signal, which is connected to the data bus of the CPU and is a three-state signal. When the pseudo-random number generation mode is selected, the CPU reads this circuit once, and the pseudo-random number generation circuit outputs a Pseudo-random number, while generating the next pseudo-random number.

Sampling the pseudo-random number or digital noise signal, the sampling sequence is set to { _xi }, and the mean value u of N samples is:

$\mathrm{<span\; class="notranslate">\; u</span>}<span\; class="notranslate">\; =</span>\frac{\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{\overset{\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{<span\; class="notranslate">\; \&Sigma;</span>}}{\mathrm{<span\; class="notranslate">\; x</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}}{\mathrm{<span\; class="notranslate">\; N</span>}}$

The variance σ ² is equivalent to finding the power of the AC part of the signal, the formula is:

${\mathrm{<span\; class="notranslate">\; \&sigma;</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\frac{\underset{\mathrm{<span\; class="notranslate">\; i</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{\overset{\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{<span\; class="notranslate">\; \&Sigma;</span>}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; x</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; u</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{\mathrm{<span\; class="notranslate">\; N</span>}}$

When the value of N is large, the mean u and variance ^σ2 of the sampling sequence can be used as an estimate of the true mean and true variance of the signal, and its error is very small.

Normalize the pseudo-random number sequence {x _i } with mean u and variance σ ² into a pseudo-random number sequence {y _i } with mean 0 and variance 1, the formula is:

${\mathrm{<span\; class="notranslate">\; the\; y</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; x</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; u</span>}}{\mathrm{<span\; class="notranslate">\; \&sigma;</span>}}$

Use the pseudo-random number sequence {x _i } with mean value 0 and variance 1 to construct a pseudo-random number sequence {y _i } with mean value u and variance σ ² , the formula is:

y _i =u+σ*x _i

Assuming that the bandwidth of the band-limited digital white noise signal is B, the mean is 0, and the variance is σ ² , then its amplitude spectral density is:

A(f)=σ/B

The power spectral density is:

P(f)=σ ² /B

With the above method, the mean value and variance of the output pseudo-random number, and the mean value, variance, amplitude spectral density or power spectral density of the digital white noise signal can be controlled.

Using a high-speed FPGA circuit to implement the method discussed in this paper, the clock frequency can reach 500MHz, can generate 500M pseudo-random numbers per second, and can output broadband digital noise signals with a bandwidth of 200MHz or more. Realized by ultra-high-speed digital circuits, it can output digital noise signals with higher bandwidth.

It should be understood that the examples and implementations described herein are only for illustration, and those skilled in the art can make various modifications or changes based on them, all of which belong to the protection scope of the present invention without departing from the spirit of the present invention.

Claims (1)

1. a pseudo random number production method, is characterized in that: based on the N of parallel organization longest linear feedback shift register _aposition pseudorandom number generator A, what generate m position is uniformly distributed pseudo random number, is designated as A [k], take binary representation as A _m-1[k] A _m-2[k] ... A ₁[k] A ₀[k]; Based on the N of parallel organization _bthe pseudorandom number generator B of position longest linear feedback shift register, what generate m position is uniformly distributed pseudo random number, is designated as B [k], take binary representation as B _m-1[k] B _m-2[k] ... B ₁[k] B ₀[k]; Pseudo random number A [k] carries out XOR with corresponding data position in pseudo random number B [k], and generating pseudo random number D [k], take binary representation as D _m-1[k] D _m-2[k] ... D ₁[k] D ₀[k]; The pseudo random number B [k] that the pseudo random number A [k] requiring pseudorandom number generator A to generate and pseudorandom number generator B generate is uncorrelated, namely the primitive polynomial of pseudorandom number generator A and the primitive polynomial of pseudorandom number generator B can not be mirror image primitive polynomials, due to uncorrelated between pseudorandom number generator A and pseudorandom number generator B, each in the pseudo random number D [k] generated is equally distributed, and therefore D [k] is that m position is uniformly distributed pseudo random number.