CN105036059B - Processing method of capacitive MEMS sensor and sensor structure - Google Patents

Abstract

The present invention discloses a processing method for a capacitive MEMS sensor and a capacitive MEMS sensor. The method can utilize SON (silicon-on-nothing) technology to process two layers of silicon film on a single side as two levels of a capacitor, and utilize the capacitance change caused by the deformation of the lower silicon film after being compressed to measure the pressure. This processing method can be satisfied by an IC production line without the need for additional equipment or non-CMOS production line processes such as anodic bonding, and is conducive to controlling the consistency of sensor performance on the entire wafer.

Description

A processing method and sensor structure of a capacitive MEMS sensor

technical field

The invention relates to the technical field of semiconductor equipment processing, in particular to a processing method and sensor structure of a capacitive MEMS sensor.

Background technique

The production of capacitive MEMS sensors in the prior art usually adopts anodic bonding process. For example, the US patent document US5200363 proposes an electronic component with at least one silicon chip. This patent is based on silicon-glass bonding technology, ie, anodic bonding. Silicon wafers and glass are bonded together by silicon-glass bonding technology. A cavity is etched on the glass, and the pressure is detected by detecting the piezoresistive change value caused by the stress after applying pressure deformation on the upper surface of the silicon membrane.

Although the process is relatively mature and simple, the large thermal expansion coefficient gap between silicon and glass will affect the performance of the device, resulting in a large temperature drift of the sensor. Moreover, the anodic bonding process is not a standard CMOS process. Glass generally cannot be taped on a CMOS production line because it contains conductive ions, so the process needs to be outsourced, making it difficult to monitor the quality, and investing in corresponding equipment will increase investment in fixed assets.

In other production methods, a piezoresistive detection structure is formed. For example, Chinese patent document CN102285633 A discloses a manufacturing method for a composite integrated sensor structure. In the etching method, a cavity is etched, and silicon epitaxy is regrown to fill the etching hole, and a silicon thin film structure is formed. Then a piezoresistive structure is built on the cantilever beam, and the pressure is detected by detecting the piezoresistive change value caused by the stress.

Compared with piezoresistive detection, the signal noise of capacitance detection is low and the signal-to-noise ratio is high. However, piezoresistive devices, due to their inherent thermal noise, are difficult to achieve high signal-to-noise ratio sensor devices. Secondly, the capacitance detection scheme is less affected by temperature, but because temperature has a greater influence on piezoresistance, the output results vary greatly with temperature, which increases the difficulty and cost of subsequent chip temperature compensation.

Contents of the invention

An object of the present invention is to provide a low-cost processing method for capacitive MEMS sensors.

Another object of the present invention is to provide a method for processing a capacitive MEMS sensor, which has high performance consistency of the sensors on the same wafer.

Another object of the present invention is to provide a capacitive MEMS sensor with a high signal-to-noise ratio of the capacitive structure, which reduces the influence of temperature on the device and improves device precision.

For reaching above-mentioned purpose, the present invention adopts following technical scheme:

On the one hand, provide a kind of processing method of capacitive MEMS sensor, it is characterized in that, comprising the following steps:

Step S1, providing a silicon wafer substrate, and performing pattern processing on the silicon wafer substrate;

Step S2, using dry etching to etch deep grooves or deep holes on the silicon wafer substrate according to the shape of the pattern;

Step S3, performing annealing treatment on the silicon wafer substrate in a high-temperature oxygen-free environment, so that the silicon atoms on the surface of the silicon wafer substrate are migrated to form the first suspended silicon film, the second suspended silicon film and the first suspended silicon film. a first cavity between the silicon film and the second suspended silicon film, and a second cavity located between the second suspended silicon film and the silicon wafer substrate;

Step S4, photoetching a pattern on the surface of the silicon wafer substrate, and etching through the first suspended silicon film by dry etching according to the shape of the photolithographic pattern, so that the original first suspended silicon film forms a suspended film structure, and ensuring that the suspended film structure is connected to the silicon wafer substrate through a connection structure;

Step S5, using a semiconductor processing method to fabricate an electrical isolation structure, so that the connection between the suspended film and the silicon wafer substrate is completely electrically isolated:

Specifically, thermal oxidation treatment is performed on the silicon wafer substrate, so that the surface of the suspended film structure exposed to the external environment forms an electrically insulating electrical isolation structure, and the connection between the suspended film and the silicon wafer substrate is completely covered. oxidation;

Step S6, depositing a sealing semiconductor material, and covering the entire surface of the silicon wafer substrate to form a sealing layer, so that the sealing layer material seals the previously etched structure;

Specifically, the first silicon epitaxial growth process is performed, and a sealing layer is grown on the surface of the silicon wafer substrate, so that the sealing layer material covers the entire upper surface of the wafer and seals the previously etched structure;

Step S7, photoetching a pattern on the sealing layer, removing the sealing semiconductor material and the electrical isolation structure in the pattern, so that the uppermost silicon film and part of the silicon wafer substrate are exposed;

Specifically, a pattern is photolithographically etched on the sealing layer, and part of the epitaxial growth silicon and the electrical isolation structure are removed through a dry etching process to ensure that the uppermost silicon film and part of the silicon wafer substrate are exposed;

Step S8, depositing a conductive semiconductor material, forming a conductive material layer on the surface of the silicon wafer substrate, and realizing the electrical contact between the uppermost silicon film, the substrate and the conductive material layer through the previously etched opening;

Specifically, the second silicon epitaxial growth process is performed, and a conductive material layer is grown on the sealing layer, the first suspended silicon film and part of the silicon wafer substrate grown in the first silicon epitaxial growth process, so as to realize the uppermost silicon film, electrical contact between the substrate and the layer of conductive material;

Step S9, photolithographically patterning, removing the sealing layer and the conductive material layer, so as to insulate the first suspended silicon film and the silicon wafer from the rest of the sealing layer and the conductive material layer;

Step S10, depositing a semiconductor insulating layer outside the conductive material layer;

Step S11, etching and exposing the conductive material layer after patterning;

Step S12, depositing metal electrodes and patterning them;

Step S13 , patterning again, carving through the first suspended silicon film to form an air inlet structure.

As a preferred technical solution of the processing method of the capacitive MEMS sensor, the silicon wafer substrate in step S1 adopts a silicon wafer with a <100> crystal orientation, a silicon wafer with a <110> crystal orientation, or a < 111> Crystalline silicon wafer.

It should be pointed out that there are not too many requirements on the crystal orientation of the silicon wafer in this technical solution, and any silicon wafer with a crystal orientation structure can be used as the substrate silicon material used in this solution.

As a preferred technical solution of the processing method of the capacitive MEMS sensor, the shape of the pattern in step S2 may be one of rectangle, square, hexagon or circle or any combination thereof.

As a preferred technical solution for the processing method of the capacitive MEMS sensor, the high-temperature oxygen-free environment in step S3 is: the temperature is 1000°C to 1300°C, in a vacuum environment or an argon environment or a hydrogen environment, and the annealing time is long It is 5min～60min.

As a preferred technical solution of the processing method of the capacitive MEMS sensor, the connection structure in step S4 is an elongated connecting piece with a cross-sectional width less than or equal to 4 microns.

As a preferred technical solution of the processing method of the capacitive MEMS sensor, the process of depositing the sealing semiconductor material in step S6 is chemical vapor deposition.

As a preferred technical scheme of the processing method of the capacitive MEMS sensor, the dry etching described in step S14 is a deep reactive ion etching technique (DRIE), and the air inlet structure is a deep groove or a deep hole .

In another aspect, a capacitive MEMS sensor is provided, which is characterized in that it is processed by the above-mentioned processing method for a capacitive MEMS sensor.

The beneficial effects of the present invention are: the whole process is based on CMOS process lines and silicon wafers, avoiding non-CMOS processes such as anodic bonding and additional investment in fixed assets, ensuring the consistency of processing and manufacturing, the number of layers of silicon films, the thickness of silicon films and each The depth of the layer cavity can be controlled and adjusted within a certain range, and the sensor range can be adjusted by adjusting the thickness of the silicon film.

Description of drawings

The present invention will be described in further detail below according to the drawings and embodiments.

Fig. 1 is a flow chart of the processing method for the capacitive MEMS sensor described in the embodiment.

FIG. 2 is a top view of the silicon wafer after the pattern processing described in the embodiment.

FIG. 3 is a schematic cross-sectional view of a silicon wafer after processing the pattern described in the embodiment.

FIG. 4 is a schematic diagram of the structure of the silicon wafer after annealing.

FIG. 5 is a schematic diagram of the structure of the suspended thin film formed on the surface of the silicon wafer after etching.

Fig. 6 is a top view of Fig. 5 .

FIG. 7 is a cross-sectional view of a silicon wafer after fabricating an electrical isolation structure by using a semiconductor processing method.

FIG. 8 is a cross-sectional view of a silicon wafer after depositing a sealing layer.

FIG. 9 is a cross-sectional view after removing part of the sealing layer and the electrical isolation structure by etching.

FIG. 10 is a cross-sectional view of a silicon wafer after depositing a conductive material layer.

FIG. 11 is a cross-sectional view of the silicon wafer after etching the sealing layer and the conductive material layer.

FIG. 12 is a cross-sectional view after depositing and patterning a semiconductor insulating layer.

Fig. 13 is a schematic diagram of the structure after depositing metal electrodes and patterning.

FIG. 14 is a cross-sectional view of the silicon wafer after the gas inlet is processed.

In the picture:

100. Silicon wafer substrate; 101. Deep hole; 102. First suspended silicon film; 103. Second suspended silicon film; 104. First cavity; 105. Second cavity; 106. Electrical isolation structure; 107 , sealing layer; 108, conductive material layer; 109, semiconductor insulating layer; 110, electrode; 111, air inlet.

detailed description

The technical solutions of the present invention will be further described below in conjunction with the accompanying drawings and through specific implementation methods.

As shown in Figures 1 to 14, in this embodiment, a method for processing a capacitive MEMS sensor according to the present invention includes the following steps:

Step S1, providing a silicon wafer substrate 100, and performing pattern processing on the silicon wafer substrate 100;

Step S2, etching deep holes 101 on the silicon wafer substrate 100 according to the pattern;

Step S3, performing annealing treatment on the silicon wafer substrate 100 in a high-temperature oxygen-free environment, so that the silicon atoms on the substrate surface of the silicon wafer 1 are migrated to form a first suspended silicon film 102, a second suspended silicon film 103 and A first cavity 104 located between the first suspended silicon film 102 and the second suspended silicon film 103, a second cavity 105 located between the second suspended silicon film 103 and the silicon wafer substrate 100;

Step S4, photoetching a pattern on the surface of the silicon wafer substrate 100, and etching through the first suspended silicon film 102 according to the shape of the photolithographic pattern, so that the original first suspended silicon film 102 forms a suspended thin film structure, and ensuring that the suspended film structure is connected to the silicon wafer substrate 100 through a connection structure;

Step S5, using a semiconductor processing method to fabricate an electrical isolation structure, so that the connection between the suspended film and the silicon wafer substrate 100 is completely electrically isolated:

Specifically, the silicon wafer substrate 100 is thermally oxidized, so that the surface of the suspended film structure exposed to the external environment forms an electrically insulating electrical isolation structure 106, and the suspended film is connected to the silicon wafer substrate 100 The place is completely oxidized to form electrical insulation;

Step S6, depositing a sealing conductive semiconductor material, and covering the entire surface of the silicon wafer substrate 100 to form a sealing layer 107, so that the sealing layer 107 seals the previously etched structure;

Specifically, the first silicon epitaxial growth process is performed, and a sealing layer 107 is grown on the surface of the silicon wafer substrate 100, so that the sealing layer 107 covers the entire upper surface of the wafer and seals the previously etched structure;

Step S7, photoetching a pattern on the sealing layer 107, removing the sealing layer 107 and the electrical isolation structure 106 in the pattern, so that the uppermost silicon film and part of the silicon wafer substrate 100 are exposed;

Specifically, a pattern is photolithographically etched on the sealing layer 107, and part of the sealing layer 107 and the electrical isolation structure are removed through a dry etching process to ensure that the uppermost silicon film and part of the silicon wafer substrate 100 are exposed;

Step S8, depositing a conductive semiconductor material, forming a conductive material layer 108 on the surface of the silicon wafer substrate 100, and realizing the electrical contact between the uppermost silicon film, the substrate and the conductive material layer 108 through the previously etched opening ;

Specifically, the second silicon epitaxial growth process is performed, and the conductive material layer 108 is grown on the sealing layer 107, the first suspended silicon film 102 and part of the silicon wafer substrate 100 grown in the first silicon epitaxial growth process, to achieve the best The electrical contact between the upper silicon film, the substrate and the conductive material layer 108;

Step S9, photolithographic patterning, etching off the sealing layer 107 and the conductive material layer 108, so that the first suspended silicon film 102, the silicon wafer substrate 100 and the rest of the sealing layer 107 and the conductive material layer 108 are insulated;

Step S10, depositing a semiconductor insulating layer 109 outside the conductive material layer 108;

Step S11, etching and exposing the conductive material layer 108 after patterning;

Step S12, depositing metal electrodes and patterning them;

Step S13 , patterning again, cutting through the first suspended silicon film 102 to form the air inlet 112 structure.

Further, the silicon wafer substrate 100 in step S1 is a silicon wafer with a <100> orientation, a silicon wafer with a <110> orientation, or a silicon wafer with a <111> orientation.

The etching on the silicon wafer substrate 100 according to the pattern shape described in step S2 may also be etching deep grooves or other structures.

It should be pointed out that there are not too many requirements on the crystal orientation of the silicon wafer in this technical solution, and any silicon wafer with a crystal orientation structure can be used as the silicon wafer substrate material used in this solution.

Further, the shape of the pattern in step S2 is circular.

In other embodiments, the shape of the pattern may also be one of rectangle, square, hexagon or any combination thereof.

Further, the high-temperature oxygen-free environment in step S3 is: the temperature is 1050° C., and the annealing is carried out in an argon environment for 10 minutes.

Further, the connection structure described in step S4 is an elongated connecting piece with a cross-sectional width of 2 microns.

Further, the silicon epitaxial growth process in step S6 is chemical vapor deposition.

Further, the dry etching in step S14 is deep reactive ion etching (DRIE), and the structure of the air inlet 111 is a deep groove or a deep hole.

Specifically, using a <100> oriented silicon wafer 100 substrate, a series of small circular patterns are photoetched first. The diameter is d and the spacing is s.

A deep hole 101' of depth h' is etched using a deep reactive ion etching technique.

Annealed at 1050°C for 10 minutes in an argon environment, due to the physical phenomenon of surface silicon atom migration at high temperature, two layers of silicon films, the first suspended silicon film 102 and the second suspended silicon film 103, and the first cavity 104 and the second cavity were formed. Cavity 105 has two layers of cavities. At this time, the thickness h of silicon on the dry-etched substrate, the pattern spacing s and the diameter d determine the number of silicon films to be formed later, the thickness of the silicon films, and the depth of each cavity.

In this embodiment, the thickness h of the etched substrate silicon is 8 μm, the pattern spacing s is 0.5 μm, and the diameter d is 0.9 μm. The number of silicon film layers is two, the thickness of the silicon film is 1 μm, and the depth of each cavity is 1 μm. .

The surface of the wafer is photolithographically patterned, and the first suspended silicon film 102 is etched into a desired pattern by dry etching. The first suspended silicon film 102 is etched to form a suspended film structure. The main connection structure between the suspended film structure and the silicon wafer substrate adopts a slender strip type with a cross-sectional width of 2 microns to ensure complete oxidation of this part in the next process to form an electrical isolation material.

After the etching is completed, the mask photoresist is removed, and the entire wafer is subjected to thermal oxidation treatment. Since the upper surfaces of the entire first suspended silicon film 102 and the second suspended silicon film 103 are exposed to the environment, the first suspended silicon film 103 can be exposed to the environment. The surface of the silicon film 102 and the upper surface of the second suspended silicon film 103 form a layer of insulating layer as the electrical isolation structure 106. Since the connection structure is in the shape of a slender strip, it is easy to be completely oxidized to realize the first suspended silicon film 102 and the upper surface of the suspended silicon film 103. Electrical insulation of other parts of the silicon wafer substrate 100 .

On this basis, the first silicon epitaxial growth process is performed on the entire upper surface of the silicon wafer substrate 100 , and the sealing layer 107 is grown on the electrical isolation structure 106 . This step of epitaxial process can block the pinhole structure that may remain on the surface of the wafer after the previous step of thermal oxidation, and prevent liquid from flowing into the cavity in the subsequent cleaning photolithography step, affecting the structure and subsequent processes.

After the epitaxial growth is completed, the pattern is photolithography, and the sealing layer 107 and the electrical isolation structure 106 are removed by using a dry etching process.

In the second silicon epitaxial growth process, a conductive material layer 108 is grown on the sealing layer 107, the first suspended silicon film 102 and part of the silicon wafer substrate 100 to realize the electrical contact between the upper and lower layers of silicon

For photolithographic patterning, dry etching is used to etch the conductive material layer 108 . Specifically, the semiconductor insulating layer 109 is grown for subsequent electrode deposition. The semiconductor insulating layer 109 is grown by chemical vapor deposition, and after patterning, dry etching is performed to ensure that the corresponding part of the upper surface of the silicon wafer substrate 100 is exposed.

Metal electrodes are deposited, patterned, and then annealed to achieve ohmic contact between the electrode 110 and the first suspended silicon film 102, and ohmic contact between the electrode 110 and a part of the silicon wafer 100 substrate.

Finally, photolithographic patterning is performed again, and dry etching is used to etch through the first suspended silicon film 102 to form a deep hole as the structure of the air inlet 111 .

A capacitive MEMS sensor is processed by the above-mentioned processing method of the capacitive MEMS sensor.

In the description herein, it should be understood that the terms "upper", "lower", and other orientation or positional relationships are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of description and simplified operation, rather than indicating or It should not be construed as limiting the invention by implying that a referenced device or element must have a particular orientation, be constructed, and operate in a particular orientation. In addition, the terms "first" and "second" are only used for distinction in description and have no special meaning.

It should be stated that the above-mentioned specific implementation methods are only preferred embodiments of the present invention and the applied technical principles. Within the technical scope disclosed in the present invention, any changes or substitutions that are easily conceivable by those skilled in the art, All should be covered within the protection scope of the present invention.

Claims (8)

1. A processing method for capacitive MEMS sensor, is characterized in that, comprises the following steps: Step S1, providing a silicon wafer substrate, and performing pattern processing on the silicon wafer substrate; Step S2, using dry etching to etch deep grooves or deep holes on the silicon wafer substrate according to the shape of the pattern; Step S3, performing annealing treatment on the silicon wafer substrate in a high-temperature oxygen-free environment, so that the silicon atoms on the surface of the silicon wafer substrate are migrated to form the first suspended silicon film, the second suspended silicon film and the first suspended silicon film. a first cavity between the silicon film and the second suspended silicon film, and a second cavity located between the second suspended silicon film and the silicon wafer substrate; Step S4, photoetching a pattern on the surface of the silicon wafer substrate, and etching through the first suspended silicon film by dry etching according to the shape of the photolithographic pattern, so that the original first suspended silicon film forms a suspended film structure, and ensuring that the suspended film structure is connected to the silicon wafer substrate through a connection structure; Step S5, using a semiconductor processing method to fabricate an electrical isolation structure, so that the connection between the suspended film and the silicon wafer substrate is completely electrically isolated: Step S6, depositing a sealing semiconductor material, and covering the entire surface of the silicon wafer substrate to form a sealing layer, so that the sealing layer seals the previously etched structure; Step S7, photoetching a pattern on the sealing layer, removing the sealing semiconductor material and the electrical isolation structure in the pattern, so that the uppermost silicon film and part of the silicon wafer substrate are exposed; Step S8, depositing a conductive semiconductor material, forming a conductive material layer on the surface of the silicon wafer substrate, and realizing the electrical contact between the uppermost silicon film, the substrate and the conductive material layer through the previously etched opening; Step S9, photolithographically patterning, removing the sealing layer and the conductive material layer, so as to insulate the first suspended silicon film and the silicon wafer from the rest of the sealing layer and the conductive material layer; Step S10, depositing a semiconductor insulating layer outside the conductive material layer; Step S11, etching and exposing the conductive material layer after patterning; Step S12, depositing metal electrodes and patterning them; Step S13 , patterning again, carving through the first suspended silicon film to form an air inlet structure. 2. the processing method of capacitive MEMS sensor according to claim 1, is characterized in that, described silicon wafer substrate in step S1 adopts the silicon wafer of <100> crystal direction, the silicon crystal of <110> crystal direction Round or <111> oriented silicon wafers. 3. The processing method of a capacitive MEMS sensor according to claim 2, wherein the pattern shape described in step S2 can be one or any combination of rectangles, squares, hexagons or circles . 4. The processing method of a capacitive MEMS sensor according to claim 3, characterized in that the high-temperature oxygen-free environment in step S3 is: the temperature is 1000°C to 1300°C, in a vacuum environment or an argon environment or a hydrogen environment , the annealing time is 5min~60min. 5. The processing method of a capacitive MEMS sensor according to claim 4, characterized in that, the connection structure in step S4 is an elongated strip-shaped connector with a cross-sectional width less than or equal to 4 microns. 6 . The method for processing a capacitive MEMS sensor according to claim 5 , wherein the process of depositing and sealing semiconductor material in step S6 is chemical vapor deposition. 7 . 7. the processing method of capacitive MEMS sensor according to claim 6 is characterized in that, dry etching described in step S14 is deep reactive ion etching (DRIE), and described air inlet structure is deep groove or deep holes. 8. A capacitive MEMS sensor, characterized in that it is processed by the method for processing a capacitive MEMS sensor according to any one of claims 1 to 7.