CN104991113B - Applied to the zero cross detection circuit in high frequency switch power - Google Patents

Abstract

Include offset portion, detection part and output par, c the invention provides a kind of zero cross detection circuit being applied in high frequency switch power；Wherein described offset portion provides bias current for each branch road of zero cross detection circuit；The detection part detects rectifying tube drain voltage VX when switching tube is turned off, when VX rises to 0V from negative value, exports low level, rectifying tube is turned off, the generation of reverse current is prevented；Output par, c is used for the driving force for adjusting output waveform and increase detection circuit.Circuit form of the present invention it is simple, it is necessary to quiescent current it is low and low in energy consumption；The trip point of zero passage detection can be adjusted according to the size of bias current, wide using scope, be can be not only used for the zero passage detection in low-frequency switch power supply, be can be used for high frequency switch power.

Description

Zero-crossing detection circuit applied in high-frequency switching power supply

technical field

The invention relates to a power management module in the field of analog integrated circuit design, in particular to a zero-crossing detection circuit applied in a high-frequency switching power supply.

Background technique

Nowadays, portable electronic products tend to be more and more miniaturized, intelligent and highly integrated. In order to achieve high integration of switching power supply (DC-DC), the switching frequency must be increased to reduce the off-chip components such as inductors and capacitors to be integrated. Due to the size of the chip, the minimum switching frequency is 50MHz in the published literature on fully integrated DC-DC converters, and some literatures have increased the switching frequency to several hundred MHz. Increasing the switching frequency will inevitably bring about the complexity of the circuit design, and because the inductance value is very small, the current ripple on the inductance is very large, and it is easy to enter the DCM mode and generate reverse current. If the rectifier cannot be turned off in time, Even a delay of just a few nanoseconds can result in reverse currents approaching 100mA or worse. The traditional zero-crossing detection circuit uses a comparator structure. As shown in Figure 2, the voltage at point VX is compared with the 0V voltage, and the rectifier is turned off at the zero-crossing point. However, there is a propagation delay in the comparator, and the propagation delay The delay has a great influence on the high-frequency switching power supply, which will lead to a very large reverse current, as shown in Figure 3, and if the delay of the comparator is to be reduced, it will inevitably bring a lot of power consumption and occupy a large area.

Contents of the invention

In order to solve the above technical problems, the present invention provides a zero-crossing detection circuit applied to a high-frequency switching power supply, which is characterized in that it includes a bias part, a detection part and an output part;

Wherein the bias part provides bias current for each branch of the zero-crossing detection circuit;

The detection part detects the drain voltage VX of the rectifier tube when the switch tube is turned off, and outputs a low level when VX rises from a negative value to 0V, and turns off the rectifier tube to prevent the generation of reverse current;

The output section is used to adjust the output waveform and increase the driving capability of the detection circuit.

Preferably, the bias part includes a first PMOS transistor, a first NMOS transistor and a second NMOS transistor;

The source of the first PMOS transistor is connected to the power supply, the gate of the first NMOS transistor, the drain of the first NMOS transistor, and the gate of the second NMOS transistor are connected to the IB IAS port, the source of the first NMOS transistor, the second NMOS transistor The sources of the transistors are respectively grounded, and the drain of the first PMOS transistor, the gate of the first PMOS transistor, and the drain of the second NMOS transistor are connected.

Preferably, the detection part includes a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor;

The drain of the second PMOS transistor, the source of the second PMOS transistor, the source of the third PMOS transistor, the source of the fourth PMOS transistor, and the source of the fifth PMOS transistor are respectively connected to the power supply. The gates of the three PMOS transistors, the gates of the fourth PMOS transistors, and the gates of the fifth PMOS transistors are respectively connected to the gates of the first PMOS transistors, the drains of the fifth PMOS transistors are connected to the drains of the sixth NMOS transistors, and the drains of the third PMOS transistors The drain, the drain of the third NMOS transistor, the gate of the third NMOS transistor, and the gate of the fourth NMOS transistor are connected, and the drain of the fourth PMOS transistor, the drain of the fourth NMOS transistor, and the gate of the sixth NMOS transistor are connected,

The source of the third NMOS transistor and the source of the sixth NMOS transistor are respectively grounded, the source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the port EN, and the source of the fifth NMOS transistor is connected to the port EN. Port VX.

Preferably, the output part includes a first inverter and a second inverter connected in series, and the drain of the fifth PMOS transistor and the drain of the sixth NMOS transistor are respectively connected to the input of the first inverter .

Preferably, the substrates of the PMOS transistors and the NMOS transistors are both grounded.

Preferably, the channel lengths of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor are all 2.5 to 2.8 times the minimum channel length under the PMOS standard process, The channel lengths of the first NMOS transistor and the second NMOS transistor are both 5.5 to 5.6 times the minimum channel length under the NMOS standard process, and the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor The channel length of the NMOS transistor is the minimum channel length under the NMOS standard process.

The present invention has the following beneficial effects:

1. The circuit form is simple, the quiescent current required is very low, so the power consumption is very low, and the zero-crossing detection circuit in the form of a traditional comparator must increase the bias current and the size of the MOS tube to improve the comparator’s performance. Response speed, which increases both power consumption and cost;

2. The jump point of zero-crossing detection can be adjusted according to the size of the bias current, so that the application range of the present invention is very wide, and it can be used for zero-crossing detection in low-frequency switching power supply, and can also be used in high-frequency switching power supply; When used in a high-frequency switching power supply, the trip point can be advanced as needed to offset the influence of circuit propagation delay and prevent the generation of reverse current.

Of course, any product implementing the present invention does not necessarily need to achieve all the above-mentioned advantages at the same time.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings that are required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. Those of ordinary skill in the art can also obtain other drawings based on these drawings without any creative effort.

FIG. 1 is a schematic diagram of a zero-crossing detection circuit provided by an embodiment of the present invention;

Fig. 2 is a structural diagram of a traditional zero-crossing detection circuit;

Figure 3 shows the propagation delay and reverse current of a traditional zero-crossing detection circuit.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

As shown in Figure 1, a zero-crossing detection circuit applied to a high-frequency switching power supply is characterized in that it includes a bias part 1, a detection part 2 and an output part 3;

Wherein the bias part 1 provides a bias current for each branch of the zero-crossing detection circuit;

The detection part 2 detects the drain voltage VX of the rectifier tube when the switch tube is turned off, and outputs a low level when VX rises from a negative value to 0V, and turns off the rectifier tube to prevent the generation of reverse current;

The output part 3 is used to adjust the output waveform and increase the driving capability of the detection circuit.

In this embodiment, the bias part 1 includes a first PMOS transistor PM1, a first NMOS transistor NM1 and a second NMOS transistor NM2;

The source of the first PMOS transistor PM1 is connected to the power supply, the gate of the first NMOS transistor NM1, the drain of the first NMOS transistor NM1, and the gate of the second NMOS transistor NM2 are connected to the I B IAS port. The source of the first NMOS transistor NM1 and the second NMOS The source of the transistor NM2 is respectively grounded, the drain of the first PMOS transistor PM1, the gate of the first PMOS transistor PM1, and the drain of the second NMOS transistor NM2 are connected.

The detection part 2 includes a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, and a sixth NMOS transistor. NM6;

The drain of the second PMOS transistor PM2, the source of the second PMOS transistor PM2, the source of the third PMOS transistor PM3, the source of the fourth PMOS transistor PM4, and the source of the fifth PMOS transistor PM5 are respectively connected to the power supply, and the second PMOS transistor PM2 The gate, the gate of the third PMOS transistor PM3, the gate of the fourth PMOS transistor PM4, and the gate of the fifth PMOS transistor PM5 are respectively connected to the gate of the first PMOS transistor PM1, and the drain of the fifth PMOS transistor PM5 is connected to the gate of the sixth NMOS transistor NM6 The drain is connected, the drain of the third PMOS transistor PM3, the drain of the third NMOS transistor MN3, the gate of the third NMOS transistor NM3, the gate of the fourth NMOS transistor NM4 are connected, the drain of the fourth PMOS transistor PM4, the drain of the fourth NMOS transistor NM4 The drain is connected to the gate of the sixth NMOS transistor NM6,

The source of the third NMOS transistor NM3 and the source of the sixth NMOS transistor NM6 are respectively grounded, the source of the fourth NMOS transistor NM4 is connected to the drain of the fifth NMOS transistor NM5, the gate of the fifth NMOS transistor NM5 is connected to the port EN, and the fifth NMOS transistor NM5 The source of NM5 is connected to port VX.

The output part 3 includes a first inverter and a second inverter connected in series, and the drain of the fifth PMOS transistor PM5 and the drain of the sixth NMOS transistor NM6 are respectively connected to the input of the first inverter.

Both the substrates of the PMOS transistors and the NMOS transistors are grounded. The channel lengths of the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, the fourth PMOS transistor PM4, and the fifth PMOS transistor PM5 are all 2.5 to 2.8 times the minimum channel length under the PMOS standard process. The channel lengths of the first NMOS transistor NM1 and the second NMOS transistor NM2 are both 5.5 to 5.6 times the minimum channel length under the NMOS standard process, the third NMOS transistor NM3, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, and the sixth NMOS transistor NM5. The channel length of the NMOS transistor NM6 is the minimum channel length under the NMOS standard process.

In this embodiment, the port IBIAS provides the bias current for the zero-crossing detection circuit, the port EN is the circuit enable signal, VX is connected to the drain of the rectifier tube, and the voltage at this point is sampled in real time, and N_SHUT is the circuit output signal, which is used to control the current of the inductor. Turn off the rectifier when crossing zero;

The working process of the zero-crossing detection circuit applied in the high-frequency switching power supply provided by the embodiment of the present invention is as follows:

The port EN is connected with the driving signal of the switch tube. When the switch tube is turned on, the inductor current rises. At this time, EN is at a low level, and the zero-crossing detection circuit does not work. When the switch tube is turned off, the inductor current begins to drop. When EN is high level, the zero-crossing detection circuit starts to work to monitor the zero-crossing point of the inductor current; VX is directly connected to the drain terminal of the rectifier tube. The voltage value of the voltage gradually changes to the positive voltage, and when the inductor current is close to zero, the voltage of VX is also close to zero, that is to say: the zero crossing point of the inductor current is synchronized with the zero crossing point of the VX voltage, so the voltage value of VX can be used for Detect the zero-crossing point of the inductor current;

When EN is at a high level, the fifth NMOS transistor NM5 is turned on. If the inductor current is large, that is, the voltage value of VX is relatively negative. At this time, the drain of the fourth NMOS transistor NM4 and the gate voltage of the sixth NMOS transistor NM6 Pulled very low, at this time the sixth NMOS transistor NM6 is turned off, so the output N_SHUT is high, and the rectifier continues to work; if the inductor current drops to close to zero, that is, the voltage value of VX rises to close to 0V, at this time the first The drains of the four NMOS transistors NM4 will rise accordingly, and when the drains rise to the point where the sixth NMOS transistor NM6 is turned on, the output N_SHUT jumps to a low level, turning off the rectifier. The conversion of the drain voltage of the fourth NMOS transistor NM4 is related to the current flowing through, so the jump point can be changed by adjusting the current flowing through the fourth NMOS transistor NM4, and the jump point is adjusted in the present invention. -10mV or so, to offset the propagation delay of the circuit and prevent the generation of reverse current.

The circuit form of the present invention is simple, and the quiescent current required is very low, so the power consumption is very low, while the zero-crossing detection circuit in the form of a traditional comparator must increase the bias current and the size of the MOS tube to improve the comparator's performance. Response speed, which increases both power consumption and cost;

The jump point of zero-crossing detection can be adjusted according to the size of the bias current, so that the present invention has a wide range of applications, and can be used for zero-crossing detection in low-frequency switching power supplies and high-frequency switching power supplies; When switching power supplies at high frequencies, the jump point can be advanced as needed to offset the effects of circuit propagation delay and prevent reverse current generation.

The preferred embodiments of the invention disclosed above are only to help illustrate the invention. The preferred embodiments are not exhaustive in all detail, nor are the inventions limited to specific embodiments described. Obviously, many modifications and variations can be made based on the contents of this specification. This description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can well understand and utilize the present invention. The invention is to be limited only by the claims, along with their full scope and equivalents.

Claims (4)

1. A zero-crossing detection circuit applied in a high-frequency switching power supply, characterized in that it includes a bias part, a detection part and an output part; Wherein the bias part provides bias current for each branch of the zero-crossing detection circuit; The detection part detects the drain voltage VX of the rectifier tube when the switch tube is turned off, and outputs a low level when VX rises from a negative value to 0V, and turns off the rectifier tube to prevent the generation of reverse current; The output part is used to adjust the output waveform and increase the driving capability of the detection circuit; The bias part includes a first PMOS transistor, a first NMOS transistor and a second NMOS transistor; The source of the first PMOS transistor is connected to the power supply, the gate of the first NMOS transistor, the drain of the first NMOS transistor, and the gate of the second NMOS transistor are connected to the IBIAS port, and the source of the first NMOS transistor and the second NMOS transistor The sources are respectively grounded, and the drain of the first PMOS transistor, the gate of the first PMOS transistor, and the drain of the second NMOS transistor are connected; The detection part includes a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; The drain of the second PMOS transistor, the source of the second PMOS transistor, the source of the third PMOS transistor, the source of the fourth PMOS transistor, and the source of the fifth PMOS transistor are respectively connected to the power supply. The gates of the three PMOS transistors, the gates of the fourth PMOS transistors, and the gates of the fifth PMOS transistors are respectively connected to the gates of the first PMOS transistors, the drains of the fifth PMOS transistors are connected to the drains of the sixth NMOS transistors, and the drains of the third PMOS transistors The drain, the drain of the third NMOS transistor, the gate of the third NMOS transistor, and the gate of the fourth NMOS transistor are connected, and the drain of the fourth PMOS transistor, the drain of the fourth NMOS transistor, and the gate of the sixth NMOS transistor are connected. The source of the third NMOS transistor and the source of the sixth NMOS transistor are respectively grounded, the source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the port EN, and the source of the fifth NMOS transistor is connected to the port VX. 2. The zero-crossing detection circuit applied in a high-frequency switching power supply as claimed in claim 1, wherein the output part includes a first inverter and a second inverter connected in series, and the fifth PMOS The transistor drain and the sixth NMOS transistor drain are respectively connected to the input of the first inverter. 3. The zero-crossing detection circuit applied in a high-frequency switching power supply according to claim 2, wherein the substrates of each of the PMOS transistors and NMOS transistors are grounded. 4. The zero-crossing detection circuit applied in a high-frequency switching power supply as claimed in claim 3, wherein the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth The channel lengths of the PMOS transistors are both 2.5 to 2.8 times the minimum channel length under the PMOS standard process, and the channel lengths of the first NMOS transistor and the second NMOS transistor are both 5.5 to 2.8 times the minimum channel length under the NMOS standard process. 5.6 times, the channel lengths of the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are all the minimum channel lengths under the NMOS standard process.