CN104979404A - Lateral double-diffused metal oxide semiconductorfield-effect transistor with ladder field oxygen - Google Patents

Abstract

The present invention proposes a novel super-junction lateral double-diffused metal oxide semiconductor field effect transistor (SJ-LDMOS), including forming an SJ layer on the surface of the LDMOS drift region, and using two-step shallow trench isolation (STI) technology in the Super Junction A new type of semiconductor device with a stepped field oxide layer formed on the top, on the one hand, uses the electric field modulation effect to make the electric field distribution on the device surface more uniform, thereby increasing the breakdown voltage of the device; The thickness of the oxide layer is small, and there are more majority carrier accumulations on the surface of the drift region under the field plate in the on state, and the vertical current channel of the device under the thin stepped oxide layer is widened, which greatly reduces the conduction of the device resistance.

Description

A lateral double-diffused metal-oxide-semiconductor field-effect transistor with step field oxygen

technical field

The invention relates to the field of semiconductor devices, in particular to a lateral double-diffused metal oxide semiconductor field effect transistor.

Background technique

Applying super junction SJ (Super Junction) technology to LDMOS (Lateral Double-diffused MOSFET) to form SJ-LDMOS structure is a hotspot in the research of LDMOS devices. Because SJ-LDMOS has a very low on-resistance R _ON under a certain breakdown voltage BV (Breakdown Voltage), it breaks the limit relationship of traditional power MOS devices, and has been widely used in ultra-low power PIC (Power Integrated Circuit) is being designed. However, many problems have been encountered in the process of realizing SJ-LDMOS, including the substrate-assisted depletion effect SAD (Substrate Assisted Depletion), that is, the SJ-LDMOS realized on a P-type silicon substrate, because the N-pillar drift region is simultaneously phased The auxiliary depletion of the adjacent P-pillars and the P-type substrate causes the charge of the Super Junction to not be fully compensated, resulting in a significant decrease in BV.

The SJ-LDMOS structure with a buffer layer (Buffer) can effectively reduce the influence of the substrate-assisted depletion, and the structure is compatible with the traditional BCD (Bipolar-CMOS-DMOS) process. In the traditional BCD process, the LOCOS (Local Oxidation of Silicon) technology of silicon is used to manufacture the field oxygen in the Buffer SJ-LDMOS drift region and the isolation oxide layer between the devices. Due to the high temperature process of LOCOS, on the one hand, the interdiffusion between the N column and the P column of the super junction will be seriously increased; Similarly, the charge cannot be fully compensated, so that the electrical characteristics of the device are poor.

Compared with LOCOS technology, shallow trench isolation STI (Shallow Trench Isolation) technology has a lower operating temperature, which can well solve the above problems. However, in the process of manufacturing SJ-LDMOS by STI BCD process, in order to reduce the process cost, the thickness of the field oxide layer on the drift region is determined by the isolation depth between devices, and the performance of SJ-LDMOS is limited by the BCD process of the device. Although the thick field oxide layer between the devices meets the isolation conditions, the performance of the devices has not been well optimized, and the specific on-resistance also increases significantly while increasing the withstand voltage of the device.

Contents of the invention

The invention proposes a lateral double-diffused metal oxide semiconductor field effect transistor, aiming at effectively optimizing the contradiction between the breakdown voltage and specific on-resistance of SJ-LDMOS.

Technical scheme of the present invention is as follows:

Lateral double-diffused metal-oxide-semiconductor field-effect transistors, including:

Substrates of semiconductor materials;

an epitaxial layer grown on said substrate as a buffer layer;

An adjacent base region and a drift region are formed on the epitaxial layer, and the drift region is implanted with N columns and P columns arranged alternately to form a super junction drift region;

a field oxide layer and a drain region adjacent to the superjunction drift region, wherein the field oxide layer is spaced from the channel;

A channel is formed on the base region using double diffusion technology, and a channel substrate contact is formed on the base region and shorted to a side close to the channel to form a source region;

a gate insulating layer and a gate located above the channel;

a source electrode and a drain electrode formed on the source region and the drain region, respectively;

On the same structural basis as the prior art above, the structural changes of the present invention are mainly:

The field oxide layer is a ladder type, that is, the area close to the channel is a thin field oxide layer with a shallow depth, and the area close to and adjacent to the drain region is a thick field oxide layer with a deep depth; the gate insulating layer and gate The pole extends from above the channel to cover the portion of the thin field oxide layer.

Based on the above-mentioned basic scheme, the present invention further makes the following optimization limitations and improvements:

When the thickness of the thin field oxide layer is about 1/2 of the thickness of the thick field oxide layer, the characteristics of the device are optimal.

The thick field oxide layer of the stepped field oxide layer is designed with a specific thickness according to the specific withstand voltage requirements of the device. For example: when the device withstand voltage is 100-300V, the thickness of the thick field oxide layer is about 1 μm; when the device withstand voltage is 300-300V At 700V, the thickness of the thick field oxide layer is about 1.5μm.

When the step corner position of the step field oxide layer is near the middle position of the drift region of the device, the performance of the device is optimal.

Correspondingly, the special feature of the method for manufacturing the field effect transistor device of the present invention is that when forming the active region, firstly, a shallower thin field oxide layer is formed by using STI technology on the surface of the superjunction drift region close to the channel. Layer, to ensure that the gate insulating layer and the gate extend from above the channel to cover the part of the thin field oxide layer; then in the region near the drain terminal on the surface of the superjunction drift region and a plurality of the lateral double-diffused metal oxide semiconductor field effect transistors ( Note: Usually, such devices are made together by multiple devices) and the isolation between them is formed by STI technology to form a thick field oxide layer with a deep depth, that is, a stepped field oxide layer is formed on the surface of the super junction drift region.

The beneficial effects of the technical solution of the present invention are as follows:

The present invention forms a Super Junction on the surface of the drift region of the LDMOS, on the one hand, reduces the on-resistance of the drift region; on the other hand, eliminates the substrate auxiliary depletion effect, so that the device has a high breakdown voltage. Above the drift region of the device, a stepped field oxide layer is formed, which is an improvement and innovation to the SJ-LDMOS with a single-layer thick oxide layer on the traditional drift region.

A stepped field oxide layer is formed on the surface of the SJ-LDMOS drift region by two-step STI technology. On the one hand, the stepped field oxide layer modulates the surface electric field in the drift region of the device, making the distribution of the surface electric field in the drift region more uniform, thereby effectively increasing the breakdown voltage of the device. On the other hand, due to the thinning of the field oxide layer near the channel, there is a higher concentration of majority carrier accumulation on the surface of the drift region below the field plate in the on state, and in the device longitudinal direction under the thinner oxide layer The current channel is widened, thereby greatly reducing the on-resistance of the device, so that the overall performance of the device is optimized.

Description of drawings

Fig. 1 is the structural representation (front view) of the embodiment of the present invention;

2 is a schematic three-dimensional cross-sectional view of an embodiment of the present invention (for ease of labeling, a partial three-dimensional cross-section is made for the superjunction, the drift region insulating layer, and the stepped field oxide layer);

Explanation of reference numbers:

1-source; 2-gate, including the field plate extending to the part formed above the field oxide layer; 3-gate insulating layer; 4-step field oxide layer; 5-drain electrode; 6-drain region; 7-N column and The superjunction drift region formed by P columns alternately; 8-buffer layer; 9-substrate; 10-base region; 11-source region; 12-channel;

detailed description

As shown in Figure 1, the structure of the lateral double-diffused metal-oxide-semiconductor field-effect transistor with stepped field oxygen in the present invention includes:

a substrate 9 of semiconductor material;

The epitaxial layer on the substrate serves as the buffer layer 8 of the device;

The base region 10 and the drain region 6 respectively located at both ends of the buffer layer 8, and the drain region 5 is above the drain region;

source region 11 and channel 12 located on the surface of the base region;

The source electrode 1 is formed on the surface of the source region, and the gate insulating layer 3 is located below the gate 2 on the channel 12;

On the surface of the drift region between the channel and the drain region, a super junction drift region 7 with N columns and P columns arranged alternately is formed;

Above the super junction drift region 7 is a stepped field oxide layer 4;

The thickness of the thin field oxide layer is 41, and the thickness of the thick field oxide layer is 42.

Forming a Super Junction layer on the surface of the LDMOS drift region can effectively reduce the on-resistance of the drift region. And because the buffer layer under the Super Junction can effectively solve the substrate-assisted depletion effect, the device has a high breakdown voltage. In order to further optimize the characteristics of the device and solve the problem that the thickness of the field oxide layer is limited by the thickness of the isolation oxide layer between devices, a two-step STI technique is used to form a stepped field oxide layer on the superjunction drift region. According to the principle of electric field modulation, the stepped field oxide layer modulates the electric field on the surface of the drift region, making the electric field distribution more uniform and further improving the breakdown voltage of the device. And because the thickness of the thin field oxide layer near the channel is small, the concentration of the majority of current carriers accumulated in the region below the surface field plate in the drift region increases, and the conduction path of the current under the thin field oxide layer becomes wider, thereby greatly reducing the on-resistance of the device.

Taking N-channel LDMOS as an example, it can be prepared by the following steps:

1) Epitaxial N-type buffer layer on the substrate of semi-insulating material (including Si, SiC and GaAs, etc.);

2) forming a P-type base region on the left end of the buffer layer;

3) From the base region to the drain region, a number of high-concentration N columns and P columns arranged alternately are injected to form a super junction drift region;

4) Using two-step STI technology to form the active region and form a stepped field oxide layer on the super junction drift region; the step corner position of the field oxide layer is the midpoint position of the super junction drift region; where the thickness of the thin field oxide layer It is 1/2 of the thickness of the thick-field oxide layer; when the withstand voltage requirement is 100-300V, the thickness of the thick-field oxide layer is 1μm; when the withstand voltage requirement is 300-700V, the thickness of the thick-field oxide layer is 1.5μm;

5) Form a gate oxide layer on the channel and deposit polysilicon, etch the polysilicon and gate oxide layer to form a gate;

6) Use double-diffusion technology to implant in the base region to form a channel, and at the same time implant to form a drain region at the right end;

7) forming a channel substrate contact at the left end of the base region;

8) Deposit a passivation layer on the surface of the device, and etch the contact hole;

9) Deposit metal and etch to form drain and source.

After experiments, the performance of the device is greatly improved compared with the traditional device, and the breakdown voltage of the device is increased by about 25% when the drift region length of the two devices is the same; The on-resistance dropped by about 30%.

Of course, the LDMOS in the present invention can also be a P-type channel, and its structure is equivalent to that of an N-channel LDMOS, which should also belong to the protection scope of the claims of the present application, and will not be repeated here.

The above is only a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the technical principle of the present invention, some improvements and replacements can also be made, these improvements and replacements The scheme also falls within the protection scope of the present invention.

Claims (5)

1. A lateral double-diffused metal-oxide-semiconductor field-effect transistor, comprising: Substrates of semiconductor materials; an epitaxial layer grown on said substrate as a buffer layer; An adjacent base region and a drift region are formed on the epitaxial layer, and the drift region is implanted with N columns and P columns arranged alternately to form a super junction drift region; a field oxide layer and a drain region adjacent to the superjunction drift region, wherein the field oxide layer is spaced from the channel; A channel is formed on the base region using double diffusion technology, and a channel substrate contact is formed on the base region and shorted to a side close to the channel to form a source region; a gate insulating layer and a gate located above the channel; a source electrode and a drain electrode formed on the source region and the drain region, respectively; It is characterized by: The field oxide layer is a ladder type, that is, the area close to the channel is a thin field oxide layer with a shallow depth, and the area close to and adjacent to the drain region is a thick field oxide layer with a deep depth; the gate insulating layer and gate The pole extends from above the channel to cover the portion of the thin field oxide layer. 2. The lateral double diffused metal oxide semiconductor field effect transistor according to claim 1, wherein the thickness of the thin field oxide layer is 1/2 of the thickness of the thick field oxide layer. 3. The lateral double-diffused metal oxide semiconductor field effect transistor according to claim 1, characterized in that: when the withstand voltage requirement is 100-300V, the thickness of the thick field oxide layer is 1 μm; when the withstand voltage requirement is 300-700V , the thickness of the thick field oxide layer is 1.5 μm. 4 . The lateral double-diffused metal oxide semiconductor field effect transistor according to claim 1 , wherein the position of the step corner of the field oxide layer is the midpoint position of the superjunction drift region. 5. A method for making the lateral double-diffused metal-oxide-semiconductor field-effect transistor according to claim 1, comprising the following steps: 1) Epitaxial buffer layer on the substrate of semiconductor material; 2) forming a base region at the left end on the buffer layer; 3) A superjunction drift region is generated from the base region to the right end, that is, high-concentration N columns and P columns are alternately injected; 4) forming an active region and simultaneously forming a field oxide layer on the superjunction drift region; 5) Form a gate oxide layer on the channel and deposit polysilicon, etch the polysilicon and gate oxide layer to form a gate; 6) In the base region, a channel is formed by implanting double diffusion technology, and at the same time, a drain region is formed by implanting at the right end of the superjunction drift region; 7) forming a channel substrate contact at the left end of the base region; 8) Deposit a passivation layer on the entire surface, and etch the contact hole; 9) Deposit metal and etch to form drain and source; It is characterized by: When forming the active region, first use STI technology to form a shallow thin field oxide layer on the surface of the super junction drift region close to the channel to ensure that the gate insulating layer and the gate extend from above the channel to cover the thin field oxide layer part; then use STI technology to form a thick field oxide layer with a deeper depth in the region near the drain end of the superjunction drift region surface and the mutual isolation between a plurality of lateral double-diffused metal-oxide-semiconductor field effect transistors, that is, in A stepped field oxide layer is formed on the surface of the superjunction drift region.