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CN104979323A - 四方扁平无引脚封装及其制造方法 - Google Patents

四方扁平无引脚封装及其制造方法 Download PDF

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Publication number
CN104979323A
CN104979323A CN201410283470.3A CN201410283470A CN104979323A CN 104979323 A CN104979323 A CN 104979323A CN 201410283470 A CN201410283470 A CN 201410283470A CN 104979323 A CN104979323 A CN 104979323A
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CN
China
Prior art keywords
pads
chip
contact
connection pads
extension
Prior art date
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Pending
Application number
CN201410283470.3A
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English (en)
Inventor
石智仁
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Chipmos Technologies Inc
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Chipmos Technologies Inc
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Publication date
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Publication of CN104979323A publication Critical patent/CN104979323A/zh
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Abstract

本发明提供一种四方扁平无引脚封装及其制造方法，该四方扁平无引脚封装包括：一封装材料，以及配置于封装材料中的多个芯片座连接垫、多个接点连接垫及一芯片。每一芯片座连接垫以一第一延伸部与相邻的至少另一芯片座连接垫彼此连接。芯片座连接垫与接点连接垫以一阵列方式排列，芯片座连接垫配置于阵列中央，接点连接垫配置于芯片座连接垫周围，每一接点连接垫与相邻的至少另一接点连接垫或芯片座连接垫其中之一之间分别各具有对应的一第二延伸部，对应的二个第二延伸部之间以一沟槽彼此间隔。芯片固定于芯片座连接垫的一上表面，且分别与接点连接垫电性连接。

Description

四方扁平无引脚封装及其制造方法
技术领域
本发明是有关于一种四方扁平无引脚封装及其制造方法，特别是有关于一种可以共用导线架，并可以适用各种芯片尺寸及引脚配置且可以增加引脚数的四方扁平无引脚封装及其制造方法。
背景技术
四方扁平无引脚封装(Quad Flat No-Lead,QFN)，由于具有成本低，可以应用于印刷电路板的表面焊接技术(Surface Mount Technology,SMT)，而且厚度较薄，所以被广泛应用于许多半导体芯片的封装中。然而，由于四方扁平无引脚封装的连接垫(contacts)皆配置于封装外围的四周，而受限于表面焊接技术的能力，连接垫的间距有一定的限制，因此在特定封装面积下，连接垫的数量并无法有效增加。换言之，当引脚愈多时封装面积则须越大，所以限制了四方扁平无引脚封装在高引脚数封装的应用。此外，依照芯片面积的尺寸，需要不同的导线架设计，因此导线架无法共用或模块化，缺乏设计制造上的弹性。
然而随着轻薄短小的产品需求，能够于有限的空间中达到最大的效能，一直是半导体封装研发的目标，因此如何能在不影响封装面积/体积的条件下，提高封装的连接垫数量，已成为本领域的重要课题。另外，封装的模块化及共用化设计，亦是本技术领域的趋势。
发明内容
本发明的目的之一在于提供一种四方扁平无引脚封装及其制造方法，可以在不影响封装面积/体积的条件下，提高封装的连接垫数量。
本发明的另一目的在于提供一种四方扁平无引脚封装及其制造方法，适用于各种不同尺寸的芯片及各种引脚数，而本发明的导线架具有模块化、共用化的优点。
根据本发明的上述及其他目的提出一种四方扁平无引脚封装，包括：一封装材料、多个芯片座连接垫、多个接点连接垫，以及一芯片。封装材料，具有一封装下表面；芯片座连接垫，配置于封装材料中，其中每一芯片座连接垫以一第一延伸部与相邻的至少另一芯片座连接垫彼此连接，其中芯片座连接垫的下表面暴露于封装下表面。接点连接垫配置于封装材料中，芯片座连接垫与接点连接垫以一阵列方式排列，其中芯片座连接垫配置于阵列中央，接点连接垫配置于芯片座连接垫周围，其中每一接点连接垫与相邻的至少另一接点连接垫或芯片座连接垫其中之一之间分别各具有对应的一第二延伸部，对应的二个第二延伸部之间以一沟槽彼此间隔，且沟槽暴露出第二延伸部的一端，接点连接垫的下表面暴露于封装下表面。芯片配置于封装材料中，且固定于芯片座连接垫远离封装下表面的一上表面，芯片分别与接点连接垫电性连接。
在本发明的一个或多个实施例中，第一延伸部及第二延伸部的下表面暴露于封装下表面。第一延伸部的厚度小于芯片座连接垫的厚度，且第二延伸部的厚度小于接点连接垫的厚度。
在本发明的一个或多个实施例中，第一延伸部的宽度小于芯片座连接垫的宽度，且第二延伸部的宽度小于接点连接垫的宽度。
在本发明的一个或多个实施例中，其中沟槽是由切割、蚀刻、冲压或其组合的一种方法形成。一绝缘材料可以填充于沟槽中。
根据本发明的上述及其他目的提出一种导线架，适用于四方扁平无引脚封装，包括：多个连接垫，以一阵列方式排列，其中每一连接垫与相邻的至少另一连接垫之间以一延伸部彼此相连，其中二相邻的延伸部之间以连接垫其中之一或一空间彼此间隔，其中延伸部的厚度小于这些连接垫的厚度。
在本发明的一个或多个实施例中，延伸部的宽度小于连接垫的宽度。
在本发明的一个或多个实施例中，连接垫的下表面与延伸部的下表面为共平面。
根据本发明的上述及其他目的提出一种半导体封装方法，应用于四方扁平无引脚封装，包括：提供一导线架，具有多个连接垫，以一阵列方式排列，其中每一连接垫与相邻的至少另一连接垫之间以一延伸部彼此相连，其中二相邻的延伸部之间以连接垫其中之一或一空间彼此间隔，其中延伸部的厚度小于这些连接垫的厚度。将一芯片固定于连接垫中靠近中央的部分连接垫上，定义与芯片贴合的连接垫为多个芯片座连接垫，其余的连接垫为多个接点连接垫。将芯片与接点连接垫电性连接。以一封装材料覆盖芯片、芯片座连接垫与接点连接垫，且暴露出芯片座连接垫、接点连接垫以及延伸部的一表面。局部移除芯片座连接垫与接点连接垫之间以及接点连接垫彼此之间的延伸部，使得芯片座连接垫与接点连接垫电性隔离，且接点连接垫之间彼此电性隔离。
在本发明的一个或多个实施例中，局部移除延伸部的方法包括切割、蚀刻、冲压或其组合。
在本发明的一个或多个实施例中，于局部移除延伸部之后，每一接点连接垫与相邻的至少另一接点连接垫或芯片座连接垫其中之一之间分别各具有对应的一第二延伸部，对应的二个第二延伸部之间以一沟槽彼此间隔。于局部移除这些延伸部之后，更包括填充一绝缘材料于沟槽中。
在本发明的一个或多个实施例中，延伸部的宽度小于连接垫的宽度。
本发明的四方扁平无引脚封装及其制造方法，由于接点连接垫是以阵列方式排列，可以在不影响封装面积/体积的条件下，提高封装的连接垫数量。
本发明的四方扁平无引脚封装及其制造方法中，芯片座连接垫与接点连接垫是以阵列式排列，芯片座连接垫与接点连接垫的数量，可以依照芯片尺寸及接点数量而调整，可以适用于各种不同尺寸的芯片及各种引脚数，因而本发明的导线架具有模块化、共用化的优点。
附图说明
图1绘示依据本发明一实施例，一种四方扁平无引脚封装的剖面示意图。
图2绘示依据本发明一实施例，一种导线架的俯视图。
图3至图7绘示依据本发明一实施例，一种半导体封装方法各步骤的剖面示意图。
图8绘示依据本发明一实施例，一种四方扁平无引脚封装的仰视图。
关于本发明的优点，精神与特征，将以实施例并参照所附附图，进行详细说明与讨论。值得注意的是，为了让本发明能更容易理解，后附的附图仅为示意图，相关尺寸并非以实际比例绘示。
【附图标记说明】
100：四方扁平无引脚封装         204：延伸部
102：封装材料                   206：虚线区域
102A：封装下表面                208：空间
104：芯片座连接垫               300：导线架
104A：上表面                    302：连接垫
104B：下表面                    304：芯片座连接垫
106：接点连接垫                 304A：上表面
106A：下表面                    306：接点连接垫
108：芯片                       308：芯片
110：第一延伸部                 310：延伸部
112：第二延伸部                 304B、306A、310A：下表面
114：导线                       312：第二延伸部
116：沟槽                       314：导线
118：绝缘材料                   316：封装材料
200：导线架
202：连接垫
具体实施方式
为了让本发明的优点，精神与特征可以更容易且明确地了解，后续将以实施例并参照所附附图进行详述与讨论。值得注意的是，这些实施例仅为本发明代表性的实施例，其中所举例的特定方法，装置，条件，材质等并非用以限定本发明或对应的实施例。
请先参照图1，其绘示依据本发明一实施例，一种四方扁平无引脚封装100的剖面示意图。在某些实施例中，本发明的四方扁平无引脚封装100，包括：封装材料102、多个芯片座连接垫104、多个接点连接垫106以及一芯片108。封装材料102具有一封装下表面102A，其材质比如是环氧树脂。芯片座连接垫104配置于封装材料102中，每一芯片座连接垫104以第一延伸部110与相邻的至少另一芯片座连接垫104彼此连接，使得多个芯片座连接垫104可以彼此串联成一体。芯片座连接垫104的下表面104B则暴露于封装下表面102A。多个接点连接垫106配置于封装材料102中。值得一提的是，芯片座连接垫104与接点连接垫106原本同为一导线架的构件，并彼此连接，经过适当的分离步骤使得芯片座连接垫104与接点连接垫106分离，且各接点连接垫106之间彼此分离，后续实施例中将会详述相关结构及工艺。其中，芯片座连接垫104与接点连接垫106是以一阵列方式排列，芯片座连接垫104大致配置于阵列的中央，接点连接垫106则配置于芯片座连接垫104周围。每一接点连接垫106与相邻的另一接点连接垫106或芯片座连接垫104其中之一之间分别各具有对应的一第二延伸部112，对应的二个第二延伸部112之间以一沟槽116彼此间隔，且沟槽116暴露出第二延伸部112的一端。也就是说，芯片座连接垫104与接点连接垫106之间以及接点连接垫106彼此之间原本彼此连接，而经过分离步骤后，接点连接垫106与部分芯片座连接垫104形成残留的第二延伸部112。其中，沟槽116中可选择性的填入一绝缘材料118，绝缘材料118的材质比如是防焊漆、聚酰亚胺等。
接点连接垫106的下表面106A亦暴露于封装下表面102A，以作为四方扁平无引脚封装100对外的接点。芯片108配置于封装材料102中，且固定于芯片座连接垫104远离封装下表面102A的一上表面104A。芯片108比如借由导线114分别与接点连接垫106电性连接，导线114的材质比如是金、铜、银、钯或其合金，其是电性连接芯片108的焊点(未绘示)与接点连接垫106。
如图1所示，在本发明的实施例中，第一延伸部110及第二延伸部112的下表面亦暴露于封装下表面102A，也就是说，芯片座连接垫104与接点连接垫106原本彼此连接的部分是配置对应封装下表面102A。而设计上，如图所示，第一延伸部110的厚度小于芯片座连接垫104的厚度，且接点连接垫106原本彼此连接的部分(即第二延伸部112)的厚度小于接点连接垫106的厚度。借此，在分离步骤中，接点连接垫106彼此连接的部分可以轻易被移除而断开。值得一提的是，为了能够更稳固地固定芯片108，本发明的分离步骤中，芯片座连接垫104之间的第一延伸部110较佳是维持连接而不移除，然而依据实际需求也可以选择性部分移除，而使部分芯片座连接垫104彼此分离。
请参照图2，其绘示依据本发明一实施例，一种导线架的俯视图。如上所述，图1中芯片座连接垫104与接点连接垫106原本同为一导线架的构件，并彼此连接。在本发明的某些实施例中，应用于本发明四方扁平无引脚封装的导线架200包括：多个连接垫202以一阵列方式排列，其中每一连接垫202与相邻的另一连接垫202之间是以一延伸部204彼此相连，而二相邻的延伸部204彼此间隔，而非整片连接所有连接垫。由图2可知，相邻的延伸部204之间并不直接相连，而是以一连接垫202或一空间208彼此间隔。延伸部204连结连接垫202的方式并不限于图2的方式，比如图2中延伸部204主要是以横向连接连接垫202，然而亦可以纵向连接，或者纵向横向交错的阶梯状连接，或者环状连接等等。只要可以让连接垫202之间至少有一延伸部204连接，使得有足够的支撑即可。如图2所示，虚线区域206对应图1中的芯片座连接垫104位置，如上所述，可依据实际所需，定义用以固定芯片的连接垫202为芯片座连接垫，而作为四方扁平无引脚封装100对外的接点的连接垫202定义为接点连接垫。因此，如上所述，芯片座连接垫大致配置于阵列的中央，接点连接垫则配置于芯片座连接垫周围。而芯片座连接垫与接点连接垫的数量，可以依照芯片尺寸及接点数量而调整，因此本发明的导线架具有模块化、共用化的优点。
如图1所示，为了让后续的分离步骤，可以轻易地移除部分延伸部204，延伸部204的厚度小于连接垫202的厚度(如图1所示)，且延伸部204的宽度小于连接垫202的宽度。而连接垫202的下表面与延伸部204的下表面为共平面。
请参照图3至图7，其绘示依据本发明一实施例，一种半导体封装方法各步骤的剖面示意图。请先参照图3，在本发明的某些实施例中，本发明半导体封装方法可以应用于四方扁平无引脚封装，首先提供一导线架300，导线架300具有多个连接垫302，例如图2所示，以一阵列方式排列，其中每一连接垫302与相邻的至少另一连接垫302之间以一延伸部310彼此相连。如图2所示，二相邻的延伸部310之间是以一连接垫302或一空间彼此间隔，而延伸部310的厚度小于连接垫302的厚度。
请参照图4，将一芯片308固定于连接垫中靠近中央的部分连接垫302上，定义与芯片308贴合的连接垫302为多个芯片座连接垫304，其余的连接垫302为多个接点连接垫306。芯片308以其背面贴附于芯片座连接垫304的上表面304A，比如借由一粘晶胶(DAF)或贴带(tape)贴附于上表面304A。接着，将芯片308与芯片座连接垫304外围的接点连接垫306电性连接，比如借由导线314电性连接芯片308的焊点(未绘示)与接点连接垫306，导线314的材质比如是金、铜、银、钯或其合金。
接着参照图5，进行一封装步骤，以一封装材料316覆盖芯片308、芯片座连接垫304、导线314与接点连接垫306，且暴露出芯片座连接垫304、接点连接垫306以及延伸部310的下表面304B、306A、310A。封装材料316比如是环氧树脂。
请参照图6，接着进行分离步骤，局部移除芯片座连接垫304与接点连接垫306之间以及接点连接垫306彼此之间的延伸部310，使得芯片座连接垫304与接点连接垫306电性隔离，且使得接点连接垫306之间彼此电性隔离。而在本发明某些实施例中，局部移除延伸部310的方法包括切割、蚀刻、冲压或其组合。由于延伸部310的厚度与宽度都小于连接垫302，且延伸部310的下表面310A暴露于封装材料316，所以切割、蚀刻或冲压的深度可以很浅，即可轻易将延伸部310断开，使得连接垫302彼此分离，因此可避免移除深度过深而损伤导线314。为了让分离步骤不会损伤连接垫302，切割、蚀刻或冲压时可以与连接垫302保持适当距离，而如图6所示，于局部移除延伸部310之后，每一接点连接垫306与相邻的至少另一接点连接垫306或芯片座连接垫304其中之一之间分别各形成对应的一第二延伸部312，而对应的二个第二延伸部312之间以一沟槽116彼此间隔。值得一提的是，分离步骤目的在于使得芯片座连接垫304与接点连接垫306电性隔离，且使得接点连接垫306之间彼此电性隔离，所以连接垫302之间的延伸部310是否有残留都可以达成此目的，本实施例的方式并非用以限制本发明。此外，芯片座连接垫304之间的延伸部310并无需移除，亦即芯片座连接垫304之间可以保持串连，可以增加金属暴露的底面积，以利芯片308的散热。经过分离步骤后，移除的延伸部310及部分封装材料316会形成多个沟槽116，尤其利用切割或冲压进行分离步骤时，会同时移除延伸部310邻近的封装材料316。
请参照图7，上述分离步骤中形成沟槽116之后(如图6所示)，可以选择性填入一绝缘材料118于沟槽116(如图6所示)中。绝缘材料118的材质比如是防焊漆、聚酰亚胺等。
请参照图8，其绘示依据本发明的一实施例，一种四方扁平无引脚封装100的仰视图，其中，图7为图8中I-I线段的剖视图。
综上所述，本发明的四方扁平无引脚封装及其制造方法，由于接点连接垫是以阵列方式排列，相较于传统导线架型四方扁平无引脚封装中，连接垫仅配置于封装周缘，本发明可以在不影响封装面积/体积的条件下，提高封装的连接垫数量。且本发明的四方扁平无引脚封装及其制造方法中，芯片座连接垫与接点连接垫是以阵列式排列，芯片座连接垫与接点连接垫的数量，可以依照芯片尺寸及接点数量而调整，可以适用于各种不同尺寸的芯片及各种引脚数，因而本发明的导线架具有模块化、共用化的优点。
借由以上较佳具体实施例的详述，是希望能更加清楚描述本发明的特征与精神，而并非以上述所揭露的较佳具体实施例来对本发明的范畴加以限制。相反地，其目的是希望能涵盖各种改变及具相等性的安排于本发明所欲要求的保护范围的范畴内。虽然本发明已以实施方式揭露如上，然其并非用以限定本发明，任何熟习此技艺者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰，因此本发明的保护范围当视权利要求书所界定者为准。

Claims (15)

1.一种四方扁平无引脚封装，包括：
一封装材料，具有一封装下表面；
多个芯片座连接垫，配置于该封装材料中，其中每一该芯片座连接垫以一第一延伸部与相邻的至少另一芯片座连接垫彼此连接，其中该多个芯片座连接垫的下表面暴露于该封装下表面；
多个接点连接垫，配置于该封装材料中，其中该多个芯片座连接垫与该多个接点连接垫以一阵列方式排列，其中该多个芯片座连接垫配置于该阵列中央，该多个接点连接垫配置于该多个芯片座连接垫周围，其中每一该接点连接垫与相邻的至少另一接点连接垫或该多个芯片座连接垫其中之一之间分别各具有对应的一第二延伸部，对应的二个该第二延伸部之间以一沟槽彼此间隔，且该沟槽暴露出该第二延伸部的一端，其中该多个接点连接垫的下表面暴露于该封装下表面；以及
一芯片，配置于该封装材料中，且固定于该多个芯片座连接垫远离该封装下表面的一上表面，该芯片分别与该多个接点连接垫电性连接。
2.如权利要求1所述的四方扁平无引脚封装，其特征在于，多个该第一延伸部及多个该第二延伸部的下表面暴露于该封装下表面。
3.如权利要求1所述的四方扁平无引脚封装，其特征在于，该第一延伸部的厚度小于该多个芯片座连接垫的厚度，且该第二延伸部的厚度小于该多个接点连接垫的厚度。
4.如权利要求1所述的四方扁平无引脚封装，其特征在于，该第一延伸部的宽度小于该多个芯片座连接垫的宽度，且该第二延伸部的宽度小于该多个接点连接垫的宽度。
5.如权利要求2所述的四方扁平无引脚封装，其特征在于，该第一延伸部的厚度小于该多个芯片座连接垫的厚度，且该第二延伸部的厚度小于该多个接点连接垫的厚度。
6.如权利要求1所述的四方扁平无引脚封装，其特征在于，该沟槽是选自于由切割、蚀刻、冲压及其组合所组成的族群中的一种方法所形成。
7.如权利要求1所述的四方扁平无引脚封装，其特征在于，更包括一绝缘材料填充于多个该沟槽中。
8.一种导线架，适用于四方扁平无引脚封装，包括：
多个连接垫，以一阵列方式排列，其中每一该连接垫与相邻的至少另一连接垫之间以一延伸部彼此相连，其中二相邻的该延伸部之间以该多个连接垫其中之一或一空间彼此间隔，其中该延伸部的厚度小于该多个连接垫的厚度。
9.如权利要求8所述的导线架，其特征在于，该延伸部的宽度小于该多个连接垫的宽度。
10.如权利要求8所述的导线架，其特征在于，该多个连接垫的下表面与多个该延伸部的下表面为共平面。
11.一种半导体封装方法，应用于四方扁平无引脚封装，包括：
提供一导线架，具有多个连接垫，以一阵列方式排列，其中每一该连接垫与相邻的至少另一连接垫之间以一延伸部彼此相连，其中二相邻的该延伸部之间以该多个连接垫其中之一或一空间彼此间隔，其中该延伸部的厚度小于该多个连接垫的厚度；
将一芯片固定于该多个连接垫中靠近中央的部分该多个连接垫上，定义与该芯片贴合的该多个连接垫为多个芯片座连接垫，其余的该多个连接垫为多个接点连接垫；
将该芯片与该多个接点连接垫电性连接；
以一封装材料覆盖该芯片、该多个芯片座连接垫与该多个接点连接垫，且暴露出该多个芯片座连接垫、该多个接点连接垫以及多个该延伸部的一表面；
局部移除该多个芯片座连接垫与该多个接点连接垫之间以及该多个接点连接垫彼此之间的多个该延伸部，使得该多个芯片座连接垫与该多个接点连接垫电性隔离，且该多个接点连接垫之间彼此电性隔离。
12.如权利要求11所述的半导体封装方法，其特征在于，局部移除多个该延伸部的方法是选自于由切割、蚀刻、冲压及其组合所组成的族群中的一种方法。
13.如权利要求11所述的半导体封装方法，其特征在于，于局部移除多个该延伸部之后，每一该接点连接垫与相邻的至少另一接点连接垫或该多个芯片座连接垫其中之一之间分别各具有对应的一第二延伸部，对应的二个该第二延伸部之间以一沟槽彼此间隔。
14.如权利要求13所述的半导体封装方法，其特征在于，于局部移除多个该延伸部之后，更包括填充一绝缘材料于多个该沟槽中。
15.如权利要求11所述的半导体封装方法，其特征在于，该延伸部的宽度小于该多个连接垫的宽度。
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