CN104979293B - A kind of manufacture method of semiconductor devices - Google Patents
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- CN104979293B CN104979293B CN201410138464.9A CN201410138464A CN104979293B CN 104979293 B CN104979293 B CN 104979293B CN 201410138464 A CN201410138464 A CN 201410138464A CN 104979293 B CN104979293 B CN 104979293B
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Abstract
The present invention provides a kind of manufacture method of semiconductor devices, is related to technical field of semiconductors.The manufacture method of the semiconductor devices of the present invention, by being diffused landform engineering after diffusion impervious layer is set（DTE）Processing, can improve the performance of pull-down transistor, keep or even reduce the performance of transmission gate transistor, so as to improve the β ratios of SRAM, therefore can improve the performance of semiconductor devices.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device.
Background
In the field of semiconductor technology, stress engineering is one of the most important factors for improving device performance. As the process nodes of semiconductor technology evolve to below 90nm, the impact of stress on device performance becomes non-negligible. For high-density integrated circuits, the performance of CMOS devices is increasingly required to be improved.
The effect of stress on the performance of NMOS and PMOS devices is different in different directions. Fig. 1 illustrates the directions of stresses required to improve the performance of PMOS and NMOS by stress, wherein fig. 1A illustrates the stresses required to improve the performance of NMOS and fig. 1B illustrates the stresses required to improve the performance of PMOS. Therefore, in the X direction (the channel length direction), the tensile stress can improve the performance of the NMOS, and the compressive stress can improve the performance of the PMOS; in the Y direction (channel width direction), tensile stress can improve the performance of both NMOS and PMOS.
In the prior art, as shown in fig. 2, a Diffusion Topography Engineering (DTE) technique is used to improve the performance of a MOS device by applying a compressive stress to a channel by Shallow Trench Isolation (STI). Fig. 2A is a TEM image of the device along the Y direction, and fig. 2B is a stress simulation diagram of the DTE technique. However, in this solution, due to the tensile stress generated in the channel length direction by the DTE process, the compressive stress of the PMOS in the channel length direction is released, which may cause a certain degradation of the PMOS performance.
generally, an SRAM cell includes a pull-up transistor (PU), a pull-down transistor (PD), and a pass-gate transistor (PG), wherein the pull-up transistor is a PMOS, and the pull-down transistor and the pass-gate transistor are nmos, the SRAM is capable of storing information at high reading and writing speeds, and fig. 3 illustrates a typical structure of an SRAM cell in the prior art.
Therefore, in order to solve the above technical problems, the present invention proposes a new method for manufacturing a semiconductor device (SRAM or a semiconductor device including an SRAM).
Disclosure of Invention
in view of the disadvantages of the prior art, the present invention provides a method for manufacturing a semiconductor device, which can improve the β ratio of an SRAM.
The embodiment of the invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
step S101: providing a semiconductor substrate, and defining an active region on the semiconductor substrate;
step S102: forming a diffusion barrier layer on the semiconductor substrate;
step S103: etching the diffusion barrier layer, reserving the part of the diffusion barrier layer in the width direction of the channel of the transmission gate transistor, and removing the part of the diffusion barrier layer in other areas;
step S104: diffusion topography engineering is performed to improve the performance of pull-up and pull-down transistors and to maintain or even degrade the performance of pass-gate transistors.
Optionally, in the step S103, a portion of the diffusion barrier layer located in the channel length direction of the pull-up transistor is also retained.
Optionally, in step S102, the diffusion barrier layer is a compressive stress film; in step S104, the compressive stress of the portion of the diffusion barrier layer that remains is transferred to the channel width direction of the pass gate transistor while the diffusion topographic engineering process is performed.
Optionally, in step S102, the diffusion barrier layer is a compressive stress film; in step S104, the compressive stress of the portion of the diffusion barrier layer that remains is transferred to the channel width direction of the pass gate transistor and the channel length direction of the pull-up transistor while the diffusion topographic engineering process is performed.
Optionally, in the step S102, the material of the compressive stress film is compressive stress silicon nitride.
Optionally, in the step S104, the diffusion topography engineering process is performed under an annealing condition containing hydrogen.
Optionally, in the step S104, the duration of the diffusion terrain engineering process is 5 to 120 seconds.
Optionally, after the step S104, a step S105 is further included:
removing the remaining portion of the diffusion barrier layer.
Optionally, in the step S105, a method for removing the remaining portion of the diffusion barrier layer is wet stripping.
Optionally, after the step S105, a step S106 is further included: and forming a pull-up transistor, a pull-down transistor and a transmission gate transistor in the active area.
the method for manufacturing the semiconductor device can improve the performance of a pull-up transistor and a pull-down transistor, maintain or even reduce the performance of a transmission gate transistor by performing Diffusion Topographic Engineering (DTE) treatment after the diffusion barrier layer is arranged, thereby improving the β ratio of the SRAM, and improving the performance of the semiconductor device.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1 is a schematic diagram of the directions of stresses required to improve the performance of PMOS and NMOS by stress; wherein FIG. 1A illustrates the stress required to enhance the performance of NMOS and FIG. 1B illustrates the stress required to enhance the performance of PMOS;
FIG. 2 is a schematic diagram of a prior art DTE technique; wherein, fig. 2A is a TEM image of a device in the prior art along the Y direction, and fig. 2B is a stress simulation diagram of the DTE technique;
FIG. 3 is a schematic diagram of an SRAM cell in the prior art;
fig. 4A to 4E are schematic views of structures formed at steps related to the method of manufacturing a semiconductor device according to the embodiment of the present invention; wherein,
fig. 4A-1 is a top view of the device structure after forming an active region, and fig. 4A-2 is a cross-sectional view taken along line AA' of fig. 4A-1;
FIG. 4B-1 is a top view of the device structure after formation of a compressive stress film, and FIG. 4B-2 is a cross-sectional view taken along line AA' of FIG. 4B-1;
FIG. 4C-1 is a top view of the device structure after removal of a portion of the compressive stress film, FIG. 4C-2 is a cross-sectional view taken along line AA 'of FIG. 4C-1, and FIG. 4C-3 is a cross-sectional view taken along line BB' of FIG. 4C-1;
FIG. 4D-1 is a schematic top view of the device structure after DTE is performed, FIG. 4D-2 is a schematic cross-sectional view taken along line AA 'of FIG. 4D-1, and FIG. 4D-3 is a schematic cross-sectional view taken along line BB' of FIG. 4D-1;
FIG. 4E-1 is a top view of the device structure after removal of the remaining compressive stress film, FIG. 4E-2 is a cross-sectional view taken along line AA 'of FIG. 4E-1, and FIG. 4E-3 is a cross-sectional view taken along line BB' of FIG. 4E-1;
fig. 5 is a schematic flow chart of a method of manufacturing a semiconductor device of an embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, is capable of other embodiments in addition to those detailed.
Next, a method for manufacturing a semiconductor device of an embodiment of the present invention is described with reference to fig. 4A to 4E and fig. 5. Fig. 4A to 4E are schematic views of structures formed in the relevant steps of the method of manufacturing a semiconductor device of the embodiment; fig. 5 is a schematic flow chart of a method of manufacturing a semiconductor device of an embodiment of the present invention.
The method for manufacturing a semiconductor device of the present embodiment includes the steps of:
step A1: a semiconductor substrate 100 is provided, and an active region 101 is defined on the semiconductor substrate 100, as shown in fig. 4A. Wherein the active regions 101 include an active region of a pull-up transistor (PU), an active region of a pull-down transistor (PD), and an active region of a pass-gate transistor (PG), as shown in fig. 4A.
Illustratively, the semiconductor substrate is a single crystal silicon substrate or a silicon-on-insulator substrate (SOI substrate). The pull-up transistor (PU) is PMOS, and the pull-down transistor (PD) and the pass-gate transistor (PG) are NMOS.
Step A2: a compressive stress film 102 is formed on the semiconductor substrate as shown in fig. 4B.
The compressive stress film 102 may be made of any feasible material in the prior art, such as compressive stress silicon nitride. The method for forming the compressive stress film 102 may be deposition or other suitable methods.
Step A3: the compressive stress film 102 is etched, a portion 1021 (referred to as a first portion of the remaining compressive stress film) of the compressive stress film 102 in the channel length direction of the pull-up transistor (PMOS) and a portion 1022 (referred to as a second portion of the remaining compressive stress film) of the compressive stress film 102 in the channel width direction of the transfer gate transistor (NMOS) are left, and portions of the compressive stress film 102 in other regions are removed, as shown in fig. 4C.
Illustratively, the etching may be dry etching or wet etching. When the material of the compressive stress film 102 is compressive stress silicon nitride, dry etching is preferably used.
step A4, performing a Diffusion Topography Engineering (DTE) process to improve the performance of the pull-down transistors, maintain or even degrade the performance of the pass-gate transistors to improve the β ratio (β ratio) of the SRAM, and improve the performance of the pull-up transistors, the structure formed through this step is shown in FIG. 4D.
It should be noted that fig. 4D is only for illustration and does not show the structural change after the DTE process, but actually the microstructure of the device has changed to some extent, which results in the above-mentioned change of stress.
In this embodiment, in the process of performing Diffusion Topography Engineering (DTE) processing, silicon atom migration occurs in all regions except the region covered by the retained compressive stress film (the retained compressive stress film may serve as a barrier layer to block silicon atom migration), so that tensile stress on the channel in the corresponding direction may be increased. In addition, the high temperature in the (DTE) processing process can transfer the compressive stress of the reserved compressive stress film to the channel of the device, so that the compressive stress is additionally applied to the length direction of the channel of the pull-up transistor (PMOS), the effect of a Stress Memorization Technology (SMT) is generated, and the performance of the PMOS is further improved; the compressive stress applied to the channel width direction of the pass gate transistor (NMOS) degrades the performance of the pass gate transistor.
As the performance of the pull-down transistor (PD) is improved, the performance of the pass-gate transistor (PG) is reduced, and thus the β ratio (β ratio) of the SRAM is improved, so that the stability of the SRAM and the Read Static Noise Margin (RSNM) can be improved, thereby improving the performance of the semiconductor device.
In the present embodiment, preferably, the DTE treatment is performed under an annealing condition containing hydrogen gas. The ambient environment preferably comprises other gases such as nitrogen, helium, neon, argon, krypton, xenon, and combinations thereof. The gas pressure is preferably between about 1 torr and 1000 torr, more preferably between about 1 torr and 300 torr. The temperature of the DTE treatment is controlled between 700-1200 c, more preferably between about 900-1100 c. The time of DTE treatment lasts about 5 to 120 seconds.
In this embodiment, the compressive stress film 102 may be replaced by a common film that cannot apply stress to the channel, and at this time, the compressive stress cannot be applied to the channel by the SMT technique, but the migration of silicon atoms in the DTE process can still be blocked, so as to suppress and avoid the tensile stress enhancement effect of the DTE process.
Step A5: the remaining compressive stress film 102' is removed as shown in fig. 4E.
Illustratively, the removing method may be wet stripping or dry etching, etc.
This completes the introduction of the key steps of the embodiments of the present invention. It should be noted that in the above description of the present embodiment, PU, PD, PG each refer to PU, PD, PG to be formed, and these devices will be formed in the subsequent steps. Referred to herein directly as PU, PD, PG, for the sake of brevity.
After the step a5, steps of forming PU, PD, PG and other components may be further included, and related steps may be implemented by referring to the prior art and will not be described herein.
according to the manufacturing method of the semiconductor device, Diffusion Topography Engineering (DTE) is carried out after the diffusion barrier layer (the barrier layer reserved after etching) is arranged, so that the performance of a pull-up transistor and a pull-down transistor can be improved, the performance of a transmission gate transistor is kept or even reduced, the β ratio of an SRAM is improved, the performance of the semiconductor device can be improved, and the performance of the pull-up transistor can be improved in the DTE simultaneously by reasonably arranging the diffusion barrier layer, so that the performance of the semiconductor device is further improved.
Furthermore, the diffusion barrier layer can be a diffusion barrier layer (compressive stress film) with compressive stress, so that, in the DTE treatment process, not only the tensile stress enhancement effect on the channel length direction of the pull-up transistor (PMOS) can be blocked, but also the compressive stress can be applied to the channel length direction of the pull-up transistor through the SMT technology, so that the performance of the pull-up transistor is further improved, and in addition, the compressive stress can be applied to the channel of the transmission gate transistor (NMOS), so that the performance of the transmission gate transistor is further reduced.
Fig. 5 is a flow chart showing an exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention, which is used to schematically show an exemplary flow of the manufacturing method. The method specifically comprises the following steps:
step S101: providing a semiconductor substrate, and defining an active region on the semiconductor substrate;
step S102: forming a diffusion barrier layer on the semiconductor substrate;
step S103: etching the diffusion barrier layer, reserving the part of the diffusion barrier layer in the width direction of the channel of the transmission gate transistor, and removing the part of the diffusion barrier layer in other areas;
step S104: diffusion topography engineering is performed to improve the performance of pull-up and pull-down transistors and to maintain or even degrade the performance of pass-gate transistors.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (10)
1. A method of manufacturing a semiconductor device, the method comprising:
step S101: providing a semiconductor substrate, defining an active region on the semiconductor substrate, wherein the active region is used for manufacturing an SRAM device, the SRAM device comprises a pull-down transistor and a transmission gate transistor, and the pull-down transistor and the transmission gate transistor are NMOS devices;
step S102: forming a diffusion barrier layer on the semiconductor substrate;
step S103: etching the diffusion barrier layer, reserving the part of the diffusion barrier layer in the width direction of the channel of the transmission gate transistor, and removing the part of the diffusion barrier layer in other areas;
step S104: diffusion terrain engineering is performed to improve the performance of the pull-down transistors and to degrade the performance of the pass-gate transistors.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the SRAM device further includes a pull-up transistor, the pull-up transistor is a PMOS device, and in the step S103, a portion of the diffusion barrier layer in a channel length direction of the pull-up transistor is further retained.
3. The method for manufacturing a semiconductor device according to claim 1, wherein in the step S102, the diffusion barrier layer is a compressive stress film; in step S104, the compressive stress of the portion of the diffusion barrier layer that remains is transferred to the channel width direction of the pass gate transistor while the diffusion topographic engineering process is performed.
4. The method for manufacturing a semiconductor device according to claim 2, wherein in the step S102, the diffusion barrier layer is a compressive stress film; in step S104, the compressive stress of the portion of the diffusion barrier layer that remains is transferred to the channel width direction of the pass gate transistor and the channel length direction of the pull-up transistor while the diffusion topographic engineering process is performed.
5. The method for manufacturing a semiconductor device according to claim 3 or 4, wherein in the step S102, a material of the compressive stress film is compressive stress silicon nitride.
6. The method for manufacturing a semiconductor device according to claim 1, wherein in the step S104, the diffusion topography engineering treatment is performed under an annealing condition containing hydrogen gas.
7. The method for manufacturing a semiconductor device according to claim 1, wherein in the step S104, the duration of the diffusion topographic engineering treatment is 5 to 120 seconds.
8. The method for manufacturing a semiconductor device according to claim 1, further comprising, after the step S104, a step S105 of:
removing the remaining portion of the diffusion barrier layer.
9. The method for manufacturing a semiconductor device according to claim 8, wherein in the step S105, a method of removing the portion of the diffusion barrier layer which is left is wet stripping.
10. The method for manufacturing a semiconductor device according to claim 8, further comprising, after the step S105, a step S106 of: and forming a pull-up transistor, a pull-down transistor and a transmission gate transistor in the active area.
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