CN104953984A - Linearized transistor combined inductor - Google Patents

Abstract

The invention provides a linearized transistor combined inductor. The linearized transistor combined inductor comprises a first transconductance amplifier, a second transconductance amplifier, a first current mirror, a second current mirror, a third current mirror, a feedback capacitor, an adjustable resistor, a first adjustable current source and a second adjustable voltage source, wherein the two transconductance amplifiers are connected in an intersected manner to form a gyrator, and the gyrator can convert input capacitance of the second transconductance amplifier into equivalent inductance through gyration; the adjustable resistor is used for increasing an equivalent inductance value and a quality factor Q value of the transistor combined inductor; one MOS (metal-oxide-semiconductor) transistor in the first current mirror is connected with one transistor in the first transconductance amplifier to form a negative resistance network for circuit reuse, and the Q value is increased. With the adoption of a forward feedback current source comprising the feedback capacitor and the three current mirrors, 1-dB compression point of the inductor is increased, and the total harmonic distortion is reduced. The inductor can be applied to the amplifier, the linearity of the amplifier is improved, and the gain stability of the amplifier is realized when the amplitude of the input signals change.

Description

Linearized Transistor Synthetic Inductor

technical field

The invention relates to the fields of radio frequency devices and integrated circuits, in particular to a linearized transistor synthesis inductance.

Background technique

Inductor is one of the commonly used components in radio frequency integrated circuits, and the on-chip planar spiral inductor is widely used at present. The performance of a spiral inductor is closely related to its geometry and size. The larger the inductance value, the larger the area occupied by the spiral inductor, and the lower the Q value of the quality factor, the more difficult the integration and the higher the cost. With the continuous shrinking of the feature size of integrated circuit devices, it is more and more difficult to realize the miniaturization of the chip area of the on-chip spiral inductor. The circuit composed of transistors, resistors, capacitors and other components makes its input impedance present inductive characteristics, and can be used as an inductive element instead of a spiral inductor. Using the inductance synthesized by transistors, compared with the spiral inductor, the transistor synthesized inductance occupies a small chip area and has a high quality factor Q value, and its equivalent inductance value and quality factor Q value can be tuned, which solves the problem of spiral inductors in radio frequency circuits. Problems, can be used in radio frequency integrated circuits and radio frequency systems instead of spiral inductors. At the same time, the synthetic inductance of the transistor also has shortcomings: the inductance synthesized by the transistor has nonlinear factors due to the nonlinear factors of the transistor itself, so that the synthetic inductance of the transistor has nonlinear factors. Therefore, the application of transistor synthesized inductance in radio frequency circuits has certain limitations. In radio frequency circuits with high linearity requirements, it is necessary to increase the circuit structure to improve the linearity of transistor synthesized inductance.

Contents of the invention

The object of the present invention is to provide a linearized transistor synthesis inductance. The linearity of the inductance is improved by using a forward feedback current source, the input 1-dB compression point of the inductance value is increased by 8dBm, and the total harmonic distortion is reduced by up to 19%. The negative resistance network of circuit multiplexing is adopted, and the DC bias in the inductance circuit and the active devices in the transconductance are formed by multiplexing transistors to form a negative resistance network, which improves the Q value of the inductance. The inductor of the present invention is applied to the amplifier, which can improve the linearity of the amplifier, and when the amplitude of the input signal changes, the gain of the amplifier is stable.

The present invention adopts following technical scheme:

A linearized transistor synthesis inductance is shown in Figure 1 , including: a first transconductance amplifier, a second transconductance amplifier, a first current mirror, a second current mirror, a third current mirror, a feedback capacitor, an adjustable resistor, The first adjustable current source and the second adjustable current source.

The first and second transconductance amplifiers are respectively a positive transconductance amplifier and a negative transconductance amplifier, and the two transconductance amplifiers are cross-connected to form a gyrator. The input terminal of the first transconductance amplifier is the input terminal of the synthetic inductance of the transistor, and is connected with the output terminal of the second transconductance amplifier, and the output terminal of the first transconductance amplifier is connected with the input terminal of the second transconductance amplifier through an adjustable resistance. The transconductance amplifier is a single-stage amplifier composed of bipolar transistors or a multi-stage amplifier composed of cascaded bipolar transistors. The gyrator formed by the first and second transconductance amplifiers can turn the input equivalent capacitance of the second transconductance amplifier into an equivalent inductance.

The first terminal of the adjustable resistor is connected to the output terminal of the first transconductance amplifier, and the second terminal of the adjustable resistor is connected to the input terminal of the second transconductance amplifier. When the resistance value of the adjustable resistor is changed, the equivalent inductance value and quality factor Q value of the synthesized inductance of the transistor can be adjusted. The adjustable resistance is used to enhance the adjustability of the synthesized inductance of the transistor.

The first current mirror, the second current mirror, the third current mirror and the feedback capacitor form a forward feedback current source. The first end of the first current mirror is connected to the second end of the second current mirror, the second end of the first current mirror is connected to the input end of the synthesized inductance of the transistor, and the first end of the second current mirror is connected to the second end of the third current mirror, The first end of the third current mirror is connected to the second adjustable current source. The first terminal of the feedback capacitor is connected to the input terminal of the second transconductance amplifier, and the second terminal of the feedback capacitor is connected to the mirror connection point of the third current mirror, wherein: the current at the first terminal of the current mirror is the reference current, and the current at the second terminal of the current mirror is the mirror image current, the mirror connection point is the symmetry point between the reference current and the mirror current in the current mirror. The linearity of the synthesized inductance of the transistor is improved by using a feed-forward current source.

The first adjustable current source and the second adjustable current source are voltage-controlled current sources, and the output bias current can be adjusted when the external bias voltage is adjusted. The first adjustable current source is connected to the first end of the third current mirror, and the second adjustable current source is connected to the output end of the first transconductance amplifier to adjust the magnitude of the current of the first adjustable current source and the second adjustable current source, The inductance value and the quality factor Q value of the synthesized inductance of the transistor can be adjusted.

The mirror connection point of the first current mirror is connected with the output end of the first transconductance amplifier to form a negative resistance network for circuit multiplexing, which further improves the Q value of the quality factor.

Compared with the prior art, the present invention has the following advantages:

The invention innovatively adopts a forward feedback current source, improves the 1-dB compression point of the inductance, and improves the total harmonic distortion, thereby improving the linearity of the inductance. At the same time, the negative resistance network of circuit multiplexing is adopted, and the current mirror in the inductance circuit and the active device in the positive transconductance are formed by multiplexing transistors to form a negative resistance network, which improves the Q value of the inductance.

Description of drawings

Fig. 1 is the structural block diagram of the transistor synthetic inductance of linearization of the present invention;

1-First transconductance amplifier, 2-Second transconductance amplifier, 3-First current mirror, 4-Second current mirror, 5-Third current mirror, 6-Feedback capacitor, 7-Adjustable resistor, 8- 1st adjustable current source, 9-second adjustable current source

Fig. 2 is the embodiment of the transistor synthetic inductance of linearization of the present invention;

Fig. 3 is the relationship between the inductance value and the frequency of the transistor synthetic inductance of linearization of the present invention;

Fig. 4 is the relationship diagram of the Q value and the frequency of the transistor synthetic inductance of linearization of the present invention;

Fig. 5 is the change of the inductance value of the transistor synthesis inductance of the present invention with the input signal; 1- adopts multi-level current mirror and capacitive coupling feedback branch, 2- does not adopt multi-level current mirror and capacitive coupling feedback branch

Fig. 6 is the total harmonic distortion of the synthesized inductance of the linearized transistor of the present invention.

1- Using multi-level current mirror and capacitive coupling feedback branch, 2- Not using multi-level current mirror and capacitive coupling feedback branch.

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings .

The linearized transistor synthesis inductance in the present invention comprises: the first transconductance amplifier, the second transconductance amplifier, the first current mirror, the second current mirror, the third current mirror, feedback capacitance, adjustable resistance, the first adjustable current source, the second adjustable current source. Fig. 2 is an embodiment of the linearized transistor synthesized inductance in the present invention.

The first transconductance amplifier in this embodiment is composed of a first bipolar transistor (Q1) and a third bipolar transistor (Q3), the first transconductance amplifier is a negative transconductance amplifier, and the second transconductance amplifier is composed of a second transconductance amplifier. Two bipolar transistors (Q2) are formed, the second transconductance amplifier is a positive transconductance amplifier, and the adjustable resistance is composed of a ninth MOS transistor (M _R ) and a first resistance (R _f ); the positive and negative transconductance amplifiers The constituted gyrator can turn the equivalent input capacitance of the second transconductance amplifier into an equivalent inductance, and the adjustable resistor is connected to the output terminal of the first transconductance amplifier and the input terminal of the second transconductance amplifier to improve the transistor The inductance and Q value of the synthesized inductor. The first MOS transistor (M1) is used to provide bias current for the collector of the second bipolar transistor (Q2), and the second MOS transistor (M2) is used to provide bias current for the first bipolar transistor (Q1) and the third bipolar transistor (Q2). The collector of the polar transistor (Q3) supplies the bias current.

The specific embodiment of the circuit formed by the first transconductance amplifier, the second transconductance amplifier and the adjustable resistance in this embodiment is: the base of the first bipolar transistor (Q1) is the input end of the first transconductance amplifier, And as the input terminal of the linearized transistor synthesis inductance, the emitter of the first bipolar transistor (Q1) is grounded, and the collector of the first bipolar transistor (Q1) is connected to the third bipolar transistor (Q3). The emitter is connected to the gate of the first MOS transistor (M1) at the same time, the base of the third bipolar transistor (Q3) is connected to the bias voltage source V _B3 , and the collector of the third bipolar transistor (Q3) is the first An output terminal of the transconductance amplifier is connected to the drain of the second MOS transistor (M2), and simultaneously connected to the source of the ninth MOS transistor (M _R ) and the second terminal of the first resistor (R _f ). The base of the second bipolar transistor (Q2) is the input terminal of the second transconductance amplifier, connected to the first terminal of the first resistor (R _f ), and connected to the drain of the ninth MOS transistor (M _R ), the second The collector of the bipolar transistor (Q2) is connected to the supply voltage, the emitter of the second bipolar transistor (Q2) is the output of the second transconductance amplifier, and the base of the first bipolar transistor (Q1) is connected to The drain of the first MOS transistor (M1) and the source of the first MOS transistor (M1) are grounded. The source of the second MOS transistor (M2) is connected to the power supply voltage, and the gate is connected to the second bias voltage source V _tune2 .

In this embodiment, the feed-forward current source is formed by the first current mirror, the second current mirror, the third current mirror and the feedback capacitor. The first MOS transistor (M1) and the third MOS transistor (M3) constitute the first current mirror, the fourth MOS transistor (M4), the fifth MOS transistor (M5) and the first capacitor (C1) constitute the second current mirror, and the fourth MOS transistor (M4), the fifth MOS transistor (M5) and the first capacitor (C1) constitute the second current mirror. The six MOS transistors (M6), the seventh MOS transistor (M7) and the second resistor (Rg) constitute the third current mirror, the second capacitor (C2) is the feedback capacitor, and the eighth MOS transistor (M8) provides the third current mirror base current.

In this embodiment, the specific implementation manner in which the forward feedback current source is formed by the first current mirror, the second current mirror, the third current mirror and the feedback capacitor is as follows: the drain of the third MOS transistor (M3) is the first current mirror The drain current of the third MOS transistor (M3) is the reference current of the first current mirror. The drain of the first MOS transistor (M1) is the second terminal of the first current mirror, and the drain current of the first MOS transistor (M1) is the mirror current of the first current mirror. The gate of the first MOS transistor (M1) is connected to the gate and drain of the third MOS transistor (M3), the source of the third MOS transistor (M3) is grounded, and the drain of the third MOS transistor (M3) is connected to the fourth The drain of the MOS transistor (M4). The drain of the fifth MOS transistor (M5) is the first end of the second current mirror, the drain current of the fifth MOS transistor (M5) is the reference current of the second current mirror, and the drain of the fourth MOS transistor (M4) is the second terminal of the second current mirror, and the drain current of the fourth MOS transistor (M4) is the mirror current of the second current mirror. The source of the fourth MOS transistor (M4) is connected to the power supply voltage, the gate of the fourth MOS transistor (M4) is connected to the gate and drain of the fifth MOS transistor (M5), and connected to the first terminal of the first capacitor (C1) connected, the second end of the first capacitor (C1) is grounded, and the source of the fifth MOS transistor (M5) is connected to the power supply voltage. The drain of the seventh MOS transistor (M7) is the first end of the third current mirror, the drain current of the seventh MOS transistor (M7) is the reference current of the third current mirror, and the drain of the sixth MOS transistor (M6) is the second terminal of the third current mirror, the drain current of the sixth MOS transistor (M6) is the mirror current of the third current mirror, and the gate of the sixth MOS transistor (M6) is the mirror connection point. The drain of the sixth MOS transistor (M6) is connected to the drain of the fifth MOS transistor (M5), the source of the sixth MOS transistor (M6) is grounded, and the gate of the sixth MOS transistor (M6) is connected to the second capacitor (C2 ) second terminal, and connect the first terminal of the second resistor (Rg) at the same time, the second terminal of the second resistor (Rg) is connected to the gate and drain of the seventh MOS transistor (M7), and the source of the seventh MOS transistor (M7) Pole grounded. The drain of the seventh MOS transistor (M7) is connected to the drain of the eighth MOS transistor (M8), the gate of the eighth MOS transistor (M8) is connected to the first adjustable voltage source V _tune1 , the eighth MOS transistor (M8) The source is connected to the supply voltage. The first end of the second capacitor (C2) is connected to the base of the second bipolar transistor (Q2).

In this embodiment, the forward feedback current source composed of the first current mirror, the second current mirror, the third current mirror and the feedback capacitor is used to improve the linearity of the synthesized inductance of the transistor. The working principle is as follows: when the input voltage signal v When the amplitude of _in increases, the drain current I _D1 of the first MOS transistor (M1) increases, assuming that the gate voltage V _G1 of the first MOS transistor (M1) remains unchanged, then the second bipolar transistor (Q2) The junction voltage V _CE2 between the collector and the emitter decreases, the collector current I _C2 of the second bipolar transistor (Q2) decreases, and the base current I _B2 increases, and at this time the second bipolar transistor (Q2) The base emitter junction voltage V _BE2 of the transistor (Q2) decreases, so the I′ _B2 current flowing through R _g is generated, coupled by the second capacitor (C2), the gate voltage of the sixth MOS transistor (M6) V _G6 drops, the drain current I _D6 decreases, the fourth MOS transistor (M4) and the fifth MOS transistor (M5) form a mirror constant current source, the drain current _ID4 of M ₄ decreases, and the third MOS transistor (M3 The voltage V _GS3 between the gate and source of ) decreases, the third MOS transistor (M3) and the first MOS transistor (M1) form a mirror constant current source, and the drain current _ID1 of the first MOS transistor (M1) decreases small, thereby eliminating the influence of the input signal. Therefore, using the forward feedback current source, when the input signal changes, the influence of the signal amplitude can be eliminated, thereby improving the linearity of the inductance.

In this embodiment, the first MOS transistor (M1) and the first bipolar transistor (Q1) are cross-connected to form a circuit multiplexed negative resistance network. The principle of generating negative resistance in this circuit is as follows: the voltage signal is input from the input terminal of the synthesized inductance of the transistor, and its input voltage is converted into the collector current of the first bipolar transistor (Q1), and at the same time, it is supplied to the gate of the first MOS transistor (M1). The capacitor C _gs1 between the electrode and the source is charged, and the capacitor voltage generated by C _gs1 is converted into the drain current of the first MOS transistor (M1) through the first MOS transistor (M1), forming a positive feedback negative resistance. The negative resistance network can offset a part of the positive resistance, thereby improving the Q value of the synthesized inductance of the transistor.

In this embodiment, the first adjustable current source is composed of the eighth MOS transistor (M8), and the bias current can be adjusted by adjusting the gate bias voltage of the eighth MOS transistor (M8), that is, the size of the first bias voltage source V _tune1 . The second adjustable current source is composed of a second MOS transistor (M2), and the bias current can be adjusted by adjusting the gate bias voltage of the second MOS transistor (M2), that is, the size of the second adjustable voltage source V _tune2 . The gate of the ninth MOS transistor (M _R ) is connected to the third adjustable voltage source V _tune3 . Adjusting the first adjustable voltage source V _tune1 , the second adjustable voltage source V _tune2 , and the third adjustable voltage source V _tune3 can change the equivalent inductance and Q value of the active inductor. The voltage adjustment range of the first adjustable voltage source V _tune1 is 0-2 volts, the voltage adjustment range of the second adjustable voltage source V _tune2 is 0-2 volts, and the third adjustable voltage source V _tune3 The voltage adjustment range is 0-3 volts, the voltage of the bias voltage source V _B3 is 1.8 volts, and the power supply voltage is 2.5 volts.

In this embodiment, the first MOS transistor (M1), the third MOS transistor (M3), the sixth MOS transistor (M6), the seventh MOS transistor (M7) and the ninth MOS transistor (M _R ) is an NMOS transistor, the second MOS transistor (M2), the fourth MOS transistor (M4), the fifth MOS transistor (M5) and the eighth MOS transistor (M8) are PMOS transistors.

FIG. 3 shows the relationship between the inductance value and the frequency of the above embodiment, and it can be seen that the equivalent inductance value of the synthesized inductance of the linearized transistor is adjustable. When the voltage of the first adjustable voltage source V _tune1 is 0.6V, the voltage of the second adjustable voltage source V _tune2 is 0.9V, and the voltage of the third adjustable voltage source V _tune3 is 0.8V, the equivalent inductance value reaches the maximum at 4.4GHz The value is 23.5nH, the self-resonant frequency f ₀ is 5GHz; the voltage of the first adjustable voltage source V _tune1 is 0.7V, the voltage of the second adjustable voltage source V _tune2 is 1.1V, and the voltage of the third adjustable voltage source V _tune3 is 0.3V , the equivalent inductance value reaches the maximum value of 33.6nH at 4.2GHz, and the self-resonant frequency f ₀ is 4.9GHz.

FIG. 4 is the relationship between the quality factor Q value and the frequency of the above embodiment, it can be seen that the Q value of the synthesized inductor of the linearization transistor is adjustable. When the voltage of the first adjustable voltage source V _tune1 is 0.6V, the voltage of the second adjustable voltage source V _tune2 is 0.9V, and the voltage of the third adjustable voltage source V _tune3 is 0.8V, when the frequency is 3.1GHz, the Q value reaches The maximum value is 151; when the voltage of the first adjustable voltage source V _tune1 is 0.7V, the voltage of the second adjustable voltage source V _tune2 is 1.1V, and the voltage of the third adjustable voltage source V _tune3 is 0.3V, the Q value reaches the maximum value of 578 . In the 2.5-3.6GHz frequency band, the Q value is greater than 20.

Fig. 5 is a comparison diagram of the inductance value 1-dB compression point when the above embodiment adopts and does not adopt the forward feedback current source. The curve shows the change of the inductance value with the input signal, reflecting the sensitivity of the inductance value to the input signal. When the frequency is 2GHz, the input signal voltage corresponding to the 1-dB compression point of the inductance value using the forward feedback current source is -23dBm, and the input signal voltage corresponding to the 1-dB compression point of the inductance value without the forward feedback current source is -31dBm. Using the inductor with multi-stage current source and capacitive coupling feedback, the 1-dB compression point is increased by 8dBm, which improves the linearity of the inductor.

FIG. 6 is a comparison diagram of the total harmonic distortion (THD) of the above embodiment with and without the forward feedback current source. It can be seen from the figure that when the input signal voltage is the same, the degree of total harmonic distortion is reduced when the forward feedback current source is used compared with the inductor without the forward feedback current source, and the maximum THD is reduced by 19%. .

The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (7)

1. a linearizing transistor combination inductance, it is characterized in that, comprise: the first trsanscondutance amplifier, second trsanscondutance amplifier, first current mirror, second current mirror, 3rd current mirror, feedback capacity, adjustable resistance, first adjustable current source, second adjustable current source, the input of the first trsanscondutance amplifier is the input of transistor combination inductance, and connect the output of the second trsanscondutance amplifier, the output of the first trsanscondutance amplifier connects the input of the second trsanscondutance amplifier by adjustable resistance, described adjustable resistance first end connects the output of the first trsanscondutance amplifier, adjustable resistance second end connects the input of the second trsanscondutance amplifier, the first end of the first current mirror is connected with the second current mirror second end, second end of the first current mirror connects transistor combination inductance input, the first end of the second current mirror connects the 3rd current mirror second end, 3rd current mirror first end connects the first adjustable current source, feedback capacity first end connects the input of the second trsanscondutance amplifier, feedback capacity second end connects the mirror image tie point of the 3rd current mirror, second adjustable current source connects the output of the first trsanscondutance amplifier.

2. linearizing transistor combination inductance as claimed in claim 1, is characterized in that, first, second trsanscondutance amplifier described is respectively a positive trsanscondutance amplifier and a negative transconductance amplifier, and two trsanscondutance amplifier interconnections form gyrator; Gyrator is equivalent inductance the revolution of the equivalent input capacitance of the second trsanscondutance amplifier.

3. linearizing transistor combination inductance as claimed in claim 2, is characterized in that, first, second trsanscondutance amplifier described is the one-stage amplifier of bipolar transistor formation or the casacade multi-amplifier by bipolar transistor cascade.

4. linearizing transistor combination inductance as claimed in claim 1, is characterized in that, the first described current mirror, the second current mirror, the 3rd current mirror and feedback capacity form feed-forward current source.

5. linearizing transistor combination inductance as claimed in claim 4, is characterized in that, current mirror first end electric current is reference current, and current mirror second end electric current is image current, and mirror image tie point is the symmetric points of reference current and image current in current mirror.

6. linearizing transistor combination inductance as claimed in claim 1, is characterized in that, the first adjustable current source, the second adjustable current source electric current are Voltage-controlled Current Source, when regulating external bias voltage, and adjustable output offset electric current.

7. linearizing transistor combination inductance as claimed in claim 1, is characterized in that, the mirror image tie point of the first current mirror and the output of the first trsanscondutance amplifier connect and compose the negative resistance network of circuit multiplexer, improves Q value.