CN104951334B - FPGA biplate QSPI flash program loading method - Google Patents
FPGA biplate QSPI flash program loading method Download PDFInfo
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- CN104951334B CN104951334B CN201510263302.2A CN201510263302A CN104951334B CN 104951334 B CN104951334 B CN 104951334B CN 201510263302 A CN201510263302 A CN 201510263302A CN 104951334 B CN104951334 B CN 104951334B
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- 230000002093 peripheral effect Effects 0.000 claims abstract description 22
- 230000015654 memory Effects 0.000 claims abstract description 21
- 230000008676 import Effects 0.000 claims abstract 2
- 230000006870 function Effects 0.000 claims description 15
- 238000010276 construction Methods 0.000 claims description 2
- 230000006399 behavior Effects 0.000 claims 1
- 238000007711 solidification Methods 0.000 claims 1
- 230000008023 solidification Effects 0.000 claims 1
- 238000011068 loading method Methods 0.000 abstract description 7
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Abstract
A kind of FPGA biplates QSPI flash proposed by the present invention program loading method, it is desirable to provide a kind of loading velocity is fast, flexible and efficient biplate QSPI flash program loading method, the technical scheme is that：In Xilinx companies programmable logic array FPGA SDKs SDK, the application APP of newly-built one readwrite tests to 4 bit serial peripheral memory interface QSPI flash；In APP, parameter configuration is carried out to QSPI flash, configuration QSPI flash are input/output pattern；Import curing document, it would be desirable in the peripheral hardware memory chip DDR3 that the content being cured in flash downloads to FPGA from PC, read the content for needing to solidify by page by QSPI flash APP application programs, and be written in QSPI flash corresponding address.The present invention solves the problems, such as that the parallel 8 bit Quad SPI flash of biplate loading problem and FPGA developing instruments SDK and flashburn tools IMPACT are unable to the parallel QSPI flash of programming 8bit.
Description
Technical field
The present invention is a kind of program loading method for the biplate QSPI flash for being related to Zynq-7000 Series FPGAs, we
Method is applicable to Zynq-7000 Series FPGA platforms used.
Background technology
With the development of programming logic gate array FPGA (hereinafter referred to as FPGA) technology, FPGA function is increasingly
By force, type is also more and more.The characteristics of due to FPGA internal structures, FPGA program are typically stored in the non-volatile of outside
In memory, upon power-up of the system, program is loaded into FPGA operations from external memory storage, this process is referred to as program and added
Carry.Zynq-7000 Series FPGAs (hereinafter referred to as Zynq-7000) are a new FPGA that Xilinx companies of the U.S. release, with
Other model FPGA are compared, and its processing unit is divided into PS and the parts of PL bis-, and PS refers to embedded double ARM processing in zynq-7000
Device core, PL partly refer to traditional fpga logic part.It using ARM cores is leading that Zynq-7000, which is, is guided by ARM, configures PL portions
Point, therefore Zynq-7000 is more likely to be classified as the embeded processor similar with PowerPC, rather than one from operation principle
The traditional FPGA of kind.Zynq-7000 program loading method has a variety of, generally there is 4 bit serial peripheral memory interface Quad-
SPI flash (hereinafter referred to as Quad-SPI flash) loading method, NAND flash memories load mode, NOR
Four kinds of flash memory load mode, SD card load mode.Quad-SPI flash program load modes have program loading frequency
The advantages of rate is high, chip area footprints are small, therefore be used widely.
Quad-SPI flash programs load modes are divided into monolithic 4-bit load modes, the parallel 8-bit loading sides of biplate again
Formula, and three kinds of biplate cascade 4-bit load modes, it is as shown in the table：
Because Zynq-7000 is powerful, the capacity of commonly required flash memory is more than 16MB, therefore generally use 2
Quad-SPI flash storing program therefors, flash programming process are typically provided by FPGA exploitation software, Zynq-7000
The exploitation software I SE/Vivado of Series FPGA also provides Quad-SPI flash program burn writing functions, but problem be present, i.e.,
Programming can not be carried out to the Quad-SPI flash parallel 8-bit modes of biplate, cause Zynq-7000 Series FPGAs to carry out
Normal program loading, can not complete electric self-starting function, make high performance Zynq-7000 Series FPGAs application limited.
Zynq-7000 Series FPGAs exploitation software (version is ISE14.7 or vivado2013.4) can't programming at present
The parallel QSPI flash of 8bit, usual technical staff can only use FPGA exploitation software to realize FPGA flash programming functions,
There is no other selections.
The content of the invention
The present invention task be in view of the shortcomings of the prior art, can not for the exploitation software of Zynq-7000 Series FPGAs
The defects of correct programming biplate 8bit parallel QSPI flash (the bug problems for being defined as FPGA exploitation software), there is provided a kind of
Loading velocity is fast, the biplate QSPI flash of flexible and efficient, new Zynq-7000 Series FPGAs program loading method, with de-
From the limitation that the exploitation software for having to rely on FPGA carries out QSPI flash programmings, enable FPGA upper electric self-starting function complete
Into.
The above-mentioned purpose of the present invention can be reached by following measures, and a kind of FPGA biplates QSPI flash program adds
Support method, it is characterised in that comprise the following steps：In Xilinx companies programmable logic array FPGA SDKs SDK
In, the application APP (hereinafter referred to as APP) of a newly-built readwrite tests to QSPI flash；In APP, to QSPI
Flash carries out parameter configuration, and configuration QSPI flash are input/output pattern, i.e. I/O mode (hereinafter referred to as I/O mode)；Lead
Enter curing document, it would be desirable to which the content being cured in flash downloads to FPGA peripheral hardware internal memory DDR3 (hereinafter referred to as from PC
DDR3 in), the content for needing to solidify is read by page by QSPI flash APP application programs, and be written to QSPI flash's
In corresponding address.
The present invention has the advantages that compared to prior art：
The present invention is used in Xilinx FPGA developing instruments SDK, a newly-built readwrite tests to QSPI flash
APP programs, based on independently writing program burn writing, there is provided a kind of new programming mode, so that Zynq-7000 Series FPGAs
Program is solidified, and makes the current zynq-7000 parallel QSPI flash programming methods of biplate 8bit realize from scratch；
The present invention is based on the parallel QSPI flash of biplate 8bit for independently writing program burn writing zynq-7000, departing from right
The limitation of FPGA exploitation software, programming correctly can be carried out in the Quad-SPI flash parallel 8-bit flash of biplate,
The program of Zynq-7000 Series FPGAs is set to solidify, the loading for solving the parallel 8-bit Quad-SPI flash of biplate is asked
Topic and FPGA developing instruments SDK and flashburn tools IMPACT are unable to the problem of programming 8bit parallel QSPI flash.
The present invention has the following advantages that compared to prior art：
Burn writing speed is fast：Compared to other original FPGA programming modes, burn writing speed is constant, is not easy to adjust, this
Invent the loading method proposed, it would be desirable in the peripheral hardware internal memory DDR3 that the content being cured in flash downloads to FPGA from PC,
Read, and be written in QSPI flash address by page by QSPI flash APP application programs, can be according to actual use
QSPI flash models, programming frequency and speed are adjusted, makes it with maximal rate programming.
It is flexible and efficient.The present invention based on SDK application programs, entirely autonomous develops in Zynq-7000 Series FPGAs
The parallel QSPI flash of biplate 8bit of Zynq-7000 Series FPGAs program loading method, departing from having to rely on FPGA's
Develop the limitation that software carries out QSPI flash programmings so that FPGA upper electric self-starting function is accomplished.
Brief description of the drawings
Accompanying drawing is Zynq-7000 Series FPGAs and QSPI flash connected mode.
Fig. 1 is that Zynq-7000 Series FPGAs connect 1 QSPI flash, and data are illustrated for 4 bit bit wide fashion embodiments
Figure.
Fig. 2 is that Zynq-7000 Series FPGAs connect 2 QSPI flash, cascade system, and data are implemented for 4 bit bit wides
Illustrate and be intended to.
Fig. 3 is that Zynq-7000 Series FPGAs connect 2 QSPI flash, parallel way, and data are implemented for 8 bit bit wides
Illustrate and be intended to.
Embodiment
Refering to Fig. 1-Fig. 3.The serial peripheral memory interface of Zynq-7000 Series FPGAs and 4 bit serial peripheral hardwares store
Device connected mode shares 3 kinds, and the serial peripheral memory interface of Zynq-7000 Series FPGAs, there is 4bit data wherein shown in Fig. 1
Line is connected with 14 bit serial peripheral memory QSPI flash, and this connected mode is referred to as monolithic 4bit bit wide connection sides
Formula；The serial peripheral memory interface of Zynq-7000 Series FPGAs shown in Fig. 2, have outside 4bit data wires and 24 bit serials
If memory QSPI flash are connected, 24 bit serial peripheral memory QSPI flash are referred to as QSPI_flash_1,
QSPI_flash_2, this connected mode are referred to as monolithic 4bit bit wide cascade systems；Zynq-7000's Series FPGAs shown in Fig. 3
Serial peripheral memory interface, there are 8bit data wires to be connected with 24 bit serial peripheral memory QSPI flash, 24 ratios
Special serial peripheral memory QSPI flash are referred to as QSPI_flash_1, QSPI_flash_2, and this connected mode is referred to as
Biplate 8bit bit wide parallel modes.
FPGA biplate QSPI flash program loading method specifically comprises the following steps：It may be programmed and patrol in Xilinx companies
Collect in array FPGA SDKs SDK, the application APP of a readwrite tests to QSPI flash newly-built first
(hereinafter referred to as APP), for the readwrite tests to QSPI flash；In SDK, using new construction guide, newly-built one
APP application programs, it is therefore an objective to test the parallel QSPI flash of peripheral hardware biplate 8bit of Zynq-7000 Series FPGAs, lead to
Cross and QSPI flash APP application programs are modified, two QSPI flash are read and write with completion, erasing operation.
In APP application programs, parameter configuration is carried out to QSPI flash, configuration QSPI flash are input/output pattern, i.e. IO moulds
Formula (hereinafter referred to as I/O mode)；It is read again, reads the id information of QSPI flash chips in APP application programs,
And QSPI flash relevant information is obtained, such as manufacturer, capacity, block size information.Register is set：In APP application programs
In, the bit 1 for setting the configuration register 1 (Configuration Register 1, CR1) of QSPI flash chips is 1, is made
QSPI flash chips support 4bit operations.It is then introduced into curing document, it would be desirable to the content being cured in flash, it is false below
The entitled function.bin of its fixed file, the peripheral hardware internal memory DDR3 of Zynq-7000 Series FPGAs is downloaded to (hereinafter referred to as from PC
For DDR3) in, i.e., curing document function.bin is imported into the peripheral hardware internal memories of Zynq-7000 Series FPGAs by JTAG
In DDR3, this operation can be completed by inputting order in SDK debugging interface XMD, is ordered as dow-data
Function.bin 0x100000, represent the address for being 0x100000 by function.bin storage initial addresses；Wipe QSPI
Flash, in APP application programs, according to QSPI flash model, specific erasing order is sent, its erasing order is
60h, or C7h, h are expressed as 16 systems, and erasing operation is carried out to QSPI flash；Programming curing document, in APP application programs
In, the function.bin files at the 0x100000 of address are read by QSPI flash page, and be written to QSPI
In flash, write order used is 02h or 32h, for solving FPGA the developing instruments SDK and FPGA of Xilinx companies burning
The instrument IMPACT of writing is unable to the problem of programming 8bit parallel QSPI flash.
QSPI flash models used in the present invention are the S25FL128 of Spasion companies, method provided by the invention
It is also applied for the QSPI flash models of other companies.
Claims (9)
1. a kind of FPGA biplates QSPI flash program loading method, it is characterised in that comprise the following steps：It is public in Xilinx
Take charge of in programmable logic array FPGA SDKs SDK, newly-built one to 4 bit serial peripheral memory interface QSPI
The application APP of flash readwrite tests；In APP, peripheral hardware biplate parallel cascade or the QSPI flash of parallel connection are carried out
Parameter configuration, configuration QSPI flash are input/output pattern IO；Import curing document, it would be desirable to be cured to interior in flash
Hold download to FPGA from PC peripheral hardware memory chip DDR3 in, by QSPI flash APP application programs will need solidify in
Hold and read by page, and be written in QSPI flash corresponding address.
2. FPGA biplates QSPI flash as claimed in claim 1 program loading method, it is characterised in that：FPGA is
Zynq-7000 series, the QSPI flash interfaces of Zynq-7000 Series FPGAs share 8 position datawires, are divided into 24 data
Line, it is connected respectively with 2 QSPI flash, 2 QSPI flash are respectively qspi flash_1, qspi flash_2.
3. FPGA biplates QSPI flash as claimed in claim 1 or 2 program loading method, it is characterised in that：In FPGA
In SDK SDK, using new construction guide, a newly-built APP application program, to Zynq-7000 Series FPGAs
The parallel QSPI flash of peripheral hardware biplate 8bit tested, it is complete by being modified to QSPI flash APP application programs
Paired two QSPI flash reading and writing, erasing operation.
4. FPGA biplates QSPI flash as claimed in claim 1 program loading method, it is characterised in that：It is read out
During operation, the id information of QSPI flash chips is read by APP application programs, obtains QSPI flash relevant information.
5. FPGA biplates QSPI flash as claimed in claim 1 program loading method, it is characterised in that：Applied in APP
In program, the bit 1 for setting the configuration register 1 of QSPI flash chips is 1, QSPI flash chips is supported 4bit behaviour
Make.
6. FPGA biplates QSPI flash as claimed in claim 1 program loading method, it is characterised in that：Will solidification text
Part function.bin is imported into the peripheral hardware internal memory DDR3 of Zynq-7000 Series FPGAs by JTAG, passes through the debugging in SDK
Order is inputted in interface XMD can complete this operation, and ordering will for dow-data function.bin 0x100000, expression
The address that function.bin storage initial addresses are 0x100000.
7. FPGA biplates QSPI flash as claimed in claim 1 program loading method, it is characterised in that：Applied in APP
In program, according to QSPI flash model, specific erasing order is sent, erasing operation, programming are carried out to QSPI flash
Curing document.
8. FPGA biplates QSPI flash as claimed in claim 1 program loading method, it is characterised in that：Applied in APP
In program, the function.bin files at the 0x100000 of address are read by QSPI flash page, and be written to QSPI
In flash, write order used is that 02h or 32h, h are expressed as 16 systems.
9. FPGA biplates QSPI flash as claimed in claim 1 program loading method, it is characterised in that：It is used
QSPI flash models are S25FL128, and its erasing order is 60h, or C7h, h are expressed as 16 systems.
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| CN105515709A (en) * | 2015-12-07 | 2016-04-20 | 中国电子科技集团公司第三十二研究所 | Time synchronization device based on domestic FPGA and uclinux operating system |
| CN105573800B (en) * | 2015-12-22 | 2018-09-18 | 中船重工（武汉）凌久电子有限责任公司 | A kind of veneer or multi-slab and online updating method based on ZYNQ |
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| CN107196695A (en) * | 2017-04-07 | 2017-09-22 | 西安电子科技大学 | Inter-satellite Links test system based on Zynq |
| CN107347158A (en) * | 2017-06-01 | 2017-11-14 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Aircraft load terminal image compression method |
| CN107948653A (en) * | 2017-11-03 | 2018-04-20 | 中国航空无线电电子研究所 | A kind of video compress and recorder |
| CN108021385A (en) * | 2017-12-29 | 2018-05-11 | 北京神州龙芯集成电路设计有限公司 | A kind of programming system and method for onboard SPI Flash |
| CN108427651A (en) * | 2018-03-15 | 2018-08-21 | 天津光电丰泰科技有限公司 | A kind of difunctional multiplexing method based on Zynq Qspi-Flash |
| CN111124433B (en) * | 2018-10-31 | 2024-04-02 | 华北电力大学扬中智能电气研究中心 | Program programming equipment, system and method |
| CN111563059B (en) * | 2019-12-18 | 2022-05-24 | 中国船舶重工集团公司第七0九研究所 | PCIe-based multi-FPGA dynamic configuration device and method |
| CN112114874B (en) * | 2020-08-20 | 2021-10-15 | 北京百度网讯科技有限公司 | Data processing method and device, electronic equipment and storage medium |
| CN112445540B (en) * | 2020-11-10 | 2023-05-09 | 惠州市创荣发智能科技有限公司 | Program running method, system, terminal and storage medium |
| CN113434207B (en) * | 2021-06-09 | 2023-03-24 | 山东航天电子技术研究所 | Zynq UltraScale + SoC configuration file loading reconstruction method |
| CN118093440B (en) * | 2024-04-24 | 2024-07-02 | 中电科申泰信息科技有限公司 | QSPI FLASH program curing system and method based on serial port |
| CN119089839B (en) * | 2024-11-07 | 2025-01-28 | 中科亿海微电子科技（苏州）有限公司 | Quick configuration method for programmable logic device |
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