CN104935405A - Method suitable for DS-1 frame receiving side analysis - Google Patents
Method suitable for DS-1 frame receiving side analysis Download PDFInfo
- Publication number
- CN104935405A CN104935405A CN201510227749.4A CN201510227749A CN104935405A CN 104935405 A CN104935405 A CN 104935405A CN 201510227749 A CN201510227749 A CN 201510227749A CN 104935405 A CN104935405 A CN 104935405A
- Authority
- CN
- China
- Prior art keywords
- frame
- ram
- sequence
- search
- matrix
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000004458 analytical method Methods 0.000 title claims description 4
- 239000011159 matrix material Substances 0.000 claims description 29
- 150000001875 compounds Chemical class 0.000 claims description 5
- 239000000284 extract Substances 0.000 claims description 5
- 238000004904 shortening Methods 0.000 claims description 2
- 239000002131 composite material Substances 0.000 claims 1
- 238000000605 extraction Methods 0.000 claims 1
- 101000840457 Homo sapiens Peptidyl-tRNA hydrolase ICT1, mitochondrial Proteins 0.000 description 67
- 102100029221 Peptidyl-tRNA hydrolase ICT1, mitochondrial Human genes 0.000 description 67
- 238000010586 diagram Methods 0.000 description 9
- 230000006870 function Effects 0.000 description 6
- 238000006073 displacement reaction Methods 0.000 description 5
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009432 framing Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003245 working effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0006—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format
- H04L1/0007—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format by modifying the frame length
Landscapes
- Engineering & Computer Science (AREA)
- Quality & Reliability (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
A parsing method applied to a receiving side of a DS-1 frame, the method comprising the steps of: and receiving data from the DS-1PHY, and transmitting the obtained data to a programmable logic array (FPGA) for correlation processing to obtain a frame header position of the DS-1 frame. And resolving each time slot of the obtained DS-1 frame according to a frame format specified by an ITU-T G.704 protocol.
Description
Technical field
The invention belongs to the PDH communications field, be specifically related to DS-1 frame receiver side analytic method, and realize the chip, UE, instrument etc. of said function.
Background technology
DS-1 transmission system is early stage PDH communication system, and it is compounded in 24 railway digital voice channels in the IA High Speed Channel of a 1.544Mb/s by the principle of time-division multiplex.The frame format of compound is by ITU-T G.704 standard definition.It comprises 24 DS0 (64kbps) time slots, numbers from 1 to 24, each time slot 8bit, altogether 192bit position.The basic frame of DS-1 frame also comprises a F bit (framing bit), as frame lock bit, represents that present frame terminates the beginning with next frame.Therefore a complete DS-1 frame comprises 1 frame lock bit and 24 time slots totally 193 bits, and this code stream is serial code stream, and previous frame and next frame are closely connected does not have space, as shown in Figure 4.DS-1 frame is resolved and is relied on DS multi-frame to parse frame synchronization sequence, thus orients frame lock bit.
ITU-T is standard definition two kinds of DS-1 frame multiple connection modes G.704, are respectively SF frame and ESF frame.
SF frame format is as table one:
Table one
ESF frame format is as table two:
Table two
DS-1 receiver side analytic method is namely in one group of serial sequence, and the multi-frame form G.704 specified according to ITU-T extracts F bit sequence, thus location DS-1 frame.In brief, if 24 F bits that can extract wherein meet the multi-frame sequence that G.704 ITU-T specifies, then think and can locate DS-1 frame.According to ITU-T G.704,24 F bit sequences of SF frame are: 1000_1101_1100_1000_1101_1100, ESF frame 24 bit sequences are: xxx0_xxx0_xxx1_xxx0_xxx1_xxx1, wherein x represents arbitrary value.
Because DS-1 frame only relies on this 1 bit to be used as frame alignment, current existing scheme major part is based on traversal search, consuming time longer.
Summary of the invention
The object of the invention is to solve problem longer due to the parsing time adopting tradition solution frame method to bring in DS-1 receiver, the invention provides a kind of method of fast resolving DS-1 frame.
Provided by the inventionly be applicable to DS-1 frame receiver side fast resolving method, comprise following steps:
1st, the signal of telecommunication in line side is converted to the serial digital sequence of logic side after the PHY process of line side, and transfers to programmable logic array (FPGA).By programmable logic array (FPGA), the Serial No. obtained being stored in RAM, in order to reach the object of quick-searching DS-1 frame, following process being done to RAM:
1.1st, to arrange RAM be address bus bit wide is 13 bits.
1.2nd, high 5 bits are as the base address of each basic Frame storage, and according to ITU-T standard regulation, DS-1 multi-frame is up to 24 frames, therefore chooses the base address of 5 bits as basic frame, meets:
2
5>24。
1.3rd, low 8 bits are as the memory address of basic each bit of frame, and according to ITU-T standard regulation, the basic frame of DS-1 is 193 bits, meets:
2
8>193。
Mode of operation is as follows, arranges a counter, and low 8 bit each clock cycle of address, from adding, make zero during counter counts to 193, namely makes zero during a complete DS-1 frame.And high 5 bits add 1 simultaneously, by that analogy.Rely on such storage mode, obtain the storage array that is similar to matrix.Each row of matrix are a basic frame of DS-1, and every a line of matrix is then the combination of the bit of different DS-1 frame same positions.By the control to address ram, read RAM according to the row of matrix.Mode of operation is as follows: arrange a counter, and when reading RAM, from adding, least-significant byte remains unchanged high 5 of address, when counter counts to 24, then represents and have read a line.If read the next line of matrix, then the least-significant byte controlling address ram adds 1.
2nd, by carrying out parallel traversal search to RAM, obtain the X of DS-1 frame, Y-coordinate;
Parallel traversal search method is that the RAM of 193 row obtained by the 1st step is divided into 5 intervals, by the characteristic sequence of 5 search engine parallel search compound DS-1 frames, to reach the object shortening search time, and finally finds the sequence of compound standard in a matrix.
Build sequence search circuit by FPGA, searching method is as follows:
2.1st, read RAM by row, if the sequences match of 24 bit values obtained and ITU-T standard definition, then retain current location; If do not mated with the sequence of ITU-T standard definition, then shifting function is carried out to 24 bit values read.Still there is no after 24 times if be shifted that the match is successful, then read next line data, so repeatedly, until travel through whole 193 row data.
2.2nd, in order to acceleration detection process, adopt parallel search mode.According to above-mentioned Cleaning Principle, coupling 193x24=4632 time is needed under limiting case, in order to the match is successful at short notice, 193 row data are divided into 5 regions of search, each interval parallel search, if the match is successful in search, then retain current line position (Y-axis position), column position (X-axis position), carries out duplicate acknowledgment operation to follow-up DS-1 multi-frame, to prevent random bearer service data by chance identical with the sequence of standard definition.If follow-up multi-frame is at same position, still the match is successful, then think that DS-1 multi-frame detects successfully.The number of times of duplicate acknowledgment can carry out different settings according to different load patterns, until find line position and a column position accurately.
3rd, utilize the X obtained, Y-coordinate extracts DS-1 frame sequence.Transmission form due to DS-1 frame is continuous and end to end, and the starting point therefore writing RAM in the 1st step is random selecting, and system does not also know the starting point of random selecting and the side-play amount of DS-1 frame multi-frame head.So namely the object of this step utilizes the X obtained in the 2nd step, Y-coordinate value obtains the write starting point of RAM and the side-play amount of DS-1 frame multi-frame head.Specific operation process is:
3.1 arrange a counter in FPGA, and this counter clear when first time write RAM time, then often writes this counter of 1 bit and add 1, until write 193 bits, namely this counter O reset during a DS-1 frame frame length, and so forth.The object of this counter is the relative position of the starting point of record random selecting.
3.2 obtain matrix X, the coordinate figure of Y in the 2nd step.By the definition before us, the line number of X representing matrix, the distance of this line number and the first row represents the starting point of random selecting and the side-play amount of the starting point of multi-frame in a DS-1 frame, and this value is less than 193; The columns of Y representing matrix, the distance of this columns and first row represents the number of the starting point of random selecting and the starting point DS-1 frame apart of multi-frame, and this value is less than 24; As from the foregoing: the position D of the starting point of the original position distance write RAM of DS-1 multi-frame is:
D＝Y×193+X。
Advantage of the present invention and beneficial effect:
The present invention passes through matrix form storage mode by data stored in RAM in programmable logic array (FPGA), and employing parallel search method accelerates DS-1 frame testing process.
Accompanying drawing illustrates:
Fig. 1 is DS-1 frame detection system block schematic illustration;
Fig. 2 is the signal flow graph that DS-1 frame detects;
Fig. 3 is that RAM matrix form stores schematic diagram;
Fig. 4 is DS-1 frame code stream schematic diagram;
Fig. 5 is search routine schematic diagram;
Fig. 6 demarcates DS-1 multi-frame starting point schematic diagram by matrix coordinate point;
Fig. 7 writes RAM and emulates schematic diagram;
Fig. 8 reads RAM and emulates schematic diagram;
Fig. 9 is shifted and mates emulation schematic diagram;
Figure 10 coordinate extracts frame head emulation schematic diagram.
Embodiment
Below in conjunction with accompanying drawing and example, describe technical scheme of the present invention in detail.All the elements of the present invention realize all in FPGA, and FPGA model is the XC6SLX45 of the Spartan6 series of Xilinx.In order to realize all details of the present invention in limited resource, on algorithm of the present invention under the prerequisite not affecting performance, carry out there is suitable simplification.
1st, obtain DS-1 frame code stream through PHY, stream rate is 1.544Mhz.FPGA inside adopts and is stored in RAM by the code stream obtained according to matrix form storage means with road clock, and under the consideration of comprehensive resources and performance, this programme adopts width to be 1, and the degree of depth is that the block RAM of 8192 is as storage medium.Clock is write using this line clock and 1.544Mhz clock as RAM.A DS-1 multi-frame is made up of 24 DS-1 frames, and each DS-1 frame is made up of 193bit, therefore arranges two counters at FPGA, and counter 1 calculates the number of each bit in DS-1 single frames, and counter 2 calculates the number of DS-1 frame.Counter 1 is zero after meter to 193, and represent and be filled with a DS-1 frame, unison counter 2 adds 1, so repeatedly until be filled with 24 DS-1 frames.The simulation waveform of FPGA is shown in Fig. 7, and writing clock is line clock, and when writing the first frame, a write address high position is 0, and low level adds 1, and when writing the second frame, high 5 add 1, and low level zero is again from adding, and in figure, address is that 16 systems represent.Finally can obtain storage array as shown in Figure 3.This matrix column is determined by the least-significant byte of address ram, and the row of this matrix is determined by high 5 of address ram.Citing, A1 in figure, 1 is first row the first row, and address is 13 ' b0_0000_0000_0000 (FPGA counts from 0), A2,1 is the second row first row, address is 13 ' b0_0000_0000_0001, A3, and 2 is the third line secondary series, address is 13 ' b0_0010_0000_0001, by that analogy.
In write operation process, the position of first point in whole DS-1 multi-frame of write is random, and namely we do not know this which frame in multi-frame, do not know that this point is which bit of 193 bits in DS-1 frame yet.Although this position in frame is random, in FPGA, need the position of this point to record.Method is for arranging a counter, and with this point for starting point, counter is 0, and whenever this counter of data of coming in is from adding 1, when filling it up with a DS-1 multi-frame, namely after 193x24 bit, this counter clear does from adding again, and so forth.With this counter coordinate the most, its objective is the position of the point of record first write RAM, as the reference coordinate calculating frame head.How operation below finds the start position of DS-1 multi-frame from sequence by explaining, the coordinate that subsequent operation obtains is the relative displacement of this coordinate.
Have an other road clock in this programme FPGA as system clock, clock frequency is 60Mhz, and this programme reads clock using this clock as RAM.According to matrix form storage means, the data in RAM are read by row, and deliver to match search circuit.The process read is as follows, and arrange a counter, a line due to matrix has 24, therefore resets after this counter counts to 24, represents a line that have read matrix.Mention in previous step, this matrix column is determined by the least-significant byte of address ram, and the row of this matrix is determined by high 5 of address ram.Therefore address control method is, keep the least-significant byte of address constant, namely row remain unchanged, and high 5 are carried out from add operation, count and reset after 24, represent and have read a line 24 bits.If read next line, then the least-significant byte of address adds 1.For reading the emulation schematic diagram of the first row in Fig. 8, wherein reading clock is system clock, reads address least-significant byte constant, and high 5 add certainly, and in figure, address is that 16 systems represent.
The bit of the same position of 24 DS-1 frames that what a line 24bit 2nd, read in previous step represented is.So-called same position refers to and to offset relative to the position of frame lock bit (F bit).Therefore 24 bits obtained can be compared with the DS-1 sequence head that ITU-TG.704 defines.Owing to can not determine which DS-1 frame is first frame in multi-frame, need to carry out shifting function in comparison procedure.Identifying code is:
assign a[23:0]＝{b[22:0],b[23]}；
Wherein b is the sequence before displacement, and a is the sequence after displacement.If the sequence read from RAM is not mated with the sequence of standard definition, then need to carry out shifting function, comparison again after displacement.If be shifted after 24 times still cannot with the sequences match of standard definition, then illustrate and do not comprise DS-1 frame head in this line, need the next line reading RAM to compare.
If at multi-shift, repeatedly obtain matching sequence after line feed operation, then the line number of current reading is the Y value of matrix, and the number of times of displacement is the X value of matrix, and the coordinate of this matching sequence is: (X, Y).In fig .9, S_shift_line_data is the data read from RAM, and these data carry out a shifting function in each clock cycle, if the sequence that G.704 sequence obtained and ITU-T define is identical, then by correlating markings position 1.In figure, when
S_shift_line_data＝＝24’b000110111001_000110111001
Time, S_head_flag_sf puts 1, shows SF frame sequence head to be detected.Obtain the coordinate of current location, S_sync_pos_x, S_sync_pos_y show X-coordinate and the Y-coordinate of current location respectively simultaneously, and the coordinate of X is the coordinate of 90, Y is here 1.
Still need to carry out duplicate acknowledgment operation after obtaining the DS-1 sequence head that G.704 ITU-T define.Because the business code flow of DS-1 frame carrying is random, the situation that may run into is that the sequence that random code stream forms is by chance identical with the sequence of standard definition, so then can cause erroneous judgement.Therefore need record matching coordinate after coupling, carry out repeated matching by after storage RAM refresh at same position.Still can successful match if repeatedly to repeat relatively, then can think and find DS-1 multi-frame head.The number of times of repeated matching the random degree of reference code shape can carry out different settings.Overall search routine figure as shown in Figure 5.In brief, utilize matrix form storage mode, by row write RAM, read RAM by row, often read and once carry out matching ratio comparatively, if mate unsuccessful, carry out shifting function, and then carry out matching ratio comparatively.If be shifted, 24 rear discoveries still can not the match is successful, then read the next line data in RAM, so repeatedly.If the match is successful, then record current (X, Y) coordinate figure, carry out duplicate acknowledgment operation.
Parallel search circuit is more, and the speed of search is faster, but the resource taken is also more, and this programme comprehensive resources considers employing five groups of match search circuit parallel search.Five groups of match search circuit difference searching matrix formulas store 0th ~ 39 row, 40 ~ 79 row, 80 ~ 119 row, 120 ~ 159 row, 160 ~ 193 row of RAM.If search out the DS-1 sequence head that G.704 ITU-T defines, carry out duplicate acknowledgment operation.If confirm successfully, then preserve current X, Y-coordinate value stops other match search circuit workings simultaneously.After adopting five groups of parallel search circuit, every group searching circuit searches at most 40 row data, can accelerate the process of match search, complete coupling at short notice.In the limiting case, namely find matching sequence when reading 193 row, then the method for this parallel search will than fast 5 times of traversal search line by line.
3rd, by the X that match search electric circuit inspection arrives, Y-coordinate value is demarcated as the original position of DS-1 multi-frame.Scaling method is as follows, in figure 6, supposes that (3, the 4) position shown in figure is the matching sequence coordinate figure obtained, namely
X＝3，
Y＝4，
Owing to have recorded the position of write starting point in step one, then in the serial sequence of whole DS-1 multi-frame, the position D of the starting point of the original position distance write RAM of DS-1 multi-frame is:
D＝Y×193+X。
The method of such acquisition DS-1 multi-frame initial point position is as follows: in FPGA, arrange a counter, when the position of first step write starting point, this counter is 0, do from add operation whenever FPGA receives this counter of bit, when the value of this counter equals the moment of D, the bit that FPGA receives is then the starting point of whole DS-1 multi-frame.In the simulation waveform of Figure 10, S_frame_cnt is frame count, and from 0 to 192, altogether 193bit, i.e. a complete DS-1 frame, S_frame_num is a frame counting number, and sign has how many DS-1 frames.Work as S_frame_num=0, be first data of write RAM during S_frame_cnt=0, the counter of S_frame_cnt and S_frame_num composition is above-mentioned reference coordinate simultaneously.We have known that in previous step the coordinate of X-axis is 90, and Y-axis coordinate is 1, and namely the position of distance first write point distance 1 DS-1 frame 90 bit is DS-1 multi-frame head, and O_t1_data_pulse is the mark of this position.
Because the frame length of each DS-1 frame is fixed as 193 bits, therefore with this multi-frame original position for basic point, every the starting point that 193 bits are next DS-1 frame, and so forth, the F bit in DS-1 frame can be located from the DS-1 code stream of input, and the position of multi-frame head, thus reach the object of resolving each time slot.
Claims (4)
1. be applicable to a DS-1 frame receiver side analytic method, it is characterized in that described method comprises the steps:
1st, the signal of telecommunication in line side is converted to the serial digital sequence of logic side after the PHY process of line side, and transfers to programmable logic array (FPGA), in FPGA, DS-1 frame is stored in RAM with a matrix type;
2nd, by carrying out parallel traversal search to RAM, obtain the X of DS-1 frame, Y-coordinate;
3rd, utilize the X obtained, Y-coordinate extracts DS-1 frame sequence.
2. method according to claim 1, is characterized in that the RAM in the 1st step need do following process:
1.1st, to arrange RAM be address bus bit wide is 13 bits;
1.2nd, high 5 bits are as the base address of each basic Frame storage;
1.3rd, low 8 bits are as the memory address of basic each bit of frame;
Mode of operation is as follows, arranges a counter, and low 8 bit each clock cycle of address, from adding, make zero during counter counts to complete DS-1 frame length, zero when namely counting up to 193; And high 5 bits add 1 simultaneously, by that analogy; Rely on such storage mode, obtain the storage array that is similar to matrix; Each row of matrix are a basic frame of DS-1, and every a line of matrix is then the combination of the bit of different DS-1 frame same position.
3. method according to claim 2, it is characterized in that the parallel traversal search method described in the 2nd step is that the RAM of 193 row obtained by the 1st step is divided into 5 intervals, by the characteristic sequence of 5 search engine parallel search compound DS-1 frames, the corresponding region of search of each search engine, to reach the object shortening search time, and finally find the sequence of compound standard in a matrix.
4. method according to claim 1, the coordinate extraction method that it is characterized in that described in the 3rd step is the starting point that the starting position coordinates of the composite standard sequence the 2nd step obtained is demarcated as DS-1 multi-frame, transfers to rear end time slot parsing module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510227749.4A CN104935405B (en) | 2015-05-06 | 2015-05-06 | Method suitable for DS-1 frame receiving side analysis |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510227749.4A CN104935405B (en) | 2015-05-06 | 2015-05-06 | Method suitable for DS-1 frame receiving side analysis |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104935405A true CN104935405A (en) | 2015-09-23 |
| CN104935405B CN104935405B (en) | 2018-08-10 |
Family
ID=54122389
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510227749.4A Active CN104935405B (en) | 2015-05-06 | 2015-05-06 | Method suitable for DS-1 frame receiving side analysis |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104935405B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1184387A (en) * | 1996-11-29 | 1998-06-10 | 富士通株式会社 | Reception pointer processing apparatus in SDH transmission system |
| CN1206153A (en) * | 1997-07-07 | 1999-01-27 | 三星电子株式会社 | Method and device for reducing jitter or drift of ATM and PDH network interconnection |
| CN1588818A (en) * | 2004-08-18 | 2005-03-02 | 北京首信股份有限公司 | Method and device for realizing master and spare unit convertion on exchange port of exchanger |
| CN1612516A (en) * | 2003-10-31 | 2005-05-04 | 上海贝尔阿尔卡特股份有限公司 | Automatic selector of clock source for synchronous digital series system |
| WO2008004196A2 (en) * | 2006-07-04 | 2008-01-10 | Vastech Sa (Pty) Limited | Gateway for use in an electronic communications recording system |
| CN101919186A (en) * | 2008-01-15 | 2010-12-15 | 爱立信电话股份有限公司 | Telecom multiplexer for variable rate composite bit stream |
-
2015
- 2015-05-06 CN CN201510227749.4A patent/CN104935405B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1184387A (en) * | 1996-11-29 | 1998-06-10 | 富士通株式会社 | Reception pointer processing apparatus in SDH transmission system |
| CN1206153A (en) * | 1997-07-07 | 1999-01-27 | 三星电子株式会社 | Method and device for reducing jitter or drift of ATM and PDH network interconnection |
| CN1612516A (en) * | 2003-10-31 | 2005-05-04 | 上海贝尔阿尔卡特股份有限公司 | Automatic selector of clock source for synchronous digital series system |
| CN1588818A (en) * | 2004-08-18 | 2005-03-02 | 北京首信股份有限公司 | Method and device for realizing master and spare unit convertion on exchange port of exchanger |
| WO2008004196A2 (en) * | 2006-07-04 | 2008-01-10 | Vastech Sa (Pty) Limited | Gateway for use in an electronic communications recording system |
| CN101919186A (en) * | 2008-01-15 | 2010-12-15 | 爱立信电话股份有限公司 | Telecom multiplexer for variable rate composite bit stream |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104935405B (en) | 2018-08-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110224775B (en) | Method, device and equipment for determining time information | |
| CN104270567B (en) | High-precision synchronous multi-channel image acquisition system and time synchronization method thereof | |
| CN109669899B (en) | Method for adaptively adjusting serial port communication baud rate and serial port device | |
| CN101336003B (en) | Method for generating leader sequence and method for determining cyclic shift step length | |
| CN108880723B (en) | Clock synchronization method and device | |
| EP3955528B1 (en) | Delay measurement method, system and storage medium | |
| CN103220122B (en) | A kind of variable element high-speed parallel frame synchronizer | |
| CN102752098B (en) | For the measurement of error code method synchronous based on pseudo-random code sequence of communication system | |
| CN105406937A (en) | Frame synchronization method and apparatus | |
| CN111193567B (en) | Time synchronization method, equipment and storage medium | |
| CN211046907U (en) | High-speed serial-parallel conversion interface word synchronous circuit for FPGA chip | |
| WO2020010742A1 (en) | Single-line transmission method, chip, and communication system | |
| CN114422063B (en) | A Time Stamp Pulse Synchronization Method | |
| CN101834685A (en) | 1588 message extraction processing method and equipment | |
| CN101534154A (en) | Error code test method of burst optical signal receiving module | |
| CN104935405A (en) | Method suitable for DS-1 frame receiving side analysis | |
| CN104954113A (en) | Multichannel data transmission method and system | |
| CN105279128A (en) | Method and device for synchronizing parallel data | |
| CN101119172B (en) | Parallel overhead extracting method and device in optical synchronization digital transmission system | |
| CN105071832B (en) | A kind of high-speed frequency-hopping synchronous method for being independent of external clock benchmark | |
| CN102437991B (en) | Method and device for synchronizing GFP (Generic Framing Procedure) bit streams | |
| CN100542079C (en) | Method and device for searching synchronization code in network communication | |
| CN111181677B (en) | Time synchronization method, network device and storage medium | |
| CN100446483C (en) | A method and device for generating a correlation sequence code | |
| CN103684735A (en) | Synchronous method of distributed device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: Binhai New Area 300392 Binhai New Area of Tianjin Huayuan Industrial Zone (outer ring) three Hai Tai Road No. 8 innovation Patentee after: Tianjin Deli Instrument Equipment Co.,Ltd. Address before: Binhai New Area 300392 Binhai New Area of Tianjin Huayuan Industrial Zone (outer ring) three Hai Tai Road No. 8 innovation Patentee before: Tianjin Deviser Electronics Instrument Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220721 Address after: 300392 3519, zone B, No. 8, Haitai Chuangxin Third Road, Huayuan Industrial Zone (outside the ring), high tech Zone, Binhai New Area, Tianjin Patentee after: Deli photoelectric technology (Tianjin) Co.,Ltd. Address before: 300392 No. 8, Haitai Chuangxin Third Road, Huayuan Industrial Zone (outside the ring), Binhai high tech Zone, Binhai New Area, Tianjin Patentee before: Tianjin Deli Instrument Equipment Co.,Ltd. |