CN104935299B - The rest-set flip-flop of silicon substrate low-leakage current clamped beam floating gate - Google Patents

Abstract

The RS flip-flop of the silicon-based low-leakage current solid-supported beam floating gate of the present invention is composed of two NAND gates, each of which is composed of two NMOS transistors (10) connected in series with a resistor R, wherein the first NAND gate One input terminal of the NOT gate (①) is connected to the output terminal of the second NAND gate (②), and one input terminal of the second NAND gate (②) is connected to the output terminal of the first NAND gate (①), and the first input The signal (R) is connected to the fixed beam floating grid (4) of the NMOS transistor (10) in the first NAND gate (①), and the second input signal (S) is connected to the NMOS transistor (10) in the second NAND gate (②). ) fixed-beam floating gate (4); the entire RS flip-flop is fabricated on a P-type Si substrate (1), and four NMOS transistors (10) have a fixed-beam floating gate (4) that can float up and down. The RS The flip-flop is not only simple in structure and easy to integrate, but also has the advantages of low gate leakage current and low DC power consumption.

Description

Silicon-Based Low Leakage Current Immobilized Beam Floating Gate RS Flip-Flop

technical field

The invention provides an RS flip-flop of a silicon-based low-leakage current solid-supported beam floating gate, which belongs to the technical field of micro-electro-mechanical systems (MEMS).

Background technique

With the continuous development of digital integrated circuits, the application of various digital logic devices is also increasing. Among them, the RS flip-flop is the most basic circuit that constitutes the storage unit of various sequential circuits in digital circuits. Its characteristic is that it has 0 and 1 Once the state is determined, it can maintain itself, that is, store a binary code for a long time, and it may change only when an external signal acts. This RS flip-flop is not only simple in structure and easy to integrate, but also fast and stable. OK, so it is widely used in various digital integrated circuits. However, with the continuous increase of the integrated circuit scale and the continuous improvement of the integration level, it has been found that the power consumption problem of the RS flip-flop has become increasingly prominent. In some chips with small size and high integration level, the problem of high power consumption has been It is difficult to solve. The reason is mainly because of the problem of the MOS switch that constitutes the RS flip-flop. Due to the small thickness of the gate oxide layer of the traditional MOS device, there is a non-negligible leakage current in the gate, and this leakage current is It is an important reason for the increase of power consumption, so how to reduce the leakage current in the RS flip-flop is a big challenge that people are currently facing.

With the development of MEMS technology, a MOS device with a MEMS fixed beam structure provides the possibility to reduce the power consumption of the RS flip-flop. This unique MEMS fixed beam structure can effectively reduce the gate DC leakage of the MOS device. current, thereby greatly reducing the power consumption of the entire RS flip-flop. The present invention designs an RS flip-flop with a fixed beam grid with extremely small gate leakage current on a Si substrate.

Contents of the invention

Technical problem: the purpose of this invention is to provide a kind of RS flip-flop and preparation method of silicon-based low-leakage current solid-supported beam floating gate. In the basic RS flip-flop, the switch is mainly made of MOS tube, but due to the traditional MOS The thickness of the gate oxide layer of the device is very small, so that a part of electrons can pass through the gate oxide layer, so there is a leakage current in the gate, and it is this part of the gate leakage current that leads to an increase in the DC power consumption of the device, and the present invention is extremely The gate leakage current in the RS flip-flop is effectively reduced, thereby greatly reducing the power consumption of the RS flip-flop.

Technical solution: The RS flip-flop of the silicon-based low-leakage current solid-supported beam floating gate of the present invention is composed of two NAND gates, each of which is composed of two NMOS transistors connected in series with a resistor R, wherein the first NAND gate One input terminal of the NAND gate is connected to the output terminal of the second NAND gate, one input terminal of the second NAND gate is connected to the output terminal of the first NAND gate, and the first input signal is connected to the solid state of the NMOS transistor in the first NAND gate. Beam floating gate, the second input signal is connected to the fixed beam floating gate of the NMOS transistor in the second NAND gate; the entire RS flip-flop is fabricated on a P-type Si substrate, and the four NMOS transistors have fixed beams that can float up and down Floating grid, the fixed beam floating grid is made of Al, the two ends of the fixed beam floating grid are fixed on the anchor area, the middle spans above the gate oxide layer, and there are two pull-down electrodes under the fixed beam floating grid, distributed Between the anchor region and the gate oxide layer, the pull-down electrode is grounded and covered with a silicon nitride dielectric layer. This structure has the great advantages of low leakage current and low power consumption.

The threshold voltages of the four NMOS transistors are designed to be equal, and the pull-down voltage of the fixed-beam floating gate is designed to be equal to the threshold voltage of the NMOS transistor. Only when the voltage between the fixed-beam floating gate and the pull-down electrode of the NMOS transistor is greater than the threshold voltage , the suspended fixed beam floating gate will be pulled down and attached to the gate oxide layer to make the NMOS transistor turn on, otherwise the NMOS transistor will be turned off.

When both the R terminal and the S terminal of the NAND gate are at a high level, the fixed beam floating gate 4 of the NMOS transistor 10 connected to these two ends will be pulled down to make it conduct, but the two input signals output Q and and has no effect, by Q and The controlled NMOS tube is still in the original state, so the state of the trigger remains unchanged; when the R terminal is high and the S terminal is low, the NMOS tube connected to the R terminal is turned on, and the NMOS tube connected to the S terminal is turned on. tube cutoff, so is high, with The NMOS tube connected to the terminal is turned on, so Q outputs a low level, and the state of the flip-flop is stable at a low level; when the R terminal is low and the S terminal is high, the NMOS tube connected to the R terminal is cut off, The NMOS transistor connected to the S terminal is turned on, so Q is high level, and the NMOS transistor connected to the Q terminal is turned on, so output low level, at this time the state of the flip-flop is stable at high level; when the R terminal and S terminal are both low level, the NMOS transistors 10 connected to these two ends are all cut off, so Q and They are all high level. At this time, the RS flip-flop is in an uncertain state that is neither 1 nor 0. Therefore, to make the RS flip-flop work normally, the input signal must comply with the constraint of R+S=1, that is, R is not allowed =S=0.

In the present invention, there are 4 NOMS switch tubes inside the RS flip-flop, all of which have a MEMS fixed-beam floating gate structure. The threshold voltages of these 4 NMOS transistors are designed to be equal, and the pull-down voltage of the fixed-beam grid is designed to be the same as The threshold voltages of the NMOS tubes are equal. The fixed beam grid of the NMOS transistor is suspended above the gate oxide layer through the anchor region, rather than attached to the gate oxide layer. Since the pull-down electrode is grounded, only when the voltage between the fixed beam grid and the pull-down electrode is greater than the threshold voltage At this time, the fixed beam grid will be adsorbed and attached to the oxide layer, so that the NMOS transistor will be turned on, otherwise the NMOS transistor will be cut off. It is precisely because of the fixed beam structure of the NMOS transistor that the DC leakage current of the gate is obtained. A very good suppression, thereby reducing the power consumption of the RS flip-flop.

Beneficial effects: the silicon-based low-leakage current fixed-beam floating gate RS flip-flop of the present invention has a floating fixed-beam gate, which not only has a simple structure and is easy to integrate, but also greatly reduces the DC leakage current of the gate , thereby greatly reducing the power consumption of the RS flip-flop and improving the working stability of the RS flip-flop.

Description of drawings

Fig. 1 is the schematic diagram of the RS flip-flop of the silicon-based low-leakage current solid-supported beam floating gate of the present invention,

Fig. 2 is the internal schematic diagram of the RS flip-flop of the silicon-based low-leakage current solid-supported beam floating gate of the present invention,

3 is a top view of the RS flip-flop of the silicon-based low-leakage current solid-supported beam floating gate of the present invention,

Fig. 4 is a cross-sectional view of the P-P' direction of the RS flip-flop of the silicon-based low-leakage current solid-supported beam floating gate in Fig. 3,

Fig. 5 is a cross-sectional view along the A-A' direction of the RS flip-flop of the silicon-based low-leakage current solid-supported beam floating gate in Fig. 3 .

The figure includes: P-type Si substrate 1, anchor region 2, NMOS tube active region 3, fixed beam floating gate 4, pull-down electrode 5, silicon nitride dielectric layer 6, contact hole 7, lead 8, gate oxide layer 9, NMOS tube 10, resistor R.

detailed description

The RS flip-flop of the silicon-based low-leakage current solid-supported beam floating gate of the present invention is mainly composed of two NAND gates, wherein the output terminal Q of the first NAND gate ① and an input terminal of the second NAND gate ② connected, and the output of the second NAND gate ② It is connected to one input terminal of the first NAND gate ①, the other input terminal of the first NAND gate ① is the R terminal (clear terminal), and the other input terminal of the second NAND gate ② is the S terminal (set Bit end), this structure is the most basic RS flip-flop. The internal structures of these two NAND gates are exactly the same, they are composed of two NMOS switch tubes and a pull-up resistor R connected in series, and a point between the NMOS tube and the resistor is taken as the output terminal.

The entire RS flip-flop is fabricated based on Si substrate, the most important feature of which is that the NMOS switch tube that constitutes the RS flip-flop has a fixed beam gate suspended above the oxide layer, instead of being attached like a traditional NMOS device. On the oxide layer, the fixed beam is made of Al, and there are two pull-down electrodes under the fixed beam grid. The pull-down electrode is grounded, and the signal is loaded on the fixed beam grid, through the absorption and pull-down electrode. The function is to control the turn-on and turn-off of the MOS switch.

From the perspective of a single NAND gate, when the floating gates of the two NMOS fixed beams are loaded with a high level '1', the floating gate of the NMOS is absorbed by the pull-down electrode and attached to the gate due to the grounding of the pull-down electrode. On the oxide layer, both NMOS transistors are turned on at this time, so the entire circuit forms a path, and the output terminal is low level '0' due to the voltage division effect of the resistor R; when one of the NMOS fixed-beam floating gates is loaded When a high level '1' is applied to the floating gate of another NMOS and a low level '0' is applied, one NMOS transistor is turned on and the other NMOS transistor is turned off. The entire circuit does not form a path, so the output terminal is High level '1'; when the floating gates of the two NMOS fixed beams are loaded with low level '0', the floating gates of the two NMOSs will not be pulled down, so that both NMOS transistors are cut off State, the whole circuit does not form a path, so the output terminal is a high level '1', which is the working principle of a single NAND gate. From the perspective of the entire RS flip-flop, when both the R terminal and the S terminal are high level '1', the two input signal pairs output Q and No effect, so the state of the flip-flop remains unchanged; when the R terminal is a high level '1', and the S terminal is a low level '0', the output terminal Q is a low level '0', is high level '1', at this time the state of the flip-flop is low level '0'; when the R terminal is low level '0' and the S terminal is high level '1', the output terminal Q is high level '1', is low level '0', at this time the state of the flip-flop is high level '1'; when the R terminal and S terminal are both low level '0', the Q terminal and The output of the terminal is all high level '1', at this time the flip-flop is in an uncertain state of neither 1 nor 0, so to make the flip-flop work normally, the input signal must obey the constraint condition of R+S=1, that is R=S=0 is not allowed.

The RS flip-flop of the silicon-based low-leakage current solid-supported beam floating gate of the present invention is based on the P-type Si substrate 1, and the four switches are all composed of NMOS transistors, and the gates of the four NMOS transistors are suspended. The fixed beam floating gate 4 above the gate oxide layer 9 is made of Al, the fixed beam floating gate 4 is fixed by the anchor region 2, and two pull-down electrodes are deposited below the fixed beam floating gate 4 5. They are distributed between the anchor region 2 and the gate oxide layer 9, covered with a silicon nitride dielectric layer 6, the pull-down electrode is grounded, and these four uniquely structured NMOS transistors 10 are formed together with two resistors R the RS flip-flop.

The preparation method of the RS flip-flop of the silicon-based low-leakage current solid-supported beam floating gate of the present invention is as follows:

1) Prepare the P-type Si substrate;

2) Carry out the initial oxidation of the P-type Si substrate to form a layer of _SiO2 ;

3) Remove the surface oxide layer and provide a flat silicon surface;

4) Bottom oxygen growth;

5) Apply photoresist and remove the photoresist at the pull-down electrode;

6) Deposit a layer of polysilicon with a thickness of about 0.3 μm;

7) Remove the remaining photoresist and polysilicon on the photoresist to form a pull-down electrode;

8) Deposit silicon nitride and photoetch silicon nitride, retain the silicon nitride dielectric layer on the pull-down electrode and the silicon nitride in the active area;

9) Field oxidation;

10) Remove the bottom oxide layer and silicon nitride in the active area;

11) Perform gate oxidation and oxidize the active area to grow an oxide layer;

12) Apply photoresist to remove the photoresist at the anchor area of the fixed beam;

13) Deposit a layer of polysilicon with a thickness of about 0.3 μm;

14) Remove the remaining photoresist and the polysilicon on the photoresist to form a polysilicon anchor region;

15) Deposit and lithography polyimide sacrificial layer: coat a 1.6 μm thick polyimide sacrificial layer on the Si substrate, and it is required to fill the pits; sacrificial layer under corbels;

16) Evaporate and deposit Al to form a solid support beam pattern;

17) Apply photoresist and keep the photoresist above the fixed beam grid;

18) Anti-etch Al to form a floating grid with fixed beams;

19) Coating photoresist, photoetching out phosphorus injection holes, injecting phosphorus, and forming the active area of NMOS tube;

20) Photolithography and etching of contact holes and leads;

21) Release the polyimide sacrificial layer to form a suspended fixed-beam floating grid;

The present invention differs in that:

The four switches constituting the RS flip-flop are all composed of the same NMOS transistor. The gate of the NMOS transistor is not attached to the gate oxide layer like the traditional MOS transistor, but a fixed beam suspended above the oxide layer. structure, the threshold voltages of the two NMOS transistors are designed to be equal, and the pull-down voltage of the fixed-beam grid is designed to be the threshold voltage of the MOS transistor. When the voltage between the fixed-beam grid and the pull-down electrode is greater than the threshold voltage of the NMOS transistor, the fixed-beam The gate will be pulled down to the gate oxide layer, so that the NMOS transistor is turned on, otherwise the NMOS transistor is turned off. Due to the existence of the fixed-beam floating gate of the NMOS transistor, the gate leakage current is greatly reduced, and the DC power consumption is further reduced.

A structure that satisfies the above conditions is regarded as the silicon-based low-leakage current fixed-beam floating gate RS flip-flop of the present invention.

The symbol and truth table of the RS flip-flop of the silicon-based low-leakage current solid-supported beam floating gate of FIG. 1 of the present invention:

Claims (2)

1. a kind of rest-set flip-flop of silicon substrate low-leakage current clamped beam floating gate, it is characterised in that the rest-set flip-flop is by two NAND gates Constitute, each NAND gate is composed in series by two NMOS tubes (10) with a resistance R, wherein, the one of the first NAND gate (1.) The output end of individual input the second NAND gate of termination (2.), an input the first NAND gate of termination (1.) of the second NAND gate (2.) Output end, the first input signal (R) connects the clamped beam floating gate (4) of NMOS tube (10) in the first NAND gate (1.), the second input Signal (S) connects the clamped beam floating gate (4) of NMOS tube (10) in the second NAND gate (2.)；Whole rest-set flip-flop is served as a contrast based on p-type Si On bottom (1) make, four NMOS tubes (10) with the clamped beam floating gate (4) that can be fluctuated, the clamped beam floating gate (4) Made by Al, the two ends of clamped beam floating gate (4) are fixed in anchor area (2), it is middle across in gate oxide (9) top, solid There are two pull-down electrodes (5) strutbeam floating gate (4) lower section, is distributed between anchor area (2) and gate oxide (9), pull-down electrode (5) It is ground connection, silicon nitride medium layer (6) is also covered with thereon, this structure has the great advantages of low-leakage current, low-power consumption.

2. the rest-set flip-flop of silicon substrate low-leakage current clamped beam floating gate according to claim 1, it is characterised in that four The threshold voltage designs of NMOS tube (10) are equal, and the actuation voltage of clamped beam floating gate (4) is designed as and NMOS tube (10) Threshold voltage it is equal, only when the voltage between the clamped beam floating gate (4) and pull-down electrode (5) of NMOS tube (10) be more than threshold value During voltage, the clamped beam floating gate (4) of suspension drop-down can just be labelled to and NMOS tube (10) conducting is caused on gate oxide (9), otherwise NMOS tube (10) is just ended.