CN104932947B - A kind of fence synchronous method and equipment - Google Patents

Abstract

The invention discloses a kind of fence synchronous method and equipment, are related to the communications field, solve in the case where number of threads increases, due to having the problem of chip process performance of multinuclear or many-core processor declines caused by access bottleneck.Concrete scheme is：First processor core determines that currently processed multi-threaded program goes to predetermined fence synchronous point；The first processor core is any one in all processor cores that chip includes；Target fence sychronisation is determined according to the corresponding fence mark of the predetermined fence synchronous point；Fence synchronization message is sent to the target fence sychronisation；The number of synchronous multi-threaded program is identified and participated in the fence synchronization message comprising the fence.During the present invention is for fence synchronization.

Description

A fence synchronization method and device

technical field

The present invention relates to the communication field, in particular to a fence synchronization method and equipment.

Background technique

Traditional single-core processors usually increase the main frequency of the processor by using superscalar and pipeline processing technology to achieve the purpose of improving processor performance, but the increase of main frequency will lead to increased power consumption of the processor, and will lead to The heat dissipation of the processor is not good. Moreover, with the continuous development of semiconductor technology, the number of transistors that can be integrated on the chip is gradually increasing. In order to improve the performance of the processor and reduce the power consumption of the processor at the same time, and to make the processor have good heat dissipation, the architecture designer proposes Multi-core or many-core processors with thread-level coarse-grained parallelism.

Since multi-core or many-core processors use multi-threads for data processing, barrier synchronization is required to ensure the correct propagation of data among multiple thread programs and the correctness of thread program execution semantics. It is very important for multi-core or many-core processors. In the prior art, barrier synchronization is realized by setting a synchronization management device on the chip. The specific implementation process is: in a chip with multi-core or many-core processors, when a thread program processed by a certain processor core executes When the predetermined synchronization point is reached, the processor core sends a notification message to the synchronization management device to notify that the thread program processed by itself has been executed to the predetermined synchronization point, so that the synchronization management device counts whether all the threads in the thread program participating in the synchronization The programs have all been executed to a predetermined synchronization point, and when all thread programs have been executed to a predetermined synchronization point, an instruction to continue execution is sent to the processor core corresponding to each thread program in all thread programs participating in the synchronization, So that all processor cores continue to process the thread program.

There are at least the following problems in the prior art: since only one synchronization management device is set on the chip, in a chip with multi-core or many-core processors, when the thread program processed by the processor core is executed to a predetermined synchronization point, all It is necessary to send a notification message to the same synchronization management device to notify that the thread program it handles has been executed to a predetermined synchronization point. In this way, when the number of threads increases, a serious access bottleneck will be generated, resulting in the coordination of multiple thread programs. Execution is slower, resulting in reduced processing performance on chips with multi-core or many-core processors.

Contents of the invention

The invention provides a barrier synchronization method and device, which solves the problem of the chip processing performance degradation caused by access bottlenecks caused by multi-core or many-core processors when the number of threads increases.

To achieve the above object, the present invention adopts the following technical solutions:

The first aspect of the present invention provides a barrier synchronization method, which is applied to a chip with a multi-core or many-core processor, and at least two barrier synchronization devices are provided on the chip, and the method includes:

The first processor core determines that the currently processed thread program executes to a predetermined fence synchronization point; the first processor core is any one of all processor cores included in the chip;

determining a target barrier synchronization device according to the barrier identification corresponding to the predetermined barrier synchronization point;

Sending a barrier synchronization message to the target barrier synchronization device; the barrier synchronization message includes the barrier identifier and the number of thread programs participating in the synchronization.

With reference to the first aspect, in a possible implementation manner, the determining the target barrier synchronization device according to the barrier identifier corresponding to the predetermined barrier synchronization point includes:

According to the barrier identification corresponding to the predetermined barrier synchronization point, the target barrier synchronization device is determined according to a preset rule; the preset rule includes a mapping relationship between a barrier identification and a barrier synchronization device.

With reference to the first aspect and the foregoing possible implementation manner, in another possible implementation manner, after sending the barrier synchronization message to the target barrier synchronization device, the method further includes:

Suspend processing of the currently processed thread program and enter a waiting state.

In combination with the first aspect and the above possible implementation manner, in another possible implementation manner, after suspending the processing of the currently processed thread program and entering the waiting state, further include:

receiving an acknowledgment message sent by the target fence synchronization device; the acknowledgment message is used to notify the first processor core to continue processing the currently processed thread program;

Continue to process the currently processed thread program.

The second aspect of the present invention provides a barrier synchronization method, which is applied to a chip with a multi-core or many-core processor, and at least two barrier synchronization devices are provided on the chip, and the method includes:

The target barrier synchronization device receives a barrier synchronization message sent by the first processor core; the barrier synchronization message is sent by the first processor core when it is determined that the currently processed thread program has been executed to a predetermined barrier synchronization point, and the first A processor core is any one of all processor cores included in the chip, and the fence synchronization message includes the fence identification corresponding to the predetermined fence synchronization point and the number of thread programs participating in the synchronization; the target The fence synchronization device is a fence synchronization device for processing the fence synchronization message sent by the processor core corresponding to the predetermined fence synchronization point;

Add 1 to the count value of the count field contained in the first queue according to the fence identifier corresponding to the predetermined fence synchronization point; the first queue is used to identify all thread program states participating in synchronization corresponding to the fence identifier Queue; the first queue includes the fence identifier, queue status, and count fields.

With reference to the second aspect, in a possible implementation manner, before adding 1 to the count value of the count field included in the first queue according to the fence identifier, the method further includes:

judging whether the first queue exists;

When the first queue does not exist, create the first queue, and update the status of the queue to a usage status.

With reference to the second aspect and the foregoing possible implementation manner, in another possible implementation manner, the first queue further includes identification information of a processor core corresponding to a thread program that has been executed to the predetermined fence synchronization point;

After receiving the fence synchronization message sent by the first processor core, the method further includes:

Add the identification information of the first processor core to the first queue.

With reference to the second aspect and the foregoing possible implementation manner, in another possible implementation manner, before adding the identification information of the first processor core to the first queue, the method further includes:

Judging whether the number of identification information of processor cores corresponding to the thread program that has been executed to the predetermined fence synchronization point is less than a preset threshold; the preset threshold is less than or equal to the maximum number of threads supported by the chip;

When it is determined that the number of identification information of processor cores corresponding to the thread program that has been executed to the predetermined barrier synchronization point is less than the preset threshold, performing the step of adding the identification information of the first processor core added to the first queue.

In combination with the second aspect and the foregoing possible implementation manner, another possible implementation manner further includes:

When it is determined that the number of identification information of processor cores corresponding to the thread program that has been executed to the predetermined barrier synchronization point is not less than the preset threshold, the identification information of the first processor core is saved to in memory.

With reference to the second aspect and the above possible implementation manner, in another possible implementation manner, the first queue further includes a function for identifying whether each thread program in all thread programs participating in the synchronization is executed to the predetermined A bit sequence of the barrier synchronization point, where each bit in the bit sequence has a mapping relationship with the identification information of the processor core;

After receiving the fence synchronization message sent by the first processor core, the method further includes:

updating the bit corresponding to the identification information of the first processor core from a first identification to a second identification; the first identification is used to identify that the thread program processed by the processor core has not been executed to the predetermined barrier A synchronization point, the second identifier is used to identify that the thread program processed by the processor core has been executed to the predetermined fence synchronization point.

With reference to the second aspect and the above possible implementation manner, in another possible implementation manner, after adding 1 to the count value of the count field contained in the first queue according to the barrier identifier, the method further includes:

judging whether the count value of the count field is equal to the number of thread programs participating in the synchronization;

When the count value of the count field is equal to the number of the thread programs participating in the synchronization, obtain the identification information of the processor core corresponding to each of the thread programs participating in the synchronization among all the thread programs participating in the synchronization;

Send a confirmation message to the processor core corresponding to each of the thread programs participating in the synchronization according to the identification information of the processor core corresponding to each thread program participating in the synchronization among all the thread programs participating in the synchronization; The confirmation message is used to notify the processor core to continue processing the thread program that needs to be processed by itself.

In combination with the second aspect and the above possible implementation manner, in another possible implementation manner, the obtaining the identification information of the processor core corresponding to each thread program participating in the synchronization among all the thread programs participating in the synchronization includes:

The identification information of the processor core corresponding to each of the thread programs participating in the synchronization among all the thread programs participating in the synchronization is obtained from the first queue.

In combination with the second aspect and the above possible implementation manner, in another possible implementation manner, the obtaining the identification information of the processor core corresponding to each thread program participating in the synchronization among all the thread programs participating in the synchronization includes:

The identification information of the processor core corresponding to each of the thread programs participating in the synchronization among all the thread programs participating in the synchronization is obtained from the first queue and the memory.

A third aspect of the present invention provides a first processor core, which is applied to a chip with a multi-core or many-core processor, and at least two barrier synchronization devices are provided on the chip, and the first processor core, include:

The first determining unit is configured to determine that the currently processed thread program executes to a predetermined fence synchronization point; the first processor core is any one of all processor cores included in the chip;

The second determining unit is configured to determine a target barrier synchronization device according to the barrier identification corresponding to the predetermined barrier synchronization point;

A sending unit, configured to send a barrier synchronization message to the target barrier synchronization device obtained by the second determining unit; the barrier synchronization message includes the barrier identifier and the number of thread programs participating in the synchronization.

With reference to the third aspect, in a possible implementation manner, the second determining unit is specifically configured to:

According to the barrier identification corresponding to the predetermined barrier synchronization point, the target barrier synchronization device is determined according to a preset rule; the preset rule includes a mapping relationship between a barrier identification and a barrier synchronization device.

In combination with the third aspect and the above possible implementation manner, another possible implementation manner further includes:

The first processing unit is configured to suspend the processing of the currently processed thread program and enter a waiting state after the sending unit sends the fence synchronization message to the target fence synchronization device.

In combination with the third aspect and the above possible implementation manner, another possible implementation manner further includes:

The receiving unit is configured to receive a confirmation message sent by the target barrier synchronization device after the first processing unit suspends the processing of the currently processed thread program and enters a waiting state; the confirmation message is used to notify the The first processor core continues to process the currently processed thread program;

The second processing unit is configured to continue processing the currently processed thread program.

According to the fourth aspect of the present invention, a target barrier synchronization device is provided, which is applied to a chip with a multi-core or many-core processor, and at least two barrier synchronization devices are provided on the chip, and the target barrier synchronization device includes:

The receiving unit is configured to receive a barrier synchronization message sent by the first processor core; the barrier synchronization message is sent by the first processor core when it is determined that the currently processed thread program has executed to a predetermined barrier synchronization point, and the The first processor core is any one of all processor cores included in the chip, and the barrier synchronization message includes the barrier identification corresponding to the predetermined barrier synchronization point and the number of thread programs participating in the synchronization; The target barrier synchronization device is a barrier synchronization device for processing a barrier synchronization message sent by the processor core corresponding to the predetermined barrier synchronization point;

A processing unit, configured to add 1 to the count value of the count field contained in the first queue according to the barrier identifier corresponding to the predetermined barrier synchronization point contained in the barrier synchronization message obtained by the receiving unit; The queue is a queue corresponding to the fence identifier and used to identify the program states of all threads participating in the synchronization; the first queue includes the fence identifier, queue status, and the count field.

In combination with the fourth aspect, in a possible implementation manner, it also includes:

A judging unit, configured to judge whether the first queue exists before the processing unit adds 1 to the count value of the count field contained in the first queue according to the barrier identifier;

An update unit is created, configured to create the first queue and update the state of the queue to an in-use state when the judging unit obtains that the first queue does not exist.

With reference to the fourth aspect and the foregoing possible implementation manner, in another possible implementation manner, the first queue further includes identification information of processor cores corresponding to thread programs that have been executed to the predetermined fence synchronization point;

The target fence synchronization device also includes:

The adding unit is configured to add the identification information of the first processor core to the first queue after the receiving unit receives the fence synchronization message sent by the first processor core.

In combination with the fourth aspect and the above possible implementation, in another possible implementation,

The judging unit is further configured to judge the thread program that has been executed to the predetermined fence synchronization point before the adding unit adds the identification information of the first processor core to the first queue Whether the number of identification information of the corresponding processor core is less than a preset threshold; the preset threshold is less than or equal to the maximum number of threads supported by the chip;

The adding unit is specifically configured to, when the judging unit determines that the number of identification information of the processor core corresponding to the thread program that has been executed to the predetermined barrier synchronization point is less than the preset threshold, add the Add the identification information of the first processor core to the first queue.

In combination with the fourth aspect and the foregoing possible implementation manners, another possible implementation manner further includes:

A saving unit, configured to store the number of identification information of the processor core corresponding to the thread program that has been executed to the predetermined fence synchronization point by the judging unit is not less than the preset threshold The identification information of a processor core is stored in the memory.

With reference to the fourth aspect and the above possible implementation manner, in another possible implementation manner, the first queue further includes a function for identifying whether each thread program in all thread programs participating in the synchronization is executed to the predetermined A bit sequence of the barrier synchronization point, where each bit in the bit sequence has a mapping relationship with the identification information of the processor core;

The target fence synchronization device also includes:

An updating unit, configured to update the bit corresponding to the identification information of the first processor core from the first identification to the second identification after the receiving unit receives the fence synchronization message sent by the first processor core; The first flag is used to identify that the thread program processed by the processor core has not been executed to the predetermined barrier synchronization point, and the second flag is used to identify that the thread program processed by the processor core has been executed to the predetermined barrier synchronization point.

In combination with the fourth aspect and the above possible implementation, in another possible implementation,

The judgment unit is further configured to judge whether the count value of the count field is equal to the thread program participating in the synchronization after the processing unit adds 1 to the count value of the count field included in the first queue according to the barrier identifier the number of

The target fence synchronization device also includes:

An acquisition unit, configured to acquire the processor corresponding to each thread program participating in synchronization among all thread programs participating in synchronization when the count value of the counting field obtained by the judging unit is equal to the number of thread programs participating in synchronization Nuclear identification information;

The sending unit is configured to, according to the identification information of the processor core corresponding to each of the thread programs participating in the synchronization obtained by the acquiring unit, send to each of the thread programs participating in the synchronization The processor core corresponding to the thread program sends an acknowledgment message; the acknowledgment message is used to notify the processor core to continue processing the thread program that needs to be processed by itself.

In combination with the fourth aspect and the foregoing possible implementation manner, in another possible implementation manner, the acquiring unit is specifically configured to:

The identification information of the processor core corresponding to each of the thread programs participating in the synchronization among all the thread programs participating in the synchronization is obtained from the first queue.

In combination with the fourth aspect and the foregoing possible implementation manner, in another possible implementation manner, the acquiring unit is specifically configured to:

The identification information of the processor core corresponding to each of the thread programs participating in the synchronization among all the thread programs participating in the synchronization is obtained from the first queue and the memory.

In the barrier synchronization method and device provided by the present invention, when the first processor core determines that the currently processed thread program has been executed to a predetermined barrier synchronization point, it determines the target barrier synchronization device according to the barrier identification corresponding to the predetermined barrier synchronization point, and then sends to the barrier synchronization device The target barrier synchronization device sends a barrier synchronization message, and by determining the target barrier synchronization device for processing its own barrier synchronization message according to the predetermined barrier synchronization point, different barrier synchronization points can be mapped to different barrier synchronization devices, so that when the number of threads increases In this way, access bottlenecks are avoided, and the processing performance of chips with multi-core or many-core processors is improved.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings without any creative effort.

FIG. 1 is a flow chart of a barrier synchronization method provided in Embodiment 1 of the present invention;

FIG. 2 is a flow chart of a fence synchronization method provided in Embodiment 2 of the present invention;

3 is a schematic structural diagram of a chip with multi-core or many-core processors provided with four barrier synchronization devices according to Embodiment 3 of the present invention;

FIG. 4 is a flowchart of a column synchronization method provided by Embodiment 3 of the present invention;

FIG. 5 is a schematic diagram of the composition of a first processor core provided by Embodiment 4 of the present invention;

FIG. 6 is a schematic composition diagram of another first processor core provided by Embodiment 4 of the present invention;

FIG. 7 is a schematic diagram of the composition of a target fence synchronization device provided in Embodiment 5 of the present invention;

FIG. 8 is a schematic diagram of the composition of another target fence synchronization device provided in Embodiment 5 of the present invention;

FIG. 9 is a schematic diagram of the composition of a fence synchronization device provided in Embodiment 6 of the present invention;

FIG. 10 is a schematic diagram of a barrier synchronization device provided by Embodiment 7 of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

Additionally, the terms "system" and "network" are often used herein interchangeably. The term "and/or" in this article is just an association relationship describing associated objects, which means that there can be three relationships, for example, A and/or B can mean: A exists alone, A and B exist simultaneously, and there exists alone B these three situations. In addition, the character "/" in this article generally indicates that the contextual objects are an "or" relationship.

Example 1

Embodiment 1 of the present invention provides a barrier synchronization method, which is applied to a chip with a multi-core or many-core processor. At least two barrier synchronization devices are provided on the chip. As shown in FIG. 1, the method may include:

101. The first processor core determines that a currently processed thread program is executed to a predetermined barrier synchronization point. Wherein, the first processor core is any one of all processor cores included in the chip.

102. The first processor core determines a target barrier synchronization device according to a barrier identifier corresponding to a predetermined barrier synchronization point.

Wherein, the fence synchronization method of the embodiment of the present invention is applied to a chip with a multi-core or many-core processor, and at least two fence synchronization devices are arranged on the chip, when any processor core in all processor cores, That is, when the first processor core determines that the thread program currently being processed has been executed to a predetermined fence synchronization point, the first processor core first determines the target from at least two fence synchronization devices included in the chip according to the fence identification corresponding to the fence synchronization point. Fence synchronization device.

103. The first processor core sends a fence synchronization message to the target fence synchronization device.

Wherein, the barrier synchronization message includes the barrier identifier and the number of thread programs participating in the synchronization. The first processor core sends a message for fence synchronization to the determined target fence synchronization device.

In the fence synchronization method provided by the embodiment of the present invention, when the first processor core determines that the currently processed thread program has been executed to a predetermined fence synchronization point, it determines the target fence synchronization device according to the fence identification corresponding to the predetermined fence synchronization point, and then sends the The target barrier synchronization device sends a barrier synchronization message, and by determining the target barrier synchronization device for processing its own barrier synchronization message according to the predetermined barrier synchronization point, different barrier synchronization points can be mapped to different barrier synchronization devices, so that when the number of threads increases In this way, access bottlenecks are avoided, and the processing performance of chips with multi-core or many-core processors is improved.

Moreover, compared with the software method, the hardware method is used to realize fence synchronization, which has a higher processing speed, and further improves the processing performance of chips with multi-core or many-core processors.

Example 2

Embodiment 2 of the present invention provides a barrier synchronization method, which is applied to a chip with a multi-core or many-core processor. At least two barrier synchronization devices are provided on the chip. As shown in FIG. 2, the method may include:

201. The target barrier synchronization device receives a barrier synchronization message sent by the first processor core.

Wherein, the barrier synchronization message is sent by the first processor core when it is determined that the currently processed thread program executes to a predetermined barrier synchronization point, the first processor core is any one of all processor cores contained in the chip, and the barrier synchronization message contains the fence identifier corresponding to the fence synchronization point and the number of thread programs participating in the synchronization, and the target fence synchronization device is a fence synchronization device for processing the fence synchronization message sent by the processor core corresponding to the predetermined fence synchronization point.

202. The target fence synchronization device adds 1 to the count value of the count field included in the first queue according to the fence identifier.

Wherein, the first queue is a queue corresponding to the fence identifier and used to identify the program states of all threads participating in the synchronization, and the first queue includes fence identifier, queue status, and count fields.

Specifically, when the first processor core determines that the thread program currently being processed by itself has been executed to a predetermined barrier synchronization point, it first determines the target barrier synchronization device according to the barrier identification corresponding to the predetermined barrier synchronization point, and then sends a message to the target barrier synchronization device barrier synchronization message, the target barrier synchronization device can receive the barrier synchronization message sent by the first processor core for notifying itself that the thread program for processing has been executed to a predetermined barrier synchronization point, and according to the barrier synchronization message received The included fence identifier adds 1 to the count value of the count field included in the first queue corresponding to the fence identifier, so as to record the number of thread programs that have been executed to the predetermined barrier synchronization point among the thread programs participating in the synchronization.

In the fence synchronization method provided by the embodiment of the present invention, the target fence synchronization device receives the fence synchronization message sent by the first processor core, and according to the fence identifier contained in the fence synchronization message Add 1 to the count value, so as to record the number of thread programs that have been executed to the predetermined barrier synchronization point among the thread programs participating in the synchronization, and determine the target barrier synchronization for processing its own barrier synchronization message according to the predetermined barrier synchronization point through the first processor core The device enables different barrier synchronization points to be mapped to different barrier synchronization devices, thereby avoiding access bottlenecks when the number of threads increases, and improving the processing performance of chips with multi-core or many-core processors.

Moreover, compared with the software method, the hardware method is used to realize fence synchronization, which has a higher processing speed, and further improves the processing performance of chips with multi-core or many-core processors.

Example 3

Embodiment 3 of the present invention provides a barrier synchronization method, which is applied to a chip with a multi-core or many-core processor. At least two barrier synchronization devices are provided on the chip, and the at least two barrier synchronization devices are distributed in the network on chip. In different positions, as shown in FIG. 3 , an exemplary structure diagram of a chip with multi-core or many-core processors provided with four barrier synchronization devices provided by the embodiment of the present invention is shown. As shown in Figure 4, the fence synchronization method provided by the embodiment of the present invention may include:

301. The first processor core determines that a currently processed thread program is executed to a predetermined fence synchronization point.

Wherein, the first processor core is any one of all processor cores included in the chip.

302. The first processor core determines a target barrier synchronization device according to a barrier identifier corresponding to a predetermined barrier synchronization point.

Wherein, after the first processor core determines that the thread program currently processed by itself has been executed to a predetermined barrier synchronization point, the first processor core selects from at least two Among the barrier synchronization devices, a barrier synchronization device for processing its own barrier synchronization message is determined, that is, a target barrier synchronization device is determined.

In a possible implementation of the embodiment of the present invention, the first processor core determines the target fence synchronization device according to the fence identifier corresponding to the predetermined fence synchronization point. The barrier synchronization device is determined from the at least two barrier synchronization devices included in the chip according to a preset rule, and the preset rule may include a mapping relationship between the barrier ID and the barrier synchronization device. For example, taking the round-robin method as an example, assuming that the number of fence synchronization points is more than the number of fence synchronization devices, and the chip contains a total of 4 fence synchronization devices, the processor core can use the fence identification corresponding to its own fence synchronization point , determine the fence synchronization device that processes its own fence synchronization message in a round-robin manner. For example, the fence identification corresponding to a certain fence synchronization point is 7, and the chip contains 4 fence synchronization devices. At this time, the processor core can identify the fence After dividing by 4 and taking the remainder, the number of the barrier synchronization device for processing its own barrier synchronization message can be obtained as 3, even if the target barrier identifier can be determined.

It should be noted that in the embodiment of the present invention, the method of determining the target barrier synchronization device in a round-robin manner is only a possible implementation method provided by the embodiment of the present invention. Specifically, how to The identification and determination of the target barrier synchronization device may be determined according to the requirements of the actual application scenario, and this embodiment of the present invention does not specifically limit it here.

It should be noted that, in a possible implementation of the embodiment of the present invention, the preset rule may also be that each processor core corresponds to a barrier synchronization device, or each bank of the shared cache may correspond to a barrier synchronization device, the The preset rules may be pre-set and agreed, and this embodiment of the present invention does not specifically limit the preset rules.

303. The first processor core sends a fence synchronization message to the target fence synchronization device.

Wherein, the barrier synchronization message includes the barrier identifier and the number of thread programs participating in the synchronization. After the first processor core determines the target fence synchronization device according to the fence identification corresponding to the predetermined fence synchronization point, it can send to the target fence synchronization device a fence for notifying itself that the thread program for processing has been executed to the predetermined fence synchronization point Synchronize messages.

It should be noted that the barrier synchronization message can be notified to the target barrier synchronization device by adding a synchronization command to the processor core. This embodiment of the present invention does not make specific limitations here, and the synchronization command can be non-preemptive or preemptive style.

304. The first processor core suspends processing the currently processed thread program, and enters a waiting state.

Wherein, after the first processor core sends the barrier synchronization message to the target barrier synchronization device, the first processor core may suspend the processing of the currently processed thread program and enter a waiting state, so as to achieve the purpose of barrier synchronization.

305. The target barrier synchronization device receives the barrier synchronization message sent by the first processor core.

Wherein, the barrier synchronization message is sent by the first processor core when it is determined that the currently processed thread program executes to a predetermined barrier synchronization point, and the barrier synchronization message includes the barrier identification corresponding to the predetermined barrier synchronization point and the ID of the thread program participating in the synchronization Number; the target fence synchronization device is a fence synchronization device for processing a fence synchronization message sent by a processor core corresponding to a predetermined fence synchronization point.

Wherein, when the first processor core determines that the thread program processed by itself has been executed to a predetermined barrier synchronization point, and after determining the target barrier synchronization device, it can send a barrier synchronization message to the target barrier synchronization device. At this time, the target barrier synchronization device will A fence synchronization message sent by the first processor core may be received, including the fence identifier corresponding to the predetermined fence synchronization point and the number of thread programs participating in the synchronization.

306. The target fence synchronization device judges whether there is a first queue.

Wherein, after the target barrier synchronization device receives the barrier synchronization message sent by the first processor core, it can determine whether there is a barrier corresponding to the barrier synchronization point corresponding to the barrier synchronization point contained in the barrier synchronization message. The first queue, the first queue is a queue corresponding to the fence identifier used to identify the program states of all threads participating in the synchronization, and the first queue includes a fence identifier, a queue state and a count field, wherein the fence identifier is used for The barrier synchronization point is uniquely identified. The queue status is used to identify the status of the queue, which can be in use or idle. The count field is used to record the number of thread programs that have been executed to the predetermined barrier synchronization point.

It should be noted that, in the embodiment of the present invention, a barrier synchronization device can maintain at least one queue for identifying the program states of all threads participating in the same synchronization, so that the scalability of the barrier synchronization method provided by the embodiment of the present invention Well, making it better suited for chips with multi-core processors, and even better for chips with many-core processors.

307. When the first queue does not exist, the target fence synchronization device creates the first queue, and updates the status of the queue to the usage status.

Wherein, when the target fence synchronization device determines that there is no first queue corresponding to the fence identifier, it may create a first queue containing the fence identifier, and update the queue status of the first queue from the idle state to the used state.

It should be noted that, if the target fence synchronization device determines that there is a first queue corresponding to the fence identifier, step 308 is directly executed.

308. The target fence synchronization device adds 1 to the count value of the count field included in the first queue according to the fence identifier corresponding to the predetermined fence synchronization point.

It should be noted that, in a possible implementation manner in the embodiment of the present invention, when each processor core corresponds to a barrier synchronization device, when the target barrier synchronization device receives the barrier synchronization message sent by the first processor core, it may Step 308 is directly executed without judging whether there is a first queue corresponding to the fence identifier.

In a possible implementation of the embodiment of the present invention, further, the first queue also includes the identification information of the processor core corresponding to the thread program that has been executed to the predetermined barrier synchronization point, and the target barrier synchronization device according to After the fence identifier corresponding to the predetermined fence synchronization point adds 1 to the count value of the count field contained in the first queue, the following steps 309 to 311 may be executed.

309 . The target barrier synchronization device judges whether the number of identification information of processor cores corresponding to the thread programs that have been executed to a predetermined barrier synchronization point is less than a preset threshold.

Wherein, the preset threshold is less than or equal to the maximum number of threads supported by the chip. After the target barrier device adds 1 to the count value of the count field contained in the first queue according to the barrier identifier corresponding to the predetermined barrier synchronization point in the received barrier synchronization message, it can continue to judge that the predetermined barrier synchronization point has been executed. Whether the number of identification information of the processor core corresponding to the thread program is less than a preset threshold, when it is determined that the number of identification information of the processor core corresponding to the thread program that has been executed to a predetermined barrier synchronization point is less than the preset threshold, Execute the following step 310; when it is determined that the number of identification information of processor cores corresponding to the thread program that has been executed to the predetermined barrier synchronization point is not less than the preset threshold, execute the following step 311.

310. The target fence synchronization apparatus adds the identification information of the first processor core to the first queue.

311. The target fence synchronization device saves the identification information of the first processor core into a memory.

It should be noted that, in the embodiment of the present invention, when the preset threshold is less than the maximum number of threads supported by the chip, when the number of identification information of the processor core corresponding to the thread program that has been executed to the predetermined fence synchronization point When not less than the preset threshold, by storing the identification information of the first processor core in the memory, the space for storing the identification information corresponding to the processor core in the target fence synchronization device is saved.

In another possible implementation of the embodiment of the present invention, further, the first queue further includes a bit sequence for identifying whether each thread program in all thread programs participating in the synchronization is executed to a predetermined barrier synchronization point , and each bit in the bit sequence has a mapping relationship with the identification information of the processor core, then the target fence synchronization device adds the count value of the count field contained in the first queue to 1, the following step 312 can be performed.

312. The target fence synchronization apparatus updates bits corresponding to the identification information of the first processor core from the first identification to the second identification.

Wherein, the first identification is used to identify that the thread program processed by the processor core has not been executed to a predetermined barrier synchronization point, and the second identification is used to indicate that the thread program processed by the processor core has been executed to a predetermined barrier synchronization point. For example, the first identification is 0, and the second identification is 1. When creating the first queue, each bit in the bit sequence that has a mapping relationship with the identification information of the processor core is set to 0. When the target fence synchronization device receives When the fence synchronization message of the first processor core is received, the bit corresponding to the identification information of the first processor core can be updated from 0 to 1, so as to indicate that the thread program processed by the first processor core has been executed to the predetermined Fence synchronization point.

It should be noted that, in a possible implementation of the embodiment of the present invention, a bit sequence is used to identify whether the thread program participating in the synchronization is executed to a predetermined barrier synchronization point, thereby saving the target barrier synchronization device from storing identification information corresponding to the processor core. Space.

313. The target fence synchronization device judges whether the count value in the count field is equal to the number of thread programs participating in synchronization.

Wherein, after the target barrier device adds 1 to the count value of the count field contained in the first queue, and saves the identification information of the first processor core or updates the bit corresponding to the identification information of the first processor core, the target barrier The synchronization device can judge whether all the thread programs participating in the synchronization have been executed to the predetermined barrier synchronization point, that is, judge whether the count value of the count field contained in the first queue is equal to the number of the thread programs participating in the synchronization.

314. When the count value in the count field is equal to the number of thread programs participating in synchronization, the target barrier synchronization device acquires identification information of the processor core corresponding to each thread program participating in synchronization among all thread programs participating in synchronization.

Wherein, in a possible implementation manner, when the target barrier device uses a bit sequence to identify whether the thread program participating in the synchronization has been executed to a predetermined barrier synchronization point, since each bit in the bit sequence is related to the processor core There is a mapping relationship between the identification information. At this time, the target barrier synchronization device obtains the identification information of the processor core corresponding to each thread program participating in the synchronization among all the thread programs participating in the synchronization. Specifically, it may be: obtain all the synchronization information from the first queue. The identification information of the processor core corresponding to each thread program participating in the synchronization in the thread program.

In another possible implementation, when the target fence device uses the identification information of the recorded processor core to identify whether the thread program participating in the synchronization has been executed to the predetermined fence synchronization point, at this time the target fence synchronization device obtains all the synchronization The identification information of the processor cores corresponding to each of the thread programs participating in the synchronization in the thread program specifically may be: obtaining the identification of the processor cores corresponding to each of the thread programs participating in the synchronization in all the thread programs participating in the synchronization from the first queue information, or obtain the identification information of the processor core corresponding to each thread program participating in the synchronization among all the thread programs participating in the synchronization from the first queue and the memory.

It should be noted that, when the count value of the count field is not equal to the number of thread programs participating in synchronization, it means that some thread programs in the thread programs participating in synchronization have not been executed to the predetermined barrier synchronization point, and the target barrier synchronization device at this time The barrier synchronization messages sent by processor cores corresponding to other thread programs participating in synchronization may be continuously received until the count value in the count field is equal to the number of thread programs participating in synchronization and step 314 is executed.

315. The target barrier synchronization device sends a message to the processor core corresponding to each thread program participating in synchronization among all thread programs participating in synchronization according to the identification information of the processor core corresponding to each thread program participating in synchronization among all thread programs participating in synchronization. Send a confirmation message.

Wherein, after the target barrier synchronization device obtains the identification information of the processor core corresponding to each thread program participating in synchronization among all the thread programs participating in synchronization, it can The identification information of the corresponding processor core sends a confirmation message for notifying the processor core that it can continue to process the thread program that needs to be processed by itself to the processor core corresponding to each thread program participating in the synchronization among all the thread programs participating in the synchronization.

316. The first processor core receives the confirmation message sent by the target barrier synchronization device.

317. The first processor core continues to process the currently processed thread program.

Wherein, after the first processor core receives the confirmation message sent by the target barrier synchronization device, it can know that all the thread programs participating in the synchronization have been executed to the predetermined barrier synchronization point, and the first processor core can continue to process at this time. The currently processing thread program.

In the fence synchronization method provided by the embodiment of the present invention, the target fence synchronization device receives the fence synchronization message sent by the first processor core, and according to the fence identifier contained in the fence synchronization message Add 1 to the count value, so as to record the number of thread programs that have been executed to the predetermined barrier synchronization point among the thread programs participating in the synchronization, and determine the target barrier synchronization for processing its own barrier synchronization message according to the predetermined barrier synchronization point through the first processor core The device enables different barrier synchronization points to be mapped to different barrier synchronization devices, thereby avoiding access bottlenecks when the number of threads increases, and improving the processing performance of chips with multi-core or many-core processors.

Moreover, the hardware method is used to realize barrier synchronization, which has a higher processing speed compared with the software method, and further improves the processing performance of chips with multi-core or many-core processors, and a barrier synchronization device can be maintained by at least A queue used to identify the program state of all threads participating in the same synchronization, making it scalable.

Example 4

Embodiment 4 of the present invention provides a first processor core, which is applied to a chip with a multi-core or many-core processor. At least two barrier synchronization devices are provided on the chip. The first processor core is shown in the figure As shown in FIG. 5 , the first processor core may include: a first determining unit 41 , a second determining unit 42 , and a sending unit 43 .

The first determining unit 41 is configured to determine that the currently processed thread program executes to a predetermined fence synchronization point; the first processor core is any one of all processor cores included in the chip.

The second determining unit 42 is configured to determine a target barrier synchronization device according to the barrier identifier corresponding to the predetermined barrier synchronization point.

The sending unit 43 is configured to send a fence synchronization message to the target fence synchronization device obtained by the second determining unit 42; the fence synchronization message includes the fence identifier and the number of thread programs participating in the synchronization.

In the embodiment of the present invention, further optionally, the second determining unit 42 is specifically configured to determine the target barrier synchronization device according to preset rules according to the barrier identifier corresponding to the predetermined barrier synchronization point; The preset rules include a mapping relationship between barrier identifiers and barrier synchronization devices.

In the embodiment of the present invention, further optionally, as shown in FIG. 6 , the first processor core may further include: a first processing unit 44 .

The first processing unit 44 is configured to, after the sending unit 43 sends a fence synchronization message to the target fence synchronization device, suspend processing of the currently processed thread program and enter a waiting state.

In the embodiment of the present invention, further optionally, the first processor core may further include: a receiving unit 45 and a second processing unit 46 .

The receiving unit 45 is configured to receive a confirmation message sent by the target barrier synchronization device after the first processing unit 44 suspends the processing of the currently processed thread program and enters a waiting state; the confirmation message is used to notify The first processor core continues to process the currently processed thread program.

The second processing unit 46 is configured to continue processing the currently processed thread program.

It should be noted that, for the specific description of the functional modules in the first processor core provided in the embodiment of the present invention, reference may be made to the specific description of the corresponding content in the method embodiment, and details are not described in detail in the embodiment of the present invention.

In the first processor core provided in the embodiment of the present invention, when the first processor core determines that the currently processed thread program has been executed to a predetermined fence synchronization point, it determines the target fence synchronization device according to the fence identifier corresponding to the predetermined fence synchronization point, and then Send a barrier synchronization message to the target barrier synchronization device, and determine the target barrier synchronization device that processes its own barrier synchronization message according to the predetermined barrier synchronization point, so that different barrier synchronization points can be mapped to different barrier synchronization devices, thereby increasing the number of threads In the case of an access bottleneck, the processing performance of a chip with a multi-core or many-core processor is improved.

Moreover, the hardware method is used to realize barrier synchronization, which has a higher processing speed compared with the software method, and further improves the processing performance of chips with multi-core or many-core processors, and a barrier synchronization device can be maintained by at least A queue used to identify the program state of all threads participating in the same synchronization, making it scalable.

Example 5

Embodiment 5 of the present invention provides a target barrier synchronization device, which is applied to a chip with a multi-core or many-core processor. At least two barrier synchronization devices are provided on the chip. The target barrier synchronization device is shown in FIG. 7 As shown, the target fence synchronization device may include: a receiving unit 51 and a processing unit 52.

The receiving unit 51 is configured to receive a fence synchronization message sent by the first processor core; the fence synchronization message is sent by the first processor core when it is determined that the currently processed thread program executes to a predetermined fence synchronization point, so The first processor core is any one of all processor cores included in the chip, and the barrier synchronization message includes the barrier identification corresponding to the predetermined barrier synchronization point and the number of thread programs participating in the synchronization; The target fence synchronization device is a fence synchronization device for processing a fence synchronization message sent by the processor core corresponding to the predetermined fence synchronization point.

The processing unit 52 is configured to add 1 to the count value of the count field included in the first queue according to the fence identifier corresponding to the predetermined fence synchronization point contained in the fence synchronization message obtained by the receiving unit 51; The first queue is a queue corresponding to the fence identifier and used to identify the program states of all threads participating in the synchronization; the first queue includes the fence identifier, queue status, and the count field.

In the embodiment of the present invention, further optionally, as shown in FIG. 8 , the device for synchronizing the target barrier may further include: a judging unit 53 and a creating and updating unit 54 .

The judging unit 53 is configured to judge whether the first queue exists before the processing unit 52 adds 1 to the count value of the count field included in the first queue according to the barrier identifier.

The creating and updating unit 54 is configured to create the first queue and update the state of the queue to a used state when the judging unit 53 obtains that the first queue does not exist.

In the embodiment of the present invention, further optionally, the first queue further includes identification information of processor cores corresponding to thread programs that have been executed to the predetermined fence synchronization point.

The target fence synchronization device may further include: an adding unit 55 .

The adding unit 55 is configured to add the identification information of the first processor core to the first queue after the receiving unit 51 receives the fence synchronization message sent by the first processor core.

In the embodiment of the present invention, further optionally, the judging unit 53 is further configured to, before the adding unit 55 adds the identification information of the first processor core to the first queue, judge the Whether the number of identification information of processor cores corresponding to the thread programs that have been executed to the predetermined barrier synchronization point is less than a preset threshold; the preset threshold is less than or equal to the maximum number of threads supported by the chip.

The adding unit 55 is specifically configured to, when the judging unit 53 determines that the number of identification information of processor cores corresponding to the thread program that has been executed to the predetermined barrier synchronization point is less than the preset threshold, Add the identification information of the first processor core to the first queue.

In the embodiment of the present invention, further optionally, the target barrier synchronization device may further include: a saving unit 56 .

The saving unit 56 is configured to store the identification information of the processor core corresponding to the thread program that has been executed to the predetermined fence synchronization point when the judging unit 53 is not less than the preset threshold value. The identification information of the first processor core is stored in the memory.

In the embodiment of the present invention, further optionally, the first queue further includes a bit sequence for identifying whether each thread program in all thread programs participating in the synchronization is executed to the predetermined barrier synchronization point, the There is a mapping relationship between each bit in the bit sequence and the identification information of the processor core.

The device for synchronizing the target fence may further include: an updating unit 57 .

An updating unit 57, configured to update the bit corresponding to the identification information of the first processor core from the first identification to the second identification after the receiving unit 51 receives the fence synchronization message sent by the first processor core ; The first identification is used to identify that the thread program processed by the processor core has not been executed to the predetermined barrier synchronization point, and the second identification is used to identify that the thread program processed by the processor core has been executed to the predetermined The fence synchronization point.

In the embodiment of the present invention, further optionally, the judging unit 53 is further configured to judge the Whether the count value in the count field is equal to the number of thread programs participating in the synchronization.

The target fence synchronization device may further include: an acquiring unit 58 and a sending unit 59 .

An acquisition unit 58, configured to acquire the corresponding thread program number of each thread program participating in synchronization among all thread programs participating in synchronization when the count value of the counting field obtained by the judging unit 53 is equal to the number of thread programs participating in synchronization. Identification information of the processor core.

The sending unit 59 is configured to, according to the identification information of the processor core corresponding to each of the thread programs participating in the synchronization obtained by the acquiring unit 58, send to each of the thread programs participating in the synchronization The processor core corresponding to the synchronized thread program sends an acknowledgment message; the acknowledgment message is used to notify the processor core to continue processing the thread program that needs to be processed by itself.

In the embodiment of the present invention, further optionally, the obtaining unit 58 is specifically configured to obtain the processor core corresponding to each thread program participating in synchronization among all thread programs participating in synchronization from the first queue identification information.

In the embodiment of the present invention, further optionally, the obtaining unit 58 is specifically configured to obtain from the first queue and the memory the corresponding The identification information of the processor core.

It should be noted that, for the specific description of the functional modules in the target fence synchronization device provided by the embodiment of the present invention, reference may be made to the specific description of the corresponding content in the method embodiment, and the embodiments of the present invention will not be described in detail here.

The target barrier synchronization device provided by the embodiment of the present invention receives the barrier synchronization message sent by the first processor core, and adds the count value of the count field contained in the first queue corresponding to the barrier identification to the value according to the barrier identification contained in the barrier synchronization message 1, in order to record the number of thread programs that have been executed to the predetermined barrier synchronization point among the thread programs participating in the synchronization, the first processor core determines the target barrier synchronization device for processing its own barrier synchronization message according to the predetermined barrier synchronization point, so that Different barrier synchronization points can be mapped to different barrier synchronization devices, so that when the number of threads increases, access bottlenecks are avoided, and the processing performance of chips with multi-core or many-core processors is improved.

Moreover, the hardware method is used to realize barrier synchronization, which has a higher processing speed compared with the software method, and further improves the processing performance of chips with multi-core or many-core processors, and a barrier synchronization device can be maintained by at least A queue used to identify the program state of all threads participating in the same synchronization, making it scalable.

Example 6

Embodiment 6 of the present invention provides a barrier synchronization device, which is applied to a chip with a multi-core or many-core processor. At least two barrier synchronization devices are provided on the chip. As shown in FIG. 9, the barrier synchronization device can Including: at least one processor core, memory 62, communication interface 63 and bus 64, the at least one processor core, memory 62 and communication interface 63 are connected through the bus 64 and complete mutual communication, wherein:

The bus 64 may be an Industry Standard Architecture (Industry Standard Architecture, ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (Extended Industry Standard Architecture, EISA) bus, etc. The bus 64 can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is used in FIG. 9 , but it does not mean that there is only one bus or one type of bus.

The memory 62 is used for storing executable program codes, and the program codes include computer operation instructions. The memory 62 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one magnetic disk memory.

The processor core may be a central processing unit (Central Processing Unit, CPU), or a specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits configured to implement embodiments of the present invention .

The communication interface 63 is mainly used to implement communication between devices in this embodiment.

Wherein, for any one of the at least one processor core (that is, the first processor core 61 described in the embodiment of the present invention), it is specifically used to perform the following functions:

The first processor core 61 is used to determine that the currently processed thread program executes to a predetermined barrier synchronization point; the first processor core 61 is any one of all processor cores included in the chip; according to the The barrier identification corresponding to the predetermined barrier synchronization point determines the target barrier synchronization device; sends a barrier synchronization message to the target barrier synchronization device; the barrier synchronization message includes the barrier identification and the number of thread programs participating in the synchronization.

In the embodiment of the present invention, further optionally, the first processor core 61 is specifically configured to determine the target barrier synchronization device according to preset rules according to the barrier identifier corresponding to the predetermined barrier synchronization point; The preset rules include a mapping relationship between barrier identifiers and barrier synchronization devices.

In the embodiment of the present invention, further optionally, the first processor core 61 is further configured to suspend the processing of the currently processed thread program after the barrier synchronization message is sent to the target barrier synchronization device processing, enter the waiting state.

In the embodiment of the present invention, further optionally, the first processor core 61 is further configured to receive the target fence synchronization A confirmation message sent by the device; the confirmation message is used to notify the first processor core 61 to continue processing the currently processed thread program; continue to process the currently processed thread program.

It should be noted that, for the specific description of the functional modules in the first processor core provided in the embodiment of the present invention, reference may be made to the specific description of the corresponding content in the method embodiment, and details are not described in detail in the embodiment of the present invention.

In the first processor core provided in the embodiment of the present invention, when the first processor core determines that the currently processed thread program has been executed to a predetermined fence synchronization point, it determines the target fence synchronization device according to the fence identifier corresponding to the predetermined fence synchronization point, and then Send a barrier synchronization message to the target barrier synchronization device, and determine the target barrier synchronization device that processes its own barrier synchronization message according to the predetermined barrier synchronization point, so that different barrier synchronization points can be mapped to different barrier synchronization devices, thereby increasing the number of threads In the case of an access bottleneck, the processing performance of a chip with a multi-core or many-core processor is improved.

Moreover, the hardware method is used to realize barrier synchronization, which has a higher processing speed compared with the software method, and further improves the processing performance of chips with multi-core or many-core processors, and a barrier synchronization device can be maintained by at least A queue used to identify the program state of all threads participating in the same synchronization, making it scalable.

Example 7

Embodiment 7 of the present invention provides a barrier synchronization device, which is applied to a chip with a multi-core or many-core processor. At least two barrier synchronization devices are provided on the chip. As shown in FIG. 10, the barrier synchronization device can Including: at least one processor 71, memory 72, communication interface 73 and bus 74, the at least one processor 71, memory 72 and communication interface 73 are connected through the bus 74 and complete mutual communication, wherein:

The bus 74 may be an ISA bus, a PCI bus, or an EISA bus. The bus 74 can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is used in FIG. 10 , but it does not mean that there is only one bus or one type of bus.

The memory 72 is used for storing executable program codes, and the program codes include computer operation instructions. The memory 72 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one magnetic disk memory.

The processor 71 may be a CPU, or an ASIC, or one or more integrated circuits configured to implement embodiments of the present invention.

The communication interface 73 is mainly used to implement communication between devices in this embodiment.

The processor 71 is configured to execute the executable program code in the memory 72, and is specifically configured to execute the following functions:

The processor 71 is configured to receive a barrier synchronization message sent by the first processor core; the barrier synchronization message is sent by the first processor core when it is determined that the currently processed thread program executes to a predetermined barrier synchronization point , the first processor core is any one of all processor cores included in the chip, and the barrier synchronization message includes the barrier identification corresponding to the predetermined barrier synchronization point and the number of thread programs participating in the synchronization ; Add 1 to the count value of the count field included in the first queue according to the fence identifier corresponding to the predetermined fence synchronization point; the first queue is used to identify all thread program states that participate in synchronization corresponding to the fence identifier The queue; the first queue includes the fence identifier, queue status, and the count field.

In the embodiment of the present invention, further optionally, the processor 71 is further configured to determine whether there is the first queue before adding 1 to the count value of the count field included in the first queue according to the fence identifier. A queue, when the first queue does not exist, create the first queue, and update the state of the queue to the use state.

In the embodiment of the present invention, further optionally, the first queue further includes identification information of processor cores corresponding to thread programs that have been executed to the predetermined fence synchronization point.

The processor 71 is further configured to add the identification information of the first processor core to the first queue after receiving the fence synchronization message sent by the first processor core.

In the embodiment of the present invention, further optionally, the processor 71 is further configured to, before adding the identification information of the first processor core to the first queue, determine that the executed Whether the number of identification information of processor cores corresponding to the thread program to the predetermined barrier synchronization point is less than a preset threshold; the preset threshold is less than or equal to the maximum number of threads supported by the chip, when it is determined that the When the number of identification information of processor cores corresponding to the thread program executed to the predetermined fence synchronization point is less than the preset threshold, performing the adding the identification information of the first processor core to the second in a queue.

In the embodiment of the present invention, further optionally, the processor 71 is further configured to determine that the number of identification information of processor cores corresponding to the thread program that has been executed to the predetermined fence synchronization point is not When the value is less than the preset threshold, the identification information of the first processor core is stored in the memory.

In the embodiment of the present invention, further optionally, the first queue further includes a bit sequence for identifying whether each thread program in all thread programs participating in the synchronization is executed to the predetermined barrier synchronization point, the There is a mapping relationship between each bit in the bit sequence and the identification information of the processor core.

The processor 71 is further configured to, after receiving the fence synchronization message sent by the first processor core, update the bit corresponding to the identification information of the first processor core from the first identification to the second identification ; The first identification is used to identify that the thread program processed by the processor core has not been executed to the predetermined barrier synchronization point, and the second identification is used to identify that the thread program processed by the processor core has been executed to the predetermined The fence synchronization point.

In the embodiment of the present invention, further optionally, the processor 71 is further configured to, after adding 1 to the count value of the count field included in the first queue according to the barrier identifier, determine the value of the count field Whether the count value is equal to the number of thread programs participating in synchronization, and when the count value of the count field is equal to the number of thread programs participating in synchronization, obtain each thread participating in synchronization in all thread programs participating in synchronization The identification information of the processor core corresponding to the program, according to the identification information of the processor core corresponding to each thread program participating in the synchronization in all the thread programs participating in the synchronization, to each thread participating in the synchronization in all the thread programs participating in the synchronization The processor core corresponding to the program sends an acknowledgment message; the acknowledgment message is used to notify the processor core to continue processing the thread program that needs to be processed by itself.

In the embodiment of the present invention, further optionally, the processor 71 is further configured to obtain from the first queue the processor core corresponding to each of the thread programs participating in the synchronization among all the thread programs participating in the synchronization identification information.

In the embodiment of the present invention, further optionally, the processor 71 is further configured to obtain from the first queue and the memory the corresponding The identification information of the processor core.

It should be noted that, for the specific description of the functional modules in the target fence synchronization device provided by the embodiment of the present invention, reference may be made to the specific description of the corresponding content in the method embodiment, and the embodiments of the present invention will not be described in detail here.

The target barrier synchronization device provided by the embodiment of the present invention receives the barrier synchronization message sent by the first processor core, and adds the count value of the count field contained in the first queue corresponding to the barrier identification to the value according to the barrier identification contained in the barrier synchronization message 1, in order to record the number of thread programs that have been executed to the predetermined barrier synchronization point among the thread programs participating in the synchronization, the first processor core determines the target barrier synchronization device for processing its own barrier synchronization message according to the predetermined barrier synchronization point, so that Different barrier synchronization points can be mapped to different barrier synchronization devices, so that when the number of threads increases, access bottlenecks are avoided, and the processing performance of chips with multi-core or many-core processors is improved.

Moreover, the hardware method is used to realize barrier synchronization, which has a higher processing speed compared with the software method, and further improves the processing performance of chips with multi-core or many-core processors, and a barrier synchronization device can be maintained by at least A queue used to identify the program state of all threads participating in the same synchronization, making it scalable.

Through the description of the above embodiments, those skilled in the art can clearly understand that for the convenience and brevity of the description, only the division of the above-mentioned functional modules is used as an example for illustration. In practical applications, the above-mentioned functions can be allocated according to needs It is completed by different functional modules, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. For the specific working process of the device described above, reference may be made to the corresponding process in the foregoing method embodiments, and details are not repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed devices and methods may be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be Incorporation or may be integrated into another device, or some features may be omitted, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.

The unit described as a separate component may or may not be physically separated, and the component displayed as a unit may be one physical unit or multiple physical units, that is, it may be located in one place, or may be distributed to multiple different places . Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

If the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the essence of the technical solution of the present invention or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium. Several instructions are included to make a device (which may be a single-chip microcomputer, a chip, etc.) or a processor (processor) execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk, and other media that can store program codes. .

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (26)

1. a kind of fence synchronous method, which is characterized in that applied in the chip with multinuclear or many-core processor, the chip On be provided at least two fence sychronisations, the described method includes：

First processor core determines that currently processed multi-threaded program goes to predetermined fence synchronous point；The first processor core Any one in all processor cores included for the chip；

Target fence sychronisation is determined according to the corresponding fence mark of the predetermined fence synchronous point；

Fence synchronization message is sent to the target fence sychronisation；It is identified in the fence synchronization message comprising the fence And participate in the number of synchronous multi-threaded program.

It is 2. according to the method described in claim 1, it is characterized in that, described according to the predetermined corresponding grid of fence synchronous point Field mark, which is known, determines target fence sychronisation, including：

According to the corresponding fence mark of the predetermined fence synchronous point, determine that the target fence synchronously fills according to preset rules It puts；The preset rules include fence mark and the mapping relations of fence sychronisation.

3. according to the method described in claim 1, it is characterized in that, fence is sent to the target fence sychronisation described After synchronization message, further include：

Suspend the processing to the currently processed multi-threaded program, into wait state.

4. according to the method described in claim 3, it is characterized in that, in the pause to the currently processed multi-threaded program Processing, into after wait state, further includes：

Receive the confirmation message that the target fence sychronisation is sent；The confirmation message is used to notify the first processor Core continues with the currently processed multi-threaded program；

Continue with the currently processed multi-threaded program.

5. a kind of fence synchronous method, which is characterized in that applied in the chip with multinuclear or many-core processor, the chip On be provided at least two fence sychronisations, the described method includes：

Target fence sychronisation receives the fence synchronization message that first processor core is sent；The fence synchronization message is described What first processor core was sent when determining that currently processed multi-threaded program goes to predetermined fence synchronous point, at described first Reason device core is any one in all processor cores that the chip includes, comprising described predetermined in the fence synchronization message Fence synchronous point corresponding fence mark and participate in the number of synchronous multi-threaded program；The target fence sychronisation is For handling the fence sychronisation for the fence synchronization message that the corresponding processor core of the predetermined fence synchronous point is sent；

According to the count value for the count area that the corresponding fence mark of the predetermined fence synchronous point includes first queue Add 1；The first queue is the team for multi-threaded program state that identify all participations synchronous corresponding with fence mark Row；The first queue includes the fence mark, quene state, the count area.

6. according to the method described in claim 5, it is characterized in that, first queue is included in described identified according to the fence Count area count value add 1 before, further include：

Judge whether the first queue；

When there is no during the first queue, creating the first queue, and the quene state is updated to use state.

7. according to the method described in claim 5, it is characterized in that, the first queue also comprising executed to described predetermined The identification information of the corresponding processor core of multi-threaded program of fence synchronous point；

After the fence synchronization message sent in the reception first processor core, further include：

The identification information of the first processor core is added in the first queue.

8. the method according to the description of claim 7 is characterized in that add in the identification information by the first processor core Before adding in the first queue, further include：

Judge the executed to the identification information of the corresponding processor core of multi-threaded program of the predetermined fence synchronous point Whether number is less than predetermined threshold value；The predetermined threshold value is less than or equal to the maximum thread mesh that the chip is supported；

When the identification information of the definite executed to the corresponding processor core of multi-threaded program of the predetermined fence synchronous point Number be less than the predetermined threshold value when, perform the identification information by the first processor core be added to the first team In row.

9. it according to the method described in claim 8, it is characterized in that, further includes：

When the identification information of the definite executed to the corresponding processor core of multi-threaded program of the predetermined fence synchronous point Number be not less than the predetermined threshold value when, the identification information of the first processor core is preserved into memory.

10. according to the method described in claim 5, it is characterized in that, the first queue further includes to identify all participations Whether the per thread program in synchronous multi-threaded program goes to the bit sequence of the predetermined fence synchronous point, the ratio There are mapping relations for the identification information of each bit and processor core in special sequence；

After the fence synchronization message sent in the reception first processor core, further include：

The bit corresponding with the identification information of the first processor core is updated to second identifier by first flag；Described One mark is not carried out the predetermined fence synchronous point, second mark for identifying the multi-threaded program handled by processor core Know to identify by the multi-threaded program executed that processor core is handled to the predetermined fence synchronous point.

11. it according to the method described in claim 5, it is characterized in that, is identified described according to the fence by first queue bag After the count value of the count area contained adds 1, further include：

Judge whether the count value of the count area is equal to the number for participating in synchronous multi-threaded program；

When the count value of the count area is equal to the number of the multi-threaded program for participating in synchronization, it is same to obtain all participations The identification information of the corresponding processor core of synchronous multi-threaded program is each participated in the multi-threaded program of step；

According to all marks for participating in each participating in the corresponding processor core of synchronous multi-threaded program in synchronous multi-threaded program Know information, participate in each participating in the corresponding processor core transmission confirmation of synchronous multi-threaded program in synchronous multi-threaded program to all Message；The confirmation message is used to that the processor core to be notified to continue with the multi-threaded program that itself is needed to handle.

12. according to the method for claim 11, which is characterized in that described to obtain all participate in synchronous multi-threaded program often A identification information for participating in the synchronous corresponding processor core of multi-threaded program, including：

It is obtained from the first queue in all multi-threaded programs for participating in synchronization and each participates in synchronous multi-threaded program pair The identification information for the processor core answered.

13. according to the method for claim 11, which is characterized in that described to obtain all participate in synchronous multi-threaded program often A identification information for participating in the synchronous corresponding processor core of multi-threaded program, including：

Synchronous thread is each participated in the multi-threaded program synchronous with all participations are obtained in memory from the first queue The identification information of the corresponding processor core of program.

14. a kind of first processor core, which is characterized in that applied in the chip with multinuclear or many-core processor, the core On piece is provided at least two fence sychronisations, the first processor core, including：

First determination unit, for determining that currently processed multi-threaded program goes to predetermined fence synchronous point；At described first Reason device core is any one in all processor cores that the chip includes；

Second determination unit, for determining that target fence synchronously fills according to the corresponding fence mark of the predetermined fence synchronous point It puts；

Transmitting element, the target fence sychronisation for being obtained to second determination unit send fence and synchronously disappear Breath；The number of synchronous multi-threaded program is identified and participated in the fence synchronization message comprising the fence.

15. first processor core according to claim 14, which is characterized in that second determination unit is specifically used for：

According to the corresponding fence mark of the predetermined fence synchronous point, determine that the target fence synchronously fills according to preset rules It puts；The preset rules include fence mark and the mapping relations of fence sychronisation.

16. first processor core according to claim 14, which is characterized in that further include：

First processing units, for the transmitting element to the target fence sychronisation send fence synchronization message it Afterwards, the processing to the currently processed multi-threaded program is suspended, into wait state.

17. first processor core according to claim 16, which is characterized in that further include：

Receiving unit, for suspending the processing to the currently processed multi-threaded program in the first processing units, into etc. After treating state, the confirmation message that the target fence sychronisation is sent is received；The confirmation message is for notifying described the One processor core continues with the currently processed multi-threaded program；

Second processing unit, for continuing with the currently processed multi-threaded program.

18. a kind of target fence sychronisation, which is characterized in that applied in the chip with multinuclear or many-core processor, institute It states and at least two fence sychronisations is provided on chip, the target fence sychronisation, including：

Receiving unit, for receiving the fence synchronization message of first processor core transmission；The fence synchronization message is described the What one processor core was sent when determining that currently processed multi-threaded program goes to predetermined fence synchronous point, first processing Device core is any one in all processor cores that the chip includes, comprising described predetermined in the fence synchronization message The corresponding fence mark of fence synchronous point and the number for participating in synchronous multi-threaded program；The target fence sychronisation is use In the fence sychronisation for handling the fence synchronization message that the corresponding processor core of the predetermined fence synchronous point is sent；

Processing unit, for the predetermined fence included in the fence synchronization message that is obtained according to the receiving unit The count value for the count area that the corresponding fence mark of synchronous point includes first queue adds 1；The first queue for institute State the corresponding queues for being used to identify all multi-threaded program states for participating in synchronization of fence mark；The first queue includes described Fence mark, quene state, the count area.

19. target fence sychronisation according to claim 18, which is characterized in that further include：

Judging unit, for the counting for the count area for being included first queue according to fence mark in the processing unit Before numerical value adds 1, the first queue is judged whether；

Updating block is created, for when the judging unit obtains that the first queue is not present, creating the first queue, And the quene state is updated to use state.

20. target fence sychronisation according to claim 18, which is characterized in that the first queue is also included and held Row arrives the identification information of the corresponding processor core of multi-threaded program of the predetermined fence synchronous point；

The target fence sychronisation, further includes：

Adding device, described in after the fence synchronization message of receiving unit reception first processor core transmission, inciting somebody to action The identification information of first processor core is added in the first queue.

21. target fence sychronisation according to claim 20, which is characterized in that the target fence sychronisation, It further includes：

Judging unit, for the identification information of the first processor core to be added to the first queue in the adding device In before, judge the executed to the identification information of the corresponding processor core of multi-threaded program of the predetermined fence synchronous point Number whether be less than predetermined threshold value；The predetermined threshold value is less than or equal to the maximum thread mesh that the chip is supported；

The adding device determines the executed to the predetermined fence synchronous point specifically for working as the judging unit When the number of the identification information of the corresponding processor core of multi-threaded program is less than the predetermined threshold value, by the first processor core Identification information is added in the first queue.

22. target fence sychronisation according to claim 21, which is characterized in that further include：

Storage unit determines the executed to the multi-threaded program of the predetermined fence synchronous point for working as the judging unit When the number of the identification information of corresponding processor core is not less than the predetermined threshold value, the mark of the first processor core is believed Breath is preserved into memory.

23. target fence sychronisation according to claim 18, which is characterized in that the first queue, which further includes, to be used for Identify the ratio whether all per thread programs participated in synchronous multi-threaded program go to the predetermined fence synchronous point Special sequence, there are mapping relations for the identification information of each bit and processor core in the bit sequence；

The target fence sychronisation, further includes：

Updating block, for receive that first processor core is sent in the receiving unit fence synchronization message after, will be with institute Bit corresponding to identification information for stating first processor core is updated to second identifier by first flag；The first flag is used for Mark is not carried out the predetermined fence synchronous point by the multi-threaded program that processor core is handled, and the second identifier is used to identify By the multi-threaded program executed that processor core is handled to the predetermined fence synchronous point.

24. target fence sychronisation according to claim 18, which is characterized in that the target fence sychronisation, It further includes：

Judging unit, for the counting for the count area for being included first queue according to fence mark in the processing unit After numerical value adds 1, judge whether the count value of the count area is equal to the number for participating in synchronous multi-threaded program；

Acquiring unit, the count value that the count area is obtained for working as the judging unit are equal to the line for participating in synchronization During the number of Cheng Chengxu, obtain in all multi-threaded programs for participating in synchronization and each participate in the corresponding processor of synchronous multi-threaded program The identification information of core；

Transmitting element, for each participation to be same in the multi-threaded programs of all participation synchronizations obtained according to the acquiring unit The identification information of the corresponding processor core of multi-threaded program of step participates in each participating in synchronization in synchronous multi-threaded program to all The corresponding processor core of multi-threaded program sends confirmation message；The confirmation message is used to notify the processor core continues with to need The multi-threaded program of itself processing.

25. target fence sychronisation according to claim 24, which is characterized in that the acquiring unit is specifically used for：

It is obtained from the first queue in all multi-threaded programs for participating in synchronization and each participates in synchronous multi-threaded program pair The identification information for the processor core answered.

26. target fence sychronisation according to claim 24, which is characterized in that the acquiring unit is specifically used for：

Synchronous thread is each participated in the multi-threaded program synchronous with all participations are obtained in memory from the first queue The identification information of the corresponding processor core of program.