CN104925749A - Silicon wafer bonding method - Google Patents
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- CN104925749A CN104925749A CN201510187464.2A CN201510187464A CN104925749A CN 104925749 A CN104925749 A CN 104925749A CN 201510187464 A CN201510187464 A CN 201510187464A CN 104925749 A CN104925749 A CN 104925749A
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Abstract
The invention discloses a silicon wafer bonding method. The method comprises the following steps: providing a first silicon wafer, and forming an island structure in the first silicon wafer; forming a first oxide layer on the first silicon wafer with a thermal oxidation process, wherein the oxide layer is thicker than a central region on the edge of the island structure; forming a second oxide layer on the first oxide layer with a high-density plasma vapor deposition process, and performing rapid thermal annealing treatment, wherein the oxide layer is thinner than the central region on the edge of the island structure, and the first oxide layer and the second oxide layer are taken as bonding oxide layers; and providing a second silicon wafer, wherein the second silicon wafer is bonded with the first silicon wafer through the island structure. According to the characteristics of different processes, the thicknesses of the first oxide layer and the second oxide layer on the island structure compensate with each other, and high surface microcosmic flatness is achieved, so that a large bonding area is achieved when the first silicon wafer and the second silicon wafer are bonded together, and the bonding strength is enhanced.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of wafer bonding method.
Background technology
In recent years, along with MEMS (Micro-Electrico-Mechanical-System, MEMS) development of technology, various microelectromechanicdevices devices, comprise: microsensor, micro-actuator etc. achieve microminaturization, microminaturization is conducive to improving device integration, and therefore MEMS becomes one of main developing direction.
The Common fabrication processes of MEMS comprises body silicon manufacturing process, is specifically related to the bonding of silicon chip.Please refer to the schematic diagram of the device architecture in prior art as Figure 1-5 in wafer bonding process below.
As shown in Figure 1, first, provide the first silicon chip 1, and form mask layer 2 on the first silicon chip 1.Then, patterning is carried out to described mask layer 2, etch described first silicon chip 1 with the mask layer 2 of patterning, form the first cavity 3, as shown in Figure 2.Then, as shown in Figure 3, continue described first silicon chip 1 of etching, form the second cavity 4, and the sidewall of described second cavity 4 is isolated island structure 5.Afterwards, please refer to Fig. 4, the mask layer in isolated island structure 5 is removed, and utilizes thermal oxidation technology to form layer of oxide layer 6 on the first silicon chip 1.Next way is conventionally exactly as shown in Figure 5, and the second silicon chip 7 and the first silicon chip 1 are carried out bonding.
But please refer to Fig. 4 and Fig. 5, in the forming process of oxide layer 6, the marginal portion of isolated island structure 5 is than mid portion strong reaction, and therefore oxide layer 6 defines projection 61 in the marginal portion of isolated island structure 5.So as shown in Figure 5, after bonding, in fact bonding just occurs in projection 61, instead of whole isolated island structure (on oxide layer) is all bonded together with the second silicon chip 7.Obviously, such bond strength is very low, easily causes part to depart from even entirety and comes off, have a strong impact on the reliability of device.
Summary of the invention
The object of the invention is to, a kind of wafer bonding method is provided, improve bond strength, prevent from departing between silicon chip.
For solving the problems of the technologies described above, the invention provides a kind of wafer bonding method, comprising:
First silicon chip is provided, and forms isolated island structure in described first silicon chip;
Described first silicon chip utilizes thermal oxidation technology to form the first oxide layer, and described first oxide layer is thicker than middle section at the edge of isolated island structure;
Described first oxide layer utilize high density plasma CVD technique to form the second oxide layer, and carry out quick thermal annealing process, described second oxide layer is thinner than middle section at the edge of isolated island structure, and described first oxide layer and the second oxide layer are as bonding oxide layer;
There is provided the second silicon chip, described second silicon chip is by isolated island structure and the first wafer bonding.
Optionally, for described wafer bonding method, described in the first silicon chip is provided, and in described first silicon chip, form isolated island structure comprise following process:
Described first silicon chip forms mask layer;
Mask layer described in patterning;
Carry out first time etching, form the first cavity;
Carry out second time etching, form the second cavity, described second cavity sidewalls is described isolated island structure;
Remove described mask layer.
Optionally, for described wafer bonding method, the degree of depth of described first cavity is 1-5 μm.
Optionally, for described wafer bonding method, the degree of depth of described second cavity is 30-80 μm.
Optionally, for described wafer bonding method, in described second cavity, be formed with buffer stopper.
Optionally, for described wafer bonding method, thermal oxidation technology is adopted to form described first oxide layer.
Optionally, for described wafer bonding method, the thickness of described first oxide layer is 0.2-1.0 μm.
Optionally, for described wafer bonding method, high density plasma CVD technique is adopted to form described second oxide layer.
Optionally, for described wafer bonding method, the thickness of described second oxide layer is 0.4-1.5 μm.
Optionally, for described wafer bonding method, after described second silicon chip and the first wafer bonding, also comprise:
Thinning described second silicon chip.
Optionally, for described wafer bonding method, the thickness after described second wafer thinning is 20-70 μm.
In wafer bonding method provided by the invention, first on the first silicon chip, form the first oxide layer, then in the first oxide layer, form the second oxide layer, the first oxide layer and the second oxide layer are jointly as bonding oxide layer, and upper surface is smooth, then the first silicon chip and the second wafer bonding.Compared to existing technology, the feature of different process is utilized in the present invention, the thickness of the structural ground floor oxide layer of isolated island and second layer oxide layer is compensated mutually, obtain good surface microscopic flatness, thus make there is larger bonding area when the first silicon chip and the second wafer bonding, improve bond strength.
Accompanying drawing explanation
Fig. 1-5 is the schematic diagram of the device architecture in prior art in wafer bonding process;
Fig. 6 is the flow chart of wafer bonding method in the embodiment of the present invention;
Fig. 7-Figure 12 is the schematic diagram of the device architecture in the process of wafer bonding method in the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with schematic diagram, wafer bonding method of the present invention is described in more detail, which show the preferred embodiments of the present invention, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, a large amount of implementation detail must be made to realize the specific objective of developer, such as, according to regarding system or the restriction about business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, more specifically the present invention is described by way of example with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, a kind of wafer bonding method is provided, utilizes the feature of different process, the thickness being formed in the structural ground floor oxide layer of isolated island and second layer oxide layer is compensated mutually, obtain good surface microscopic flatness, thus to improve bond strength.
The method comprises:
Step S101, provides the first silicon chip, and forms isolated island structure in described first silicon chip;
Step S102, described first silicon chip utilizes thermal oxidation technology to form the first oxide layer, and described first oxide layer is thicker than middle section at the edge of isolated island structure;
Step S103, described first oxide layer utilize high density plasma CVD technique to form the second oxide layer, and carry out quick thermal annealing process, described second oxide layer is thinner than middle section at the edge of isolated island structure, and described first oxide layer and the second oxide layer are as bonding oxide layer;
Step S104, provides the second silicon chip, and described second silicon chip is by isolated island structure and the first wafer bonding.
Below enumerate the preferred embodiment of described wafer bonding method, to clearly demonstrate content of the present invention, it will be clear that content of the present invention is not restricted to following examples, other improvement by the routine techniques means of those of ordinary skill in the art are also within thought range of the present invention.
Please refer to Fig. 6, and composition graphs 7-Figure 12, wherein Fig. 6 is the flow chart of wafer bonding method in the embodiment of the present invention; Fig. 7 ~ Figure 12 is the schematic diagram of the device architecture in the process of wafer bonding method in the embodiment of the present invention.
As shown in Figure 6, in the present embodiment, described wafer bonding method comprises:
First, please refer to Fig. 7-Fig. 9, perform step S101, the first silicon chip is provided, and forms isolated island structure in described first silicon chip.Concrete, the selection of described first silicon chip 10 can be conventional silicon chip, comprises through processes such as prerinse, after the first silicon chip 10 chooses, carries out the formation of mask layer 11.As shown in Figure 7, described mask layer is preferably silicon oxide layer, can be formed, also can be silicon nitride layer, be formed by CVD technique by heat growth.The thickness of described mask layer 11 can be 0.5-1.5 μm, such as, and 0.5 μm, 0.8 μm, 1 μm etc.Certainly, the thickness of described mask layer 11 non-fully is limited to this scope, the mask layer 11 of other thickness is also fine.
Please refer to Fig. 8, after mask layer 11 is formed, patterning is carried out to mask layer 11, such as by lithographic etch process, some regions of mask layer 11 are removed, afterwards with the mask layer 11 after patterning for mask, carry out the first silicon chip 10 first time etching, form the first cavity 12.Preferably, the degree of depth of described first cavity 12 is 1-5 μm, such as 2 μm, 3 μm, 5 μm etc.Then, please refer to Fig. 9, proceed second time etching, form the second cavity 13.The sidewall of described second cavity 13 is isolated island structure 14.The degree of depth of described second cavity 13 is 30-80 μm, such as 40 μm, 50 μm, 60 μm etc.Wherein, when carrying out second time and etching, in the second cavity 13, be formed with buffer stopper 131.The height of described buffer stopper 131 can be chosen as the difference of the degree of depth of the second cavity 13 and the degree of depth of the first cavity 12, also can be less than.Then, mask layer 11 is removed.
Then, carry out step S102: on described first silicon chip 10, utilize thermal oxidation technology to form the first oxide layer 15, described first oxide layer 15 is thicker than middle section at the edge of isolated island structure 14.The thickness of described first oxide layer 15 can be 0.2-1.0 μm.As shown in Figure 10, after thermal oxide, in the edge of isolated island structure 14 upper end, the thickness of the first oxide layer 15 is greater than the thickness of first oxide layer 15 in isolated island structure 14 upper-center region, namely described in prior art, can form projection 151.So, then carry out next step.
Afterwards, carry out step S103, please refer to Figure 11, described first oxide layer 15 utilize high density plasma CVD technique (HDP CVD) form the second oxide layer 16, and carry out quick thermal annealing process, described second oxide layer 16 is thinner than middle section at the edge of isolated island structure 14, and described first oxide layer 15 and the second oxide layer 16 are as bonding oxide layer.First oxide layer 15 is formed the second oxide layer 16, and after deposition is formed, carry out rapid thermal annealing (RTA) process, described RTA is at 950 ~ 1100 DEG C, continues the time of 10 ~ 120 seconds, makes this second oxide layer 16 finer and close little with stress.Preferably, the thickness of described second oxide layer 16 is 0.4-1.5 μm, such as 0.6 μm, 1 μm, 1.2 μm etc.As seen from Figure 11, because the first oxide layer 15 is thicker than middle section at isolated island structure 14 edge, and the second oxide layer 16 is thinner than middle section at the edge of isolated island structure, therefore after the formation of this two-layer oxide layer, the thickness of the ground floor oxide layer 15 in isolated island structure 14 and second layer oxide layer 16 is compensated mutually, obtain good surface microscopic flatness, thus the bonding oxide layer upper surface obtained is smooth.
Afterwards, carry out step S104, please refer to Figure 12, provide the second silicon chip 20, described second silicon chip 20 is by isolated island structure 14 and the first silicon chip 10 bonding.As seen from Figure 12, the first silicon chip 10 and the second silicon chip 20 have larger bonding area, instead of as in prior art only at edge's bonding, this improves bond strength.
After described second silicon chip 20 and the first silicon chip 10 bonding, also comprise: thinning described second silicon chip.Such as, thickness after described second wafer thinning is 20-70 μm, according to different process requirements, can select different thickness, such as 30 μm, 40 μm, 50 μm etc.
Compared to existing technology, (namely the first oxide layer is thicker than middle section in isolated island structural edge to utilize the feature of different process in the present invention, and the second oxide layer is thinner than middle section at the edge of isolated island structure), the thickness of the structural ground floor oxide layer of isolated island and second layer oxide layer is compensated mutually, obtain good surface microscopic flatness, thus make there is larger bonding area when the first silicon chip and the second wafer bonding, improve bond strength.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (11)
1. a wafer bonding method, comprising:
First silicon chip is provided, and forms isolated island structure in described first silicon chip;
Described first silicon chip utilizes thermal oxidation technology to form the first oxide layer, and described first oxide layer is thicker than middle section at the edge of isolated island structure;
Described first oxide layer utilize high density plasma CVD technique to form the second oxide layer, and carry out quick thermal annealing process, described second oxide layer is thinner than middle section at the edge of isolated island structure, and described first oxide layer and the second oxide layer are as bonding oxide layer;
There is provided the second silicon chip, described second silicon chip is by isolated island structure and the first wafer bonding.
2. wafer bonding method as claimed in claim 1, is characterized in that, described in the first silicon chip is provided, and in described first silicon chip, form isolated island structure comprise following process:
Described first silicon chip forms mask layer;
Mask layer described in patterning;
Carry out first time etching, form the first cavity;
Carry out second time etching, form the second cavity, described second cavity sidewalls is described isolated island structure;
Remove described mask layer.
3. wafer bonding method as claimed in claim 2, it is characterized in that, the degree of depth of described first cavity is 1-5 μm.
4. wafer bonding method as claimed in claim 3, it is characterized in that, the degree of depth of described second cavity is 30-80 μm.
5. wafer bonding method as claimed in claim 4, is characterized in that, be formed with buffer stopper in described second cavity.
6. wafer bonding method as claimed in claim 1, is characterized in that, adopts thermal oxidation technology to form described first oxide layer.
7. wafer bonding method as claimed in claim 6, it is characterized in that, the thickness of described first oxide layer is 0.2 ~ 1.0 μm.
8. wafer bonding method as claimed in claim 1, is characterized in that, adopts high density plasma CVD technique to form described second oxide layer.
9. wafer bonding method as claimed in claim 8, it is characterized in that, the thickness of described second oxide layer is 0.4-1.5 μm.
10. wafer bonding method as claimed in claim 1, is characterized in that, after described second silicon chip and the first wafer bonding, also comprise:
Thinning described second silicon chip.
11. wafer bonding methods as claimed in claim 10, it is characterized in that, the thickness after described second wafer thinning is 20-70 μm.
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| CN109913880A (en) * | 2017-12-13 | 2019-06-21 | 南京机器人研究院有限公司 | A kind of weldment method for protecting surface |
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| CN108695231A (en) * | 2017-04-08 | 2018-10-23 | 沈阳硅基科技有限公司 | The preparation method of super thick soi wafer oxide layer |
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| US20060128116A1 (en) * | 2004-12-14 | 2006-06-15 | Sung Ku Kwon | Manufacturing method of silicon on insulator wafer |
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| CN102130039A (en) * | 2010-12-27 | 2011-07-20 | 上海新傲科技股份有限公司 | Method for preparing semiconductor substrate with insulating buried layer by gettering process |
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