CN104915180B - A kind of method and apparatus of data manipulation - Google Patents

Abstract

The embodiment of the present invention provides a kind of method and apparatus of data manipulation, is related to the communications field, can accurately judge whether data read command is key instruction, improves the speed that processor reads data in internal memory, and it is too high to avoid hardware cost.This method includes：It is key to determine that the first operational order has in compiler, and after first operational order is changed into the second operational order, Memory Controller Hub receives second operational order, key instruction that the Memory Controller Hub carries according to second operational order mark determines that second operational order is key instruction, and according to preference strategy in internal memory to should the data of the second operational order operate.The embodiment of the present invention is used for the operation to internal storage data.

Description

A method and device for data manipulation

technical field

The present invention relates to the communication field, in particular to a data operation method and device.

Background technique

In an existing system in which a processor accesses memory, the processor corresponds to at least one level of cache, and when the processor issues a data read command, it first queries the cache, and if no data is found in each level of cache When the data corresponding to the data read instruction is transmitted, the data read instruction will be transmitted to the memory controller, and the memory controller will schedule the instruction, and finally read the data corresponding to the data read instruction by accessing the memory.

Due to the long delay time of reading data in the memory, if the data reading instruction is a key instruction, that is to say, the execution of subsequent multiple instructions depends on the data reading instruction, the processor will be reduced. The processing rate of the entire process, therefore, in order to solve this problem, in the prior art, it is judged whether the data reading instruction is a critical instruction by adding a detection module and a prediction module, and the memory controller first determines that it is a critical instruction The data read instruction of the instruction is processed, reducing the delay time of the processor to read the data in the memory. Wherein, the detection module is used to notify the prediction module to query and predict the data read instruction when detecting a long-delayed data read instruction in the instruction submission queue; the prediction module is used to, according to the saved history The information queries and predicts the data read instruction.

However, the detection module and the prediction module increase the cost of hardware, and the prediction module predicts whether the data reading instruction is a critical instruction based on historical information, and there is a large error.

Contents of the invention

The invention provides a method and device for data operation, which can accurately judge whether a data reading instruction is a key instruction, improve the speed at which a processor reads data in a memory, and avoid high hardware costs.

To achieve the above object, the present invention adopts the following technical solutions:

The first aspect provides a data manipulation method, including:

After the compiler determines that the first operation instruction is critical and changes the first operation instruction to a second operation instruction, the memory controller receives the second operation instruction; the second operation instruction carries a key instruction identifier;

The memory controller determines that the second operation instruction is a critical instruction according to the critical instruction identifier;

Operate the data corresponding to the second operation instruction in the memory according to the priority strategy.

In a first possible implementation manner of the first aspect, if the first operation instruction is a data read instruction, receiving the second operation instruction by the memory controller includes:

receiving the first operation instruction sent by the processor when the processor does not find data corresponding to the first operation instruction in the cache;

With reference to the first aspect or the first possible implementation, in the second possible implementation, if the operation instruction to be invoked in the memory controller is not a critical instruction, the corresponding The data operation of the second operation instruction includes:

The second operation instruction is preferentially invoked to operate on data corresponding to the second operation instruction in the memory.

With reference to the second possible implementation manner, in a third possible implementation manner, before the preferentially calling the second operation instruction to operate on the data corresponding to the second operation instruction in the memory, the method further include:

According to the operand of the second operation instruction and the operand of the operation instruction to be called in the memory controller, it is determined that there is no order relationship between the operation instruction to be called in the memory controller and the second operation instruction.

The second aspect provides a data manipulation method, including:

The compiler compiles the source code to obtain the object code;

determining whether a first operation instruction in the object code is critical;

When determining that the first operation instruction is critical, changing the first operation instruction to a second operation instruction, wherein the second operation instruction carries a key instruction identifier, so that the memory controller receives the first operation instruction When the second operation instruction is used, the second operation instruction is determined to be a critical instruction according to the key instruction identifier, and the data corresponding to the second operation instruction in the memory is operated according to a priority policy.

In a first possible implementation manner of the second aspect, the determining whether the first operation instruction in the target code is critical includes:

When the operand of the first operation instruction and the operand of the operation instruction subsequent to the first operation instruction meet a preset condition, it is determined that the first operation instruction is critical.

A third aspect provides a memory controller, including:

A receiving unit, configured to receive the second operation instruction after the compiler determines that the first operation instruction is critical and changes the first operation instruction to a second operation instruction; the second operation instruction carries a key instruction logo;

A determining unit, configured to determine, according to the key instruction identifier, that the second operation instruction is a key instruction;

The processing unit is configured to operate the data corresponding to the second operation instruction in the memory according to the priority policy.

In a first possible implementation manner of the third aspect, the receiving unit is specifically configured to: if the first operation instruction is a data read instruction, if the processor does not find the corresponding first operation instruction in the cache When receiving the first operation instruction sent by the processor;

In combination with the third aspect or the first possible implementation manner, in the second possible implementation manner, the processing unit is specifically configured to: if the operation instruction to be called in the memory controller is not a critical instruction, preferentially call The second operation instruction operates on data corresponding to the second operation instruction in the memory.

With reference to the second possible implementation manner, in a third possible implementation manner, the processing unit is specifically configured to: perform an operation on the data corresponding to the second operation instruction in the memory after preferentially calling the second operation instruction Before, according to the operand of the second operation instruction and the operand of the operation instruction to be called in the memory controller, it is determined that the order of the operation instruction to be called in the memory controller and the second operation instruction does not exist relation.

A fourth aspect provides a compiler, including:

a processing unit, configured to compile the source code to obtain the object code;

a determining unit, configured to determine whether the first operation instruction in the target code is critical;

The processing unit is further configured to, when determining that the first operation instruction is critical, change the first operation instruction into a second operation instruction, wherein the second operation instruction carries a key instruction identifier, so that the memory When the controller receives the second operation instruction, it determines that the second operation instruction is a critical instruction according to the key instruction identifier, and operates the data corresponding to the second operation instruction in the memory according to a priority policy.

In a first possible implementation manner of the fourth aspect, the determining unit is specifically configured to:

When the operand of the first operation instruction and the operand of the operation instruction subsequent to the first operation instruction meet a preset condition, it is determined that the first operation instruction is critical.

With the above solution, after the compiler determines that the first operation instruction is critical and changes the first operation instruction to the second operation instruction, the memory controller receives the second operation instruction, and the memory controller receives the second operation instruction according to the second operation instruction. The key instruction identification carried by the instruction determines that the second operation instruction is a key instruction, and the data corresponding to the second operation instruction in the memory is operated according to the priority strategy. In this way, if the memory controller receives a data read instruction, it can determine whether the data read instruction is a critical instruction according to whether the data read instruction carries a key instruction identifier, and preferentially calls the data read instruction to read in the memory. Fetching the corresponding data can accurately judge whether the data reading instruction is a key instruction, improve the speed at which the processor reads data in the memory, and avoid the problem of high hardware cost caused by query and prediction.

Description of drawings

FIG. 1 is a schematic structural diagram of a system for accessing memory by a processor according to an embodiment of the present invention;

FIG. 2 is a schematic flowchart of a data manipulation method provided by an embodiment of the present invention;

FIG. 3 is a schematic diagram of a memory controller instruction queue provided by an embodiment of the present invention;

FIG. 4 is a schematic flowchart of another data manipulation method provided by an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a memory controller provided by an embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a compiler provided by an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of another memory controller provided by an embodiment of the present invention;

FIG. 8 is a schematic structural diagram of another compiler provided by an embodiment of the present invention.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The following embodiments of the present invention can be applied to a system in which a processor accesses memory. The system is shown in FIG. 1, the compiler is used to compile the source code to obtain an executable program; the processor is used to execute the executable program obtained by the compiler; the first-level cache is used to quickly cache data ; The secondary cache is used to quickly cache data; the memory controller is an important part of the computer system to control the memory and exchange data between the memory and the processor through the memory controller; the memory is used to store Data whose storage capacity is greater than that of the cache, but whose read and write access speed is less than that of the cache.

An embodiment of the present invention provides a method for data manipulation, as shown in FIG. 2 , including:

S201. After the compiler determines that the first operation instruction is critical and changes the first operation instruction to a second operation instruction, the memory controller receives the second operation instruction.

Wherein, the second operation instruction carries a key instruction identifier.

Specifically, the compiler compiles the source code to obtain the target code, and detects the obtained target code, and detects a critical first operation instruction, then the compiler changes the first operation instruction to carry the key instruction identifier The second operation instruction.

Optionally, the compiler determines that the first operation instruction is critical when an operand of the first operation instruction and an operand of an operation instruction subsequent to the first operation instruction satisfy a preset condition.

For example, the source code is:

...

for(i=1; i<100; i++)

a[i]=a[0]+i;

...

The compiler compiles the object code:

...

LDR R2, [R1];

ADD R3,R2,#1

STR R3,[R1,#1]

ADD R3,R2,#2

STR R3, [R1, #2]

...

ADD R3,R2,#99

STR R3, [R1, #99]

...

Further, after the compiler obtains the above object code, it scans the object code to detect the relationship between the operand of each operation instruction and the operand of the operation instruction subsequent to the operation instruction, and the operand of the first operation instruction When an operand of an operation instruction following the first operation instruction satisfies a preset condition, it is determined that the first operation instruction is critical. For example, the preset condition is that the number of occurrences of the operand in the first operation instruction in the operands of the subsequent operation instruction is greater than 5, then in the above object code, for the first operation instruction LDR R2, [R1], the first operation instruction An operation instruction indicates that the data at the address of R1 is read and stored in the register R2, and the compiler can determine that the operand R2 in the first operation instruction is in the subsequent instruction by scanning the operation instructions subsequent to the first operation instruction. If the number of occurrences is greater than 5, the compiler determines that the first operation instruction is critical.

It can be seen from the source code that the value of array a[1] to array a[99] obtained by executing the loop uses the value of array a[0], which is the value in register R2 in the corresponding target code. Therefore, if the If the first operation instruction is not successfully executed, subsequent operation instructions cannot be executed.

Further, when the compiler determines that the first operation instruction is critical, it changes the first operation instruction into a second operation instruction, such as LDR_c R2, [R1], and the changed object code is:

...

LDR_c R2, [R1]

ADD R3,R2,#1

STR R3,[R1,#1]

ADD R3,R2,#2

STR R3, [R1, #2]

...

ADD R3,R2,#99

STR R3, [R1, #99]

...

It should be noted that the above preset condition can also be that the frequency of the operand in the first operation instruction appearing in the operand of the subsequent operation instruction is greater than N, and N is a positive integer greater than zero, that is, the compiler is scanning the target After the code, if it is determined that the operand R2 of the first operation instruction occurs more frequently than N in subsequent operation instructions, the compiler determines that the first operation instruction is critical.

Optionally, if the first operation instruction is a data read instruction, when the processor does not find the data corresponding to the first operation instruction in the cache, the memory controller receives the first operation instruction sent by the processor .

It should be noted that the processor supports the existence of the second operation instruction, and when the processor processes the second operation instruction, the processing manner is the same as that of the first operation instruction. That is, if the first operation instruction is a data read instruction, when the processor executes the second operation instruction, it first queries the data corresponding to the second operation instruction in the cache, and if there is a data corresponding to the second operation instruction in the cache data, the processor reads the data; if the data corresponding to the second operation instruction cannot be found in each level of cache, the second operation instruction is sent to the memory controller.

S202. The memory controller determines that the second operation instruction is a critical instruction according to the critical instruction identifier.

Specifically, when the memory controller receives the second operation instruction, it determines that the second operation instruction is a critical instruction according to the key instruction identification carried by the second operation instruction, wherein the key instruction identification can be the second The name of the operation code of the operation instruction, such as the above-mentioned LDR_c, may also be other identification information carried by the instruction, which is used to indicate the criticality of the second operation instruction.

S203. The memory controller operates the data corresponding to the second operation instruction in the memory according to the priority policy.

Optionally, if the operation instruction to be invoked in the memory controller is not a critical instruction, the memory controller preferentially invokes the second operation instruction to operate on data corresponding to the second operation instruction in the memory.

Optionally, before the preferentially calling the second operation instruction to operate on the data corresponding to the second operation instruction in the memory, the memory controller according to the operand of the second operation instruction and the memory controller to be called The operand of the operation instruction determines that there is no order relationship between the operation instruction to be called in the memory controller and the second operation instruction.

It should be noted that the relationship of the above sequence means that the memory controller can only execute the operation instruction to be called first, and then execute the second operation instruction, for example:

STR R1, R2

LDR_c R3, R2

According to the above code, LDR_c R3 can only be executed after executing STR R1 and R2 to write the data in register R1 into register R2, and R2 reads the data in register R2 as register R3, so the STR and the LDR_c exist sequence relationship.

Exemplarily, the priority policy is: if the instruction to be called in the instruction queue of the memory controller is a critical instruction, then execute the instruction to be called preferentially; if the instruction to be called in the instruction queue of the memory controller is not critical instruction and there is an order relationship between the instruction to be called and the second operation instruction, the instruction to be called is executed first; if the instruction to be called in the instruction queue of the memory controller is not a critical instruction and the instruction to be called is related to the second operation If there is no order relationship among the instructions, the second operation instruction is executed preferentially.

As shown in FIG. 3 , the instruction queue of the memory controller includes operation instructions LDR_c, STR, LDR and the second operation instruction, and the order in which the memory controller executes the operation instructions is LDR_c, STR, the second operation instruction, LDR. Wherein, the LDR_c is a key instruction and does not have an order relationship with the second operation instruction; the STR has an order relationship with the second operation instruction, for example, the second operation instruction is a data read instruction, and the second operation instruction The destination operand of the second operation instruction is the same as the source operand corresponding to the STR, that is, after the memory controller executes the STR instruction to write to a certain address, it executes the second operation instruction to read the data at the same address, Therefore, the STR must be executed before the second operation instruction; the LDR is not a critical instruction and has no order relationship with the second operation instruction.

Using the above method, after the compiler determines that the first operation instruction is critical and changes the first operation instruction to the second operation instruction, the memory controller receives the second operation instruction, and the memory controller according to the second operation instruction The key instruction identification carried by the instruction determines that the second operation instruction is a key instruction, and the data corresponding to the second operation instruction in the memory is operated according to the priority policy. In this way, if the memory controller receives a data read instruction, it can determine whether the data read instruction is a critical instruction according to whether the data read instruction carries a key instruction identifier, and preferentially calls the data read instruction to read in the memory. Fetching the corresponding data can accurately judge whether the data reading instruction is a key instruction, improve the speed at which the processor reads data in the memory, and avoid the problem of high hardware cost caused by query and prediction.

An embodiment of the present invention provides a data manipulation method, as shown in FIG. 4 , including:

S401. The compiler compiles the source code to obtain the object code.

S402. The compiler determines whether the first operation instruction in the object code is critical.

Optionally, the compiler determines that the first operation instruction is critical when an operand of the first operation instruction and an operand of an operation instruction subsequent to the first operation instruction satisfy a preset condition.

For example, the source code is:

...

for(i=1; i<100; i++)

a[i]=a[0]+i;

...

The compiler compiles the object code:

...

LDR R2, [R1];

ADD R3,R2,#1

STR R3,[R1,#1]

ADD R3,R2,#2

STR R3, [R1, #2]

...

ADD R3,R2,#99

STR R3, [R1, #99]

...

Further, after the compiler obtains the above object code, it scans the object code to detect the relationship between the operand of each operation instruction and the operand of the operation instruction subsequent to the operation instruction, and the operand of the first operation instruction When an operand of an operation instruction following the first operation instruction satisfies a preset condition, it is determined that the first operation instruction is critical. For example, the preset condition is that the number of occurrences of the operand in the first operation instruction in the operands of the subsequent operation instruction is greater than 5, then in the above object code, for the first operation instruction LDR R2, [R1], the first operation instruction An operation instruction indicates that the data at the address of R1 is read and stored in the register R2, and the compiler can determine that the operand R2 in the first operation instruction is in the subsequent instruction by scanning the operation instructions subsequent to the first operation instruction. If the number of occurrences is greater than 5, the compiler determines that the first operation instruction is critical.

It can be seen from the source code that the value of array a[1] to array a[99] obtained by executing the loop uses the value of array a[0], which is the value in register R2 in the corresponding target code. Therefore, if the If the first operation instruction is not successfully executed, subsequent operation instructions cannot be executed.

It should be noted that the above preset condition can also be that the frequency of the operand in the first operation instruction appearing in the operand of the subsequent operation instruction is greater than N, and N is a positive integer greater than zero, that is, the compiler is scanning the target After the code, if it is determined that the operand R2 of the first operation instruction occurs more frequently than N in subsequent operation instructions, the compiler determines that the first operation instruction is critical.

S403. When the compiler determines that the first operation instruction is critical, change the first operation instruction into a second operation instruction.

Wherein, the second operation instruction carries a key instruction identification, so that when the memory controller receives the second operation instruction, it determines that the second operation instruction is a key instruction according to the key instruction identification, and passes the second operation instruction according to the priority policy. The operation instruction operates on the data corresponding to the second operation instruction in the memory.

For example, when the compiler determines that the first operation instruction is critical, it changes the first operation instruction into a second operation instruction, such as changing the first operation instruction LDR R2, [R1] into a second operation instruction LDR_c R2, [R1], then the changed object code is:

...

LDR_c R2, [R1]

ADD R3,R2,#1

STR R3,[R1,#1]

ADD R3,R2,#2

STR R3, [R1, #2]

...

ADD R3, R2, #99

STR R3, [R1, #99]

...

Optionally, if the first operation instruction is a data read instruction, when the processor does not find the data corresponding to the first operation instruction in the cache, the memory controller receives the first operation instruction sent by the processor .

It should be noted that the processor supports the existence of the second operation instruction, and when the processor processes the second operation instruction, the processing manner is the same as that of the first operation instruction. That is, if the first operation instruction is a data read instruction, when the processor executes the second operation instruction, it first queries the data corresponding to the second operation instruction in the cache, and if there is a data corresponding to the second operation instruction in the cache data, the processor reads the data; if the data corresponding to the second operation instruction cannot be found in each level of cache, the second operation instruction is sent to the memory controller.

When the memory controller receives the second operation instruction, it determines that the second operation instruction is a critical instruction according to the key instruction identification carried by the second operation instruction, wherein the key instruction identification may be the key instruction of the second operation instruction. The name of the operation code, such as the above-mentioned LDR_c, may also be other identification information carried by the instruction, which is used to indicate the criticality of the second operation instruction.

Using the above method, after the compiler obtains the target code, it determines that the first operation instruction is critical, and changes the first operation instruction into a second operation instruction, so that the memory controller can determine The second operation instruction is a critical instruction, and the data corresponding to the second operation instruction in the memory is operated according to the priority policy. In this way, if the memory controller receives a data read instruction, it can determine whether the data read instruction is a critical instruction according to whether the data read instruction carries a key instruction identifier, and preferentially calls the data read instruction to read in the memory. Fetching the corresponding data can accurately judge whether the data reading instruction is a key instruction, improve the speed at which the processor reads data in the memory, and avoid the problem of high hardware cost caused by query and prediction.

An embodiment of the present invention provides a memory controller 50, as shown in FIG. 5, including:

The receiving unit 51 is configured to receive the second operation instruction after the compiler determines that the first operation instruction is critical and changes the first operation instruction into a second operation instruction.

Wherein, the second operation instruction carries a key instruction identifier.

The determining unit 52 is configured to determine, according to the key instruction identifier, that the second operation instruction is a key instruction.

The processing unit 53 is configured to operate the data corresponding to the second operation instruction in the memory according to the priority policy.

Specifically, the compiler compiles the source code to obtain the target code, and detects the obtained target code, and detects a critical first operation instruction, then the compiler changes the first operation instruction to carry the key instruction identifier The second operation instruction.

Optionally, the compiler determines that the first operation instruction is critical when an operand of the first operation instruction and an operand of an operation instruction subsequent to the first operation instruction satisfy a preset condition.

For example, the source code is:

...

for(i=1; i<100; i++)

a[i]=a[0]+i;

...

The compiler compiles the object code:

...

LDR R2, [R1];

ADD R3,R2,#1

STR R3,[R1,#1]

ADD R3,R2,#2

STR R3, [R1, #2]

...

ADD R3, R2, #99

STR R3, [R1, #99]

...

Further, after the compiler obtains the above object code, it scans the object code to detect the relationship between the operand of each operation instruction and the operand of the operation instruction subsequent to the operation instruction, and the operand of the first operation instruction When an operand of an operation instruction following the first operation instruction satisfies a preset condition, it is determined that the first operation instruction is critical. For example, the preset condition is that the number of occurrences of the operand in the first operation instruction in the operands of the subsequent operation instruction is greater than 5, then in the above object code, for the first operation instruction LDR R2, [R1], the first operation instruction An operation instruction indicates that the data at the address of R1 is read and stored in the register R2, and the compiler can determine that the operand R2 in the first operation instruction is in the subsequent instruction by scanning the operation instructions subsequent to the first operation instruction. If the number of occurrences is greater than 5, the compiler determines that the first operation instruction is critical.

It can be seen from the source code that the value of array a[1] to array a[99] obtained by executing the loop uses the value of array a[0], which is the value in register R2 in the corresponding target code. Therefore, if the If the first operation instruction is not successfully executed, subsequent operation instructions cannot be executed.

Further, when the compiler determines that the first operation instruction is critical, it changes the first operation instruction into a second operation instruction, such as LDR_c R2, [R1], and the changed object code is:

...

LDR_c R2, [R1]

ADD R3,R2,#1

STR R3,[R1,#1]

ADD R3,R2,#2

STR R3, [R1, #2]

...

ADD R3, R2, #99

STR R3, [R1, #99]

...

It should be noted that the above preset condition can also be that the frequency of the operand in the first operation instruction appearing in the operand of the subsequent operation instruction is greater than N, and N is a positive integer greater than zero, that is, the compiler is scanning the target After the code, if it is determined that the operand R2 of the first operation instruction occurs more frequently than N in subsequent operation instructions, the compiler determines that the first operation instruction is critical.

Optionally, the receiving unit 51 is specifically configured to, if the first operation instruction is a data read instruction, receive the second operation instruction sent by the processor when the processor does not find the data corresponding to the first operation instruction in the cache. an operation instruction.

It should be noted that the processor supports the existence of the second operation instruction, and when the processor processes the second operation instruction, the processing manner is the same as that of the first operation instruction. That is, if the first operation instruction is a data read instruction, when the processor executes the second operation instruction, it first queries the data corresponding to the second operation instruction in the cache, and if there is a data corresponding to the second operation instruction in the cache data, the processor reads the data; if the data corresponding to the second operation instruction cannot be found in each level of cache, the second operation instruction is sent to the memory controller.

Further, when the memory controller receives the second operation instruction, it determines that the second operation instruction is a critical instruction according to the key instruction identification carried by the second operation instruction, wherein the key instruction identification can be the second The name of the operation code of the operation instruction, such as the above-mentioned LDR_c, may also be other identification information carried by the instruction, which is used to indicate the criticality of the second operation instruction.

Optionally, the processing unit 53 is specifically configured to, if the operation instruction to be invoked in the memory controller is not a critical instruction, preferentially invoke the second operation instruction to operate on data corresponding to the second operation instruction in the memory.

Optionally, the processing unit 53 is also configured to, before preferentially calling the second operation instruction to operate on the data in the memory corresponding to the second operation instruction, according to the operand of the second operation instruction and the memory controller The operand of the operation instruction to be called determines that there is no order relationship between the operation instruction to be called in the memory controller and the second operation instruction.

It should be noted that the relationship of the above sequence means that the memory controller can only execute the operation instruction to be called first, and then execute the second operation instruction, for example:

STR R1, R2

LDR_c R3, R2

According to the above code, LDR_c R3 can only be executed after executing STR R1 and R2 to write the data in register R1 into register R2, and R2 reads the data in register R2 as register R3, so the STR and the LDR_c exist sequence relationship.

Exemplarily, the priority policy is: if the instruction to be called in the instruction queue of the memory controller is a critical instruction, then execute the instruction to be called preferentially; if the instruction to be called in the instruction queue of the memory controller is not critical instruction and there is an order relationship between the instruction to be called and the second operation instruction, the instruction to be called is executed first; if the instruction to be called in the instruction queue of the memory controller is not a critical instruction and the instruction to be called is related to the second operation If there is no order relationship among the instructions, the second operation instruction is executed preferentially.

Those skilled in the art can clearly understand that for the convenience and brevity of description, only the division of the above-mentioned functional modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional modules according to needs. The internal structure of the device is divided into different functional modules to complete all or part of the functions described above. For the specific working process of the units described above, reference may be made to the corresponding process in the foregoing method embodiments, and details are not repeated here.

With the above memory controller, after the compiler determines that the first operation instruction is critical and changes the first operation instruction into a second operation instruction, the memory controller receives the second operation instruction, and the memory controller according to the The key instruction identification carried by the second operation instruction determines that the second operation instruction is a key instruction, and the data corresponding to the second operation instruction in the memory is operated according to the priority strategy. In this way, if the memory controller receives a data read instruction, it can determine whether the data read instruction is a critical instruction according to whether the data read instruction carries a key instruction identifier, and preferentially calls the data read instruction to read in the memory. Fetching the corresponding data can accurately judge whether the data reading instruction is a key instruction, improve the speed at which the processor reads data in the memory, and avoid the problem of high hardware cost caused by query and prediction.

An embodiment of the present invention provides a compiler 60, as shown in FIG. 6, including:

The processing unit 61 is configured to compile the source code to obtain the object code.

The determining unit 62 is configured to determine whether the first operation instruction in the object code is critical.

The processing unit 61 is further configured to, when determining that the first operation instruction is critical, change the first operation instruction into a second operation instruction.

Wherein, the second operation instruction carries a key instruction identification, so that when the memory controller receives the second operation instruction, it determines that the second operation instruction is a key instruction according to the key instruction identification, and according to the priority policy, the pair in the memory The operation should be performed on the data of the second operation instruction.

Optionally, the determining unit 62 is specifically configured to determine that the first operation instruction is critical when the operand of the first operation instruction and the operand of a subsequent operation instruction of the first operation instruction meet a preset condition.

For example, the source code is:

...

for(i=1; i<100; i++)

a[i]=a[0]+i;

...

The compiler compiles the object code:

...

LDR R2, [R1];

ADD R3,R2,#1

STR R3,[R1,#1]

ADD R3,R2,#2

STR R3, [R1, #2]

...

ADD R3,R2,#99

STR R3, [R1, #99]

...

Further, after the compiler obtains the above object code, it scans the object code to detect the relationship between the operand of each operation instruction and the operand of the operation instruction subsequent to the operation instruction, and the operand of the first operation instruction When an operand of an operation instruction following the first operation instruction satisfies a preset condition, it is determined that the first operation instruction is critical. For example, the preset condition is that the number of occurrences of the operand in the first operation instruction in the operands of the subsequent operation instruction is greater than 5, then in the above object code, for the first operation instruction LDR R2, [R1], the first operation instruction An operation instruction indicates that the data at the address of R1 is read and stored in the register R2, and the compiler can determine that the operand R2 in the first operation instruction is in the subsequent instruction by scanning the operation instructions subsequent to the first operation instruction. If the number of occurrences is greater than 5, the compiler determines that the first operation instruction is critical.

It can be seen from the source code that the value of array a[1] to array a[99] obtained by executing the loop uses the value of array a[0], which is the value in register R2 in the corresponding target code. Therefore, if the If the first operation instruction is not successfully executed, subsequent operation instructions cannot be executed.

Further, when the compiler determines that the first operation instruction is critical, it changes the first operation instruction into a second operation instruction, such as LDR_c R2, [R1], and the changed object code is:

...

LDR_c R2, [R1]

ADD R3,R2,#1

STR R3,[R1,#1]

ADD R3,R2,#2

STR R3, [R1, #2]

...

ADD R3, R2, #99

STR R3, [R1, #99]

...

It should be noted that the above preset condition can also be that the frequency of the operand in the first operation instruction appearing in the operand of the subsequent operation instruction is greater than N, and N is a positive integer greater than zero, that is, the compiler is scanning the target After the code, if it is determined that the operand R2 of the first operation instruction occurs more frequently than N in subsequent operation instructions, the compiler determines that the first operation instruction is critical.

Further, when the compiler determines that the first operation instruction is critical, it changes the first operation instruction into a second operation instruction, such as changing the first operation instruction LDR R2, [R1] into a second operation instruction LDR_c R2, [R1], then the changed object code is:

...

LDR_c R2, [R1]

ADD R3,R2,#1

STR R3,[R1,#1]

ADD R3,R2,#2

STR R3, [R1,#2]

...

ADD R3,R2,#99

STR R3, [R1, #99]

...

Optionally, if the first operation instruction is a data read instruction, when the processor does not find the data corresponding to the first operation instruction in the cache, the memory controller receives the first operation instruction sent by the processor .

It should be noted that the processor supports the existence of the second operation instruction, and when the processor processes the second operation instruction, the processing manner is the same as that of the first operation instruction. That is, if the first operation instruction is a data read instruction, when the processor executes the second operation instruction, it first queries the data corresponding to the second operation instruction in the cache, and if there is a data corresponding to the second operation instruction in the cache data, the processor reads the data; if the data corresponding to the second operation instruction cannot be found in each level of cache, the second operation instruction is sent to the memory controller.

When the memory controller receives the second operation instruction, it determines that the second operation instruction is a critical instruction according to the key instruction identification carried by the second operation instruction, wherein the key instruction identification may be the key instruction of the second operation instruction. The name of the operation code, such as the above-mentioned LDR_c, may also be other identification information carried by the instruction, which is used to indicate the criticality of the second operation instruction.

Those skilled in the art can clearly understand that for the convenience and brevity of description, only the division of the above-mentioned functional modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional modules according to needs. The internal structure of the device is divided into different functional modules to complete all or part of the functions described above. For the specific working process of the units described above, reference may be made to the corresponding process in the foregoing method embodiments, and details are not repeated here.

Using the above-mentioned compiler, after obtaining the object code, the compiler determines that the first operation instruction is critical, and changes the first operation instruction into a second operation instruction, so that when the memory controller receives the second operation instruction , determining that the second operation instruction is a critical instruction, and operating the data corresponding to the second operation instruction in the memory according to the priority strategy. In this way, if the memory controller receives a data read instruction, it can determine whether the data read instruction is a critical instruction according to whether the data read instruction carries a key instruction identifier, and preferentially calls the data read instruction to read in the memory. Fetching the corresponding data can accurately judge whether the data reading instruction is a key instruction, improve the speed at which the processor reads data in the memory, and avoid the problem of high hardware cost caused by query and prediction.

An embodiment of the present invention provides a memory controller 70. As shown in FIG. 7, the memory controller 70 includes:

A processor (processor) 71, a communication interface (Communications Interface) 72, a memory (memory) 73, and a communication bus 74; wherein, the processor 71, the communication interface 72, and the memory 73 are completed through the communication bus 74 mutual communication.

The processor 71 may be a multi-core CPU, or an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present invention.

The memory 73 is used to store program codes, which include computer operation instructions and network flow diagrams. The memory 73 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one magnetic disk memory.

The communication interface 72 is used to realize connection and communication between these devices.

The processor 71 is used to execute the program codes in the memory 73 to achieve the following operations:

After the compiler determines that the first operation instruction is critical and changes the first operation instruction to a second operation instruction, receiving the second operation instruction; the second operation instruction carries a key instruction identifier;

determining that the second operation instruction is a critical instruction according to the key instruction identifier;

Operate the data corresponding to the second operation instruction in the memory according to the priority policy.

Optionally, if the first operation instruction is a data read instruction, receiving the second operation instruction by the memory controller specifically includes:

When the processor does not find data corresponding to the first operation instruction in the cache, the first operation instruction sent by the processor is received.

Optionally, if the operation instruction to be called in the memory controller is not a critical instruction, the operating the data corresponding to the second operation instruction in the memory according to the priority strategy specifically includes:

The second operation instruction is preferentially invoked to operate on data corresponding to the second operation instruction in the memory.

Optionally, before the preferentially calling the second operation instruction to operate on the data corresponding to the second operation instruction in the memory, the operation further includes:

According to the operand of the second operation instruction and the operand of the operation instruction to be called in the memory controller, it is determined that there is no order relationship between the operation instruction to be called in the memory controller and the second operation instruction.

Those skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process and description of the above-described memory controller can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

An embodiment of the present invention provides a compiler 80. As shown in FIG. 8, the compiler 80 includes:

A processor (processor) 81, a communication interface (Communications Interface) 82, a memory (memory) 83, and a communication bus 84; wherein, the processor 81, the communication interface 82, and the memory 83 are completed through the communication bus 84 mutual communication.

The processor 81 may be a multi-core CPU, or an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present invention.

The memory 83 is used to store program codes, which include computer operation instructions and network flow diagrams. The memory 83 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one magnetic disk memory.

The communication interface 82 is used to realize connection and communication between these devices.

The processor 81 is used to execute the program code in the memory 83 to realize the following operations:

Compile the source code to get the object code;

determining whether a first operation instruction in the object code is critical;

When determining that the first operation instruction is critical, changing the first operation instruction to a second operation instruction, wherein the second operation instruction carries a key instruction identifier, so that the memory controller receives the first operation instruction When the second operation instruction is used, the second operation instruction is determined to be a critical instruction according to the key instruction identifier, and the data corresponding to the second operation instruction in the memory is operated according to a priority policy.

Optionally, the determining whether the first operation instruction in the target code is critical specifically includes:

When the operand of the first operation instruction and the operand of the operation instruction subsequent to the first operation instruction satisfy a preset condition, the first operation instruction is determined to be critical.

Those skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process and description of the above-described sensing device can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. All should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (10)

1. A method for data manipulation, comprising: After the compiler determines that the first operation instruction is critical and changes the first operation instruction to a second operation instruction, the memory controller receives the second operation instruction; the second operation instruction carries a key instruction identifier; Wherein, the criticality of the first operation instruction means that when the operand of the first operation instruction and the operand of the operation instruction subsequent to the first operation instruction meet a preset condition, the first operation instruction has Criticality; The memory controller determines that the second operation instruction is a critical instruction according to the critical instruction identifier; Operate the data corresponding to the second operation instruction in the memory according to the priority policy. 2. The method according to claim 1, wherein if the first operation instruction is a data read instruction, receiving the second operation instruction by the memory controller comprises: When the processor does not find data corresponding to the first operation instruction in the cache, the first operation instruction sent by the processor is received. 3. The method according to claim 1 or 2, wherein, if the operation instruction to be called in the memory controller is not a critical instruction, the corresponding second operation instruction in the memory according to the priority policy The data to manipulate includes: The second operation instruction is preferentially invoked to operate on data corresponding to the second operation instruction in the memory. 4. The method according to claim 3, wherein before the preferentially calling the second operation instruction to operate on the data corresponding to the second operation instruction in the memory, the method further comprises: According to the operand of the second operation instruction and the operand of the operation instruction to be called in the memory controller, it is determined that there is no order relationship between the operation instruction to be called in the memory controller and the second operation instruction; The sequence relationship means that the memory controller can only execute the operation instruction to be called first, and then execute the second operation instruction. 5. A method for data manipulation, comprising: The compiler compiles the source code to obtain the object code; determining whether the first operation instruction in the target code is critical; where the first operation instruction is critical means that the operand of the first operation instruction and the operation instruction subsequent to the first operation instruction When the operand of satisfies the preset condition, the first operation instruction is critical; When determining that the first operation instruction is critical, changing the first operation instruction to a second operation instruction, wherein the second operation instruction carries a key instruction identifier, so that the memory controller receives the first operation instruction When the second operation instruction is used, the second operation instruction is determined to be a critical instruction according to the key instruction identifier, and the data corresponding to the second operation instruction in the memory is operated according to a priority strategy. 6. A memory controller, characterized in that, comprising: A receiving unit, configured to receive the second operation instruction after the compiler determines that the first operation instruction is critical and changes the first operation instruction to a second operation instruction; the second operation instruction carries a key instruction identification; wherein, the first operation instruction has criticality means that when the operand of the first operation instruction and the operand of the operation instruction subsequent to the first operation instruction meet a preset condition, the first operation the order is critical; A determining unit, configured to determine, according to the key instruction identifier, that the second operation instruction is a key instruction; The processing unit is configured to operate the data corresponding to the second operation instruction in the memory according to the priority policy. 7. The memory controller according to claim 6, wherein the receiving unit is specifically configured to: if the first operation instruction is a data read instruction, the processor does not find the corresponding operation instruction in the cache. When the data of an operation instruction is received, the first operation instruction sent by the processor is received. 8. The memory controller according to claim 6 or 7, wherein the processing unit is specifically configured to: if the operation instruction to be called in the memory controller is not a critical instruction, preferentially call the second The operation instruction operates on the data corresponding to the second operation instruction in the memory. 9. The memory controller according to claim 8, wherein the processing unit is specifically configured to: before preferentially calling the second operation instruction to operate on data corresponding to the second operation instruction in the memory, According to the operand of the second operation instruction and the operand of the operation instruction to be called in the memory controller, it is determined that there is no order relationship between the operation instruction to be called in the memory controller and the second operation instruction; The sequence relationship means that the memory controller can only execute the operation instruction to be called first, and then execute the second operation instruction. 10. A compiler, characterized in that, comprising: a processing unit, configured to compile the source code to obtain the object code; A determining unit, configured to determine whether the first operation instruction in the target code is critical; where the first operation instruction is critical means that the operand of the first operation instruction and the first operation When the operand of the operation instruction following the instruction satisfies a preset condition, the first operation instruction is critical; The processing unit is further configured to, when determining that the first operation instruction is critical, change the first operation instruction into a second operation instruction, wherein the second operation instruction carries a key instruction identifier, so that the memory When the controller receives the second operation instruction, it determines that the second operation instruction is a critical instruction according to the key instruction identifier, and operates the data corresponding to the second operation instruction in the memory according to a priority strategy.