CN104901707B - Signal anti-interference device in electronic device detection - Google Patents
Signal anti-interference device in electronic device detection Download PDFInfo
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Abstract
The invention discloses the signal anti-interference device in a kind of detection of electronic device, the signal that electronic device occurs is passed sequentially through the filtering block isolating circuit of concatenation, envelope demodulation comparison circuit, FPGA decoding diagnosis apparatuss, the quality of electronic device is judged with this；Described filtering block isolating circuit is made up of with the main road resistance Rb that connects after a shunt capacitance Ca parallel connection a bypass resistance Ra, and envelope demodulation comparison circuit is made up of shunt capacitance Cb and main road electric capacity Cd；Bypass resistance Rb, shunt capacitance Ca, shunt capacitance Cb have common common port.Anti-jamming effectiveness of the present invention is good, judges that the reliability of electronic device quality is high.
Description
Technical field
The present invention relates to the detection of electronic device signal and signal processing apparatus.
Background technology
The performance parameter of the electronic devices such as electronic diode, microelectronic chip needs professional instrument or circuit to test,
And compare with the data of standard, the quality of electronic device is judged with this.
A kind of number of patent application be 2013101898949 disclosure of the invention multichannel interference signal generator and interference
Signal generating method, it include that the interference parameter for carrying out interference signal parameters setting arranges equipment, is used for producing all kinds of array moulds
Intend the interference signal generator of signal and the signal output apparatus of the output for multichannel interference signal, interference parameter arranges equipment
It is sequentially connected interference signal generator and signal output apparatus；Described interference parameter arranges equipment to be used for arranging interference signal ginseng
Number, interference signal parameters include interference strength, array format, array element distance and array amplitude phase error；Interference signal generator bag
Include parameter setting circuit, multichannel baseband signal generation circuit and the power adjusting circuit being sequentially connected；Signal output apparatus bag
Include digital to analog converter and up-convert channel.The equipment of the invention is excessively complicated, and cost is more expensive.
Number of patent application is that 2013100181407 bright discloses the anti-interference digital sample device of multichannel, including：As
The analog-digital converter group that the ADC of dry multidiameter delay is constituted, and the FPGA connected with analog-digital converter group, the modulus are turned
The analogue signal of the multi-channel parallel that multi-channel parallel radio-frequency front-end is received by parallel operation group, is converted to the numeral for being available for FPGA to process
Signal, the analog-digital converter group also connect the clock chip of a sampled clock signal for providing adjustable delay for ADC, when described
The sampled clock signal of clock chip is divided into multidiameter delay and exports gives ADC chips.The component of the device is fully open, it is difficult to
Consult and use in actual test.
Content of the invention
Goal of the invention：
The signal provided in the electronic device detection that a kind of antinoise signal interference performance is strong, the fine or not accuracy of differentiation is high is anti-interference
Device.
Technical scheme：
The present invention provides the signal anti-interference device in a kind of electronic device detection, the signal of communication that electronic device is occurred
The filtering block isolating circuit of concatenation, envelope demodulation comparison circuit, FPGA decoding diagnosis apparatuss are passed sequentially through, electronic device is finally judged
Quality.
Described filtering block isolating circuit is by a bypass resistance Ra and a main road of connecting after a shunt capacitance Ca parallel connection
Resistance Rb is constituted, and envelope demodulation comparison circuit is made up of shunt capacitance Cb and main road electric capacity Cd, bypass resistance Rb, bypass electricity
Hold Ca, shunt capacitance Cb and there is common common port（Or earth terminal）.
The value of Ca, Ra, Rb be respectively 100pf, 1000 ohm, 1000 ohm；
The value of Cb, Cd is respectively 10pf and 0.1 μ f.
The jamproof system of the present invention is mainly used in correct process chip returned data, due to the RF identification chip that commonly uses
Communication be communication, communication protocol be ISO/IEC14443 agreements.
In the present invention, the communication data format of signal of communication is preferably Manchester's code mode.For chip returns letter
Number first we can pass through simple filtering block isolating circuit, then through envelope demodulation comparison circuit, the envelope of return signal, have
The envelope of data shows as the waveform of height height, and the envelope of no data then shows as the waveform of high level.
In the system, it is preferred that emphasis is FPGA processes interference sections.Before the data 1 of Manchester's code are expressed as data wire
It is high level during 50% bit period, is low level afterwards during 50% bit period.Data 0 are low during being expressed as front 50% bit period
Level, is low level afterwards during 50% bit period.
Description of the drawings
Fig. 1 is a circuit connection diagram of the present invention；
In figure, 1- diodes（Electronic device）；2- input signals；3- shunt capacitances Ca；4- bypass resistance Ra；5- bypass electricity
Hold Cb；6- main road electric capacity Cd；7- FPGA decode diagnosis apparatuss；8- output signals；9- envelope demodulation comparison circuits；10- main road resistance
Rb；11- filters block isolating circuit；12- common ports.
Specific embodiment
In the system as shown in Figure 1, the input signal 2 that Schottky diode 1 is occurred passes sequentially through the filtering of concatenation
Block isolating circuit 11, envelope demodulation comparison circuit 9, FPGA decoding diagnosis apparatuss 7, judge its quality with this；Described filtering is every straight electricity
Road 11 is made up of with the main road resistance Rb10 that connects after a shunt capacitance Ca3 parallel connection a bypass resistance Ra4, envelope demodulation
Comparison circuit 9 is made up of shunt capacitance Cb5 and main road electric capacity Cd6, bypass resistance Rb10, shunt capacitance Ca3, shunt capacitance
Cb5 has common common port 12.
The value of Ca3, Ra4, Rb10 be respectively 100pf, 1000 ohm and 1000 ohm, the value of Cb5, Cd6 is respectively
10pf and 0.1 μ f.
We can be according to communication protocol, during a bit position, and FPGA 8 data points of sampling, this 8 points are evenly distributed,
If front 4 points are high level, four points are flat for low spot afterwards, then we judge this data for 1, if front 4 points are low level,
Four points are flat for high point afterwards, then be judged as data 0.Because we are according to communication protocol, then have been known for all should be correct
The data of return.If within the cycle that should be data 1, if front 4 points are height, being judged as 1.In the cycle that should be data 0
Interior, if rear four points are height, it is judged as 0.So just whole returned datas can be correctly recognized, be compared with real data afterwards,
Judge whether the return of chip is correct.FPGA receives signal, carries out sampling analyses according to communication protocol to signal, with positive exact figures
According to comparing, comparative result is obtained, and chip quality is judged with this.
Claims (5)
1. the signal anti-interference device during a kind of electronic device is detected, it is characterised in that：By electronic device（1）The input letter of generation
Number（2）Pass sequentially through the filtering block isolating circuit of concatenation（11）, envelope demodulation comparison circuit（9）, FPGA decoding diagnosis apparatuss（7）, with
This judges electronic device（1）Quality；Described filtering block isolating circuit（11）By a bypass resistance Ra（4）With a bypass electricity
Hold Ca（3）Connect after parallel connection a main road resistance Rb（10）Constitute, envelope demodulation comparison circuit（9）By shunt capacitance Cb
（5）With main road electric capacity Cd（6）Constitute.
2. the signal anti-interference device during electronic device as claimed in claim 1 is detected, it is characterised in that：Bypass resistance Ra
（4）, shunt capacitance Ca（3）, shunt capacitance Cb（5）There is common common port.
3. the signal anti-interference device during electronic device as claimed in claim 1 is detected, it is characterised in that：Described Ca, Ra,
The value of Rb be respectively 100pf, 1000 ohm and 1000 ohm.
4. the signal anti-interference device during electronic device as claimed in claim 1 is detected, it is characterised in that：Described Cb, Cd
Value be respectively 10pf and 0.1 μ f.
5. the signal anti-interference device during electronic device as claimed in claim 1 is detected, it is characterised in that：Signal of communication logical
Letter data form is Manchester's code mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510183799.7A CN104901707B (en) | 2015-04-18 | 2015-04-18 | Signal anti-interference device in electronic device detection |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510183799.7A CN104901707B (en) | 2015-04-18 | 2015-04-18 | Signal anti-interference device in electronic device detection |
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| CN104901707A CN104901707A (en) | 2015-09-09 |
| CN104901707B true CN104901707B (en) | 2017-03-15 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4996691A (en) * | 1988-09-21 | 1991-02-26 | Northern Telecom Limited | Integrated circuit testing method and apparatus and integrated circuit devices for use therewith |
| CN202210154U (en) * | 2011-06-22 | 2012-05-02 | 成都信息工程学院 | Weather radar test and fault detection device |
| CN102539970A (en) * | 2012-01-04 | 2012-07-04 | 华北电网有限公司计量中心 | RFID equipment testing method and system |
| CN203025317U (en) * | 2012-09-10 | 2013-06-26 | 大唐微电子技术有限公司 | Contactless smart card chip test device |
-
2015
- 2015-04-18 CN CN201510183799.7A patent/CN104901707B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4996691A (en) * | 1988-09-21 | 1991-02-26 | Northern Telecom Limited | Integrated circuit testing method and apparatus and integrated circuit devices for use therewith |
| CN202210154U (en) * | 2011-06-22 | 2012-05-02 | 成都信息工程学院 | Weather radar test and fault detection device |
| CN102539970A (en) * | 2012-01-04 | 2012-07-04 | 华北电网有限公司计量中心 | RFID equipment testing method and system |
| CN203025317U (en) * | 2012-09-10 | 2013-06-26 | 大唐微电子技术有限公司 | Contactless smart card chip test device |
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| CN104901707A (en) | 2015-09-09 |
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