CN104900516B - A kind of formation method of nickel silicide - Google Patents

Abstract

The invention discloses a kind of forming method of nickel silicide; by using stress technique; using protective layers of the opposite TiN of stress as NiPt on NMOS and PMOS; in follow-up nickel silicide forming process; different stress is memorized by reaction and phase transformation; the nickel silicide to be formed is set to apply tension to NMOS raceway grooves; compression is applied to PMOS raceway grooves; so as to avoid in the forming process of metal silicide; negative effect caused by introducing stressor layers, improve the performance of device.

Description

A kind of formation method of nickel silicide

technical field

The invention relates to the technical field of semiconductor integrated circuit manufacturing, and more specifically, to a method for forming nickel silicide using stress technology.

Background technique

In semiconductor manufacturing technology, metal silicide is widely used in source/drain contacts and gate contacts to reduce contact resistance due to its low resistivity and good adhesion with other materials. Metals with high melting points such as Ti, Co, Ni, etc. can react with silicon to form metal silicides with low resistivity through one-step or multi-step annealing process. With the continuous improvement of the semiconductor process level, especially at the technology node of 45nm and below, in order to obtain lower contact resistance, nickel and nickel alloys (such as NiPt) have become the main materials for forming metal silicides.

As the miniaturization of the feature size of VLSI continues, the size of field effect transistors is also getting smaller and faster, and the operation speed is also getting faster. How to effectively improve electron transport performance and improve the driving current of circuit components is becoming increasingly important. By increasing the carrier mobility in the channel region, the driving current of the CMOS device can be increased, and the performance of the device can be improved. An effective mechanism to increase carrier mobility is to create stress in the channel region.

Generally speaking, the mobility of electrons in silicon increases with the increase of tensile stress along the electron migration direction, and decreases with the increase of compressive stress; on the contrary, the mobility of positively charged holes in silicon increases with the It increases with the increase of compressive stress in the moving direction of the hole, and decreases with the increase of tensile stress. Therefore, the hole mobility of PMOS and the electron mobility of NMOS can be improved respectively by introducing appropriate compressive stress and tensile stress in the channel. For example, materials with compressive stress are used in the manufacturing process of PMOS devices, while materials with tensile stress are used in NMOS devices to apply appropriate stress to the channel region, thereby increasing the mobility of carriers.

In the above-mentioned process of forming such as Ni metal silicide, the prior art generally covers a NiPt metal layer on the NMOS and PMOS devices, and covers a TiN layer on the NiPt metal layer as a protective layer (cap layer) of NiPt, Furthermore, nickel and silicon are reacted to form nickel silicide with low resistivity through an annealing process. A TiN protective layer can be used to prevent NiPt from being oxidized.

However, the above-mentioned existing Ni silicide formation process adopts TiN with a single stress to cover NMOS and PMOS as a protective layer of NiPt, and TiN with a single stress (tensile stress or compressive stress) can only be applied to NMOS or PMOS. PMOS contributes to the improvement of electron mobility or hole mobility of one of them, but in the case of benefiting one of them, it will adversely affect the electrical performance of the other device.

Therefore, the existing Ni silicide formation process does not take into account the negative effect brought by the TiN stress layer introduced during the formation of the metal silicide, and needs to be optimized.

Contents of the invention

The purpose of the present invention is to overcome the above-mentioned defects in the prior art and provide a new method for forming nickel silicide, which avoids the negative effect caused by introducing a stress layer during the formation of metal silicide.

To achieve the above object, the technical scheme of the present invention is as follows:

A method for forming nickel silicide, comprising the steps of:

Step S01: providing a semiconductor substrate formed with NMOS and PMOS, depositing a SiN layer as a metal silicide barrier layer, and selectively removing the SiN in the metal silicide region to be formed;

Step S02: sequentially depositing a NiPt layer and a compressive first TiN layer, and selectively removing the first TiN layer on the NMOS;

Step S03: Depositing a second TiN layer with tensile stress, and selectively removing the second TiN layer on the PMOS;

Step S04: performing the first annealing to form the first nickel silicide in the area where the metal silicide needs to be formed;

Step S05: removing the first and second TiN layers, unreacted NiPt layer and SiN layer;

Step S06: performing a second annealing to form a second nickel silicide in the area where metal silicide needs to be formed;

Among them, during the formation of nickel silicide, different stresses are memorized through reaction and phase transition, so that the formed nickel silicide applies tensile stress to the NMOS channel and compressive stress to the PMOS channel.

Preferably, the first nickel silicide is Ni ₂ Si.

Preferably, the second nickel silicide is NiSi.

Preferably, the content of Pt in the NiPt ranges from 0% to 15%.

Preferably, the NiPt has a thickness ranging from 30 to 300 angstroms.

Preferably, the first and second TiN layers have different thicknesses.

Preferably, the thickness of the first TiN layer ranges from 20 to 300 angstroms.

Preferably, the thickness of the second TiN layer ranges from 20 to 300 angstroms.

Preferably, in step S03 and step S04, after depositing the second TiN layer, keep the second TiN layer on the PMOS, and directly perform the first annealing.

It can be seen from the above technical scheme that the present invention adopts stress technology to use TiN with opposite stress on NMOS and PMOS as the protective layer of NiPt. Remember, the formed nickel silicide can apply tensile stress to the NMOS channel and compressive stress to the PMOS channel, thereby avoiding the negative effect caused by the introduction of the stress layer during the formation of the metal silicide, and improving the device performance.

Description of drawings

Fig. 1 is the flow chart of the formation method of a kind of nickel silicide of the present invention;

2 to 7 are schematic diagrams of the process structure of forming nickel silicide according to the method of FIG. 1 in a preferred embodiment of the present invention.

Detailed ways

The specific embodiment of the present invention will be further described in detail below in conjunction with the accompanying drawings.

It should be noted that, in the following specific embodiments, when describing the embodiments of the present invention in detail, in order to clearly show the structure of the present invention for the convenience of description, the structures in the drawings are not drawn according to the general scale, and are drawn Partial magnification, deformation and simplification are included, therefore, it should be avoided to be interpreted as a limitation of the present invention.

In the following specific embodiments of the present invention, please refer to FIG. 1 , which is a flowchart of a method for forming nickel silicide according to the present invention. Meanwhile, please refer to FIGS. 2-7 , which are schematic diagrams of the process structure of forming nickel silicide according to the method of FIG. 1 in a preferred embodiment of the present invention. The device structures formed in FIGS. 2 to 7 may correspond to the steps in FIG. 1 . As shown in Figure 1, the formation method of a kind of nickel silicide of the present invention comprises the following steps:

As shown in block 01, step S01: providing a semiconductor substrate formed with NMOS and PMOS, depositing a SiN layer as a metal silicide barrier layer, and selectively removing SiN in a region where metal silicide needs to be formed.

See Figure 2. Firstly, NMOS and PMOS devices are formed on the semiconductor substrate 1 , including forming structures such as STI (Shallow Trench Isolation), gate 2 , source/drain, and the like. The substrate 1 can be implemented by a conventional silicon wafer, and the gate 2 can be a polysilicon gate. Then, a layer of SiN layer 3 is deposited on the surface of the substrate and the NMOS and PMOS devices as a metal silicide barrier layer (SAB hard mask).

See Figure 3. Then, the SiN layer can be patterned by using known photolithography and etching processes. For example, by photolithography, the pattern is transferred to SiN, and then dry-etched to selectively remove the SiN that needs to form the metal silicide region, that is, to remove the SiN of the gate and source/drain regions (the diagram is simplified, The SiN layer graphics have been completely omitted, please avoid misunderstanding). This area will be used to form metal contacts.

As shown in block 02, step S02: sequentially depositing a NiPt layer and a compressive first TiN layer, and selectively removing the first TiN layer on the NMOS.

See Figure 4. Next, a NiPt layer 4 and a first TiN layer 5 with compressive stress are sequentially deposited to cover the NMOS and PMOS devices. The NiPt layer 4 is used to subsequently react Ni therein with Si in the polysilicon gate and Si in the source/drain region in an annealed state to form nickel metal silicide. The first TiN layer 5 serves as a caplayer for the NiPt layer 4 . As an optional implementation, the content of Pt in the NiPt may range from 0% to 15%, such as 0%, 5%, 10% or 15%. That is, NiPt can exist in the form of pure nickel. As an optional implementation manner, the thickness of the NiPt layer 4 may range from 30 to 300 angstroms, such as 30 angstroms, 100 angstroms, 200 angstroms or 300 angstroms. The thickness of the first TiN layer 5 may range from 20 to 300 angstroms.

See Figure 5. Next, the first TiN layer 5 can be patterned by using known photolithography and etching processes. For example, the pattern is transferred to the first TiN layer 5 by photolithography, and then the first TiN layer on the NMOS is selectively removed by dry etching, leaving only the first TiN layer 5 with compressive stress on the PMOS.

As shown in block 03, step S03: depositing a second TiN layer with tensile stress, and selectively removing the second TiN layer on the PMOS.

See Figure 6. Next, continue to deposit a second TiN layer 6 with tensile stress to cover the NMOS and PMOS device regions. As an optional implementation manner, the thickness of the second TiN layer 6 may range from 20 to 300 angstroms. Moreover, the thicknesses of the first and second TiN layers 5 and 6 may be different or the same.

See Figure 7. Next, the second TiN layer 6 can be patterned by using known photolithography and etching processes. For example, the pattern is transferred to the second TiN layer 6 by photolithography, and then the second TiN layer on the PMOS is selectively removed by dry etching, leaving only the second TiN layer 6 with tensile stress on the NMOS. In this way, a layer of the second TiN layer 6 with tensile stress and the first TiN layer 5 with compressive stress are respectively covered in the NMOS and PMOS device regions.

As shown in block 04, step S04: perform the first annealing, and form the first nickel silicide in the area where the metal silicide needs to be formed.

Next, the first nickel silicide is formed in the area where the metal silicide needs to be formed by performing the first annealing. That is, through the first annealing, the nickel in the NiPt reacts with the silicon in the polysilicon gate and source/drain regions to form the first nickel silicide. Preferably, the first nickel silicide may be Ni ₂ Si.

As shown in block 05, step S05: removing the first and second TiN layers, the unreacted NiPt layer and the SiN layer.

Next, after the first annealing, the first and second TiN layers, the unreacted NiPt layer and the SiN layer can be removed from the surface of the NMOS and PMOS devices by using known techniques.

As shown in block 06, step S06: perform a second annealing, and form a second nickel silicide in the area where metal silicide needs to be formed.

Next, the second nickel silicide is further formed in the area where the metal silicide needs to be formed by performing the second annealing. That is, through the second annealing, the first nickel silicide formed on the surface layer of the polysilicon gate and the source/drain region is further transformed into the second nickel silicide. Preferably, the second nickel silicide may be NiSi.

As an optional implementation manner, in the above step S03 and step S04, after depositing the second TiN layer, the second TiN layer on the PMOS can also be left without removal treatment, and the first annealing can be performed directly. In this state, the performance of the device will not be significantly affected, but a process step can be saved.

It should be noted that, in the above step S02 and step S03, the second TiN layer with tensile stress may also be deposited first, and the second TiN layer on the PMOS is selectively removed; then, the second TiN layer with compressive stress is deposited. a TiN layer, and selectively remove the first TiN layer on the NMOS. That is, the order of these two steps can be reversed.

To sum up, the present invention adopts stress-opposite TiN as the protective layer of NiPt on NMOS and PMOS by applying stress technology. During the subsequent formation of nickel silicide, different stresses are memorized through reactions and phase transitions. The formed nickel silicide can apply tensile stress to the NMOS channel and compressive stress to the PMOS channel, thereby avoiding the negative effect caused by the introduction of the stress layer during the formation of the metal silicide, and improving the performance of the device .

The above are only preferred embodiments of the present invention, and the embodiments are not intended to limit the scope of patent protection of the present invention. Therefore, all equivalent structural changes made by using the description and accompanying drawings of the present invention should be included in the same way. Within the protection scope of the present invention.

Claims (9)

1. a kind of forming method of nickel silicide, it is characterised in that comprise the following steps：

Step S01：A Semiconductor substrate formed with NMOS and PMOS is provided, one SiN layer of deposition stops as metal silicide Layer, and optionally removal needs to form the SiN of metal silicide region；

Step S02：A NiPt layers and the TiN layer of compression first are sequentially depositing, and optionally removes the first TiN on NMOS Layer；

Step S03：Second TiN layer of tension is deposited, and optionally removes the second TiN layer on PMOS；

Step S04：First time annealing is carried out, is needing to form the first nickel silicide of the region of metal silicide formation；

Step S05：Remove first, second TiN layer, responseless NiPt layers and SiN layer；

Step S06：Carry out second to anneal, needing to form the second nickel silicide of the region of metal silicide formation；

Wherein, in nickel silicide forming process, different stress is memorized by reaction and phase transformation, makes the nickel to be formed Silicide applies tension to NMOS raceway grooves, applies compression to PMOS raceway grooves.

2. the forming method of nickel silicide according to claim 1, it is characterised in that first nickel silicide is Ni₂Si。

3. the forming method of nickel silicide according to claim 1, it is characterised in that second nickel silicide is NiSi。

4. the forming method of nickel silicide according to claim 1, it is characterised in that Pt content range in the NiPt For 0~15%.

5. the forming method of the nickel silicide according to claim 1 or 4, it is characterised in that the thickness range of the NiPt For 30~300 angstroms.

6. the forming method of nickel silicide according to claim 1, it is characterised in that the thickness of first, second TiN layer Degree is different.

7. the forming method of the nickel silicide according to claim 1 or 6, it is characterised in that the thickness of first TiN layer Scope is 20~300 angstroms.

8. the forming method of the nickel silicide according to claim 1 or 6, it is characterised in that the thickness of second TiN layer Scope is 20~300 angstroms.

9. the forming method of nickel silicide according to claim 1, it is characterised in that in step S03 and step S04, After depositing the second TiN layer, retain the second TiN layer on PMOS, directly carry out first time annealing.